drv_usart_v2.c 35 KB

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  1. /*
  2. * Copyright (c) 2006-2024, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024-03-19 Evlers first implementation
  9. */
  10. #include "drv_usart_v2.h"
  11. #ifdef RT_USING_SERIAL_V2
  12. #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \
  13. !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
  14. !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && \
  15. !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7)
  16. #error "Please define at least one UARTx"
  17. #endif
  18. #include <rtdevice.h>
  19. enum {
  20. #ifdef BSP_USING_UART0
  21. UART0_INDEX,
  22. #endif
  23. #ifdef BSP_USING_UART1
  24. UART1_INDEX,
  25. #endif
  26. #ifdef BSP_USING_UART2
  27. UART2_INDEX,
  28. #endif
  29. #ifdef BSP_USING_UART3
  30. UART3_INDEX,
  31. #endif
  32. #ifdef BSP_USING_UART4
  33. UART4_INDEX,
  34. #endif
  35. #ifdef BSP_USING_UART5
  36. UART5_INDEX,
  37. #endif
  38. #ifdef BSP_USING_UART6
  39. UART6_INDEX,
  40. #endif
  41. #ifdef BSP_USING_UART7
  42. UART7_INDEX,
  43. #endif
  44. };
  45. static struct gd32_uart uart_obj[] = {
  46. #ifdef BSP_USING_UART0
  47. {
  48. "uart0",
  49. USART0, // uart peripheral index
  50. USART0_IRQn, // uart iqrn
  51. RCU_USART0, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock
  52. #if defined SOC_SERIES_GD32F4xx
  53. GPIOA, GPIO_AF_7, GPIO_PIN_9, // tx port, tx alternate, tx pin
  54. GPIOA, GPIO_AF_7, GPIO_PIN_10, // rx port, rx alternate, rx pin
  55. #else
  56. GPIOA, GPIO_PIN_9, // tx port, tx pin
  57. GPIOA, GPIO_PIN_10, // rx port, rx pin
  58. #endif
  59. #ifdef BSP_UART0_RX_USING_DMA
  60. .dma.rx = DRV_DMA_CONFIG(1, 5, 4),
  61. #endif
  62. #ifdef BSP_UART0_TX_USING_DMA
  63. .dma.tx = DRV_DMA_CONFIG(1, 7, 4),
  64. #endif
  65. },
  66. #endif
  67. #ifdef BSP_USING_UART1
  68. {
  69. "uart1",
  70. USART1, // uart peripheral index
  71. USART1_IRQn, // uart iqrn
  72. RCU_USART1, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock
  73. #if defined SOC_SERIES_GD32F4xx
  74. GPIOA, GPIO_AF_7, GPIO_PIN_2, // tx port, tx alternate, tx pin
  75. GPIOA, GPIO_AF_7, GPIO_PIN_3, // rx port, rx alternate, rx pin
  76. #else
  77. GPIOA, GPIO_PIN_2, // tx port, tx pin
  78. GPIOA, GPIO_PIN_3, // rx port, rx pin
  79. #endif
  80. #ifdef BSP_UART1_RX_USING_DMA
  81. .dma.rx = DRV_DMA_CONFIG(0, 5, 4),
  82. #endif
  83. #ifdef BSP_UART1_TX_USING_DMA
  84. .dma.tx = DRV_DMA_CONFIG(0, 6, 4),
  85. #endif
  86. },
  87. #endif
  88. #ifdef BSP_USING_UART2
  89. {
  90. "uart2",
  91. USART2, // uart peripheral index
  92. USART2_IRQn, // uart iqrn
  93. RCU_USART2, RCU_GPIOB, RCU_GPIOB, // periph clock, tx gpio clock, rt gpio clock
  94. #if defined SOC_SERIES_GD32F4xx
  95. GPIOB, GPIO_AF_7, GPIO_PIN_10, // tx port, tx alternate, tx pin
  96. GPIOB, GPIO_AF_7, GPIO_PIN_11, // rx port, rx alternate, rx pin
  97. #else
  98. GPIOB, GPIO_PIN_10, // tx port, tx pin
  99. GPIOB, GPIO_PIN_11, // rx port, rx pin
  100. #endif
  101. #ifdef BSP_UART2_RX_USING_DMA
  102. .dma.rx = DRV_DMA_CONFIG(0, 1, 4),
  103. #endif
  104. #ifdef BSP_UART2_TX_USING_DMA
  105. .dma.tx = DRV_DMA_CONFIG(0, 3, 4),
  106. #endif
  107. },
  108. #endif
  109. #ifdef BSP_USING_UART3
  110. {
  111. "uart3",
  112. UART3, // uart peripheral index
  113. UART3_IRQn, // uart iqrn
  114. RCU_UART3, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock
  115. #if defined SOC_SERIES_GD32F4xx
  116. GPIOC, GPIO_AF_8, GPIO_PIN_10, // tx port, tx alternate, tx pin
  117. GPIOC, GPIO_AF_8, GPIO_PIN_11, // rx port, rx alternate, rx pin
  118. #else
  119. GPIOC, GPIO_PIN_10, // tx port, tx pin
  120. GPIOC, GPIO_PIN_11, // rx port, rx pin
  121. #endif
  122. #ifdef BSP_UART3_RX_USING_DMA
  123. .dma.rx = DRV_DMA_CONFIG(0, 2, 4),
  124. #endif
  125. #ifdef BSP_UART3_TX_USING_DMA
  126. .dma.tx = DRV_DMA_CONFIG(0, 4, 4),
  127. #endif
  128. },
  129. #endif
  130. #ifdef BSP_USING_UART4
  131. {
  132. "uart4",
  133. UART4, // uart peripheral index
  134. UART4_IRQn, // uart iqrn
  135. RCU_UART4, RCU_GPIOC, RCU_GPIOD, // periph clock, tx gpio clock, rt gpio clock
  136. #if defined SOC_SERIES_GD32F4xx
  137. GPIOC, GPIO_AF_8, GPIO_PIN_12, // tx port, tx alternate, tx pin
  138. GPIOD, GPIO_AF_8, GPIO_PIN_2, // rx port, rx alternate, rx pin
  139. #else
  140. GPIOC, GPIO_PIN_12, // tx port, tx pin
  141. GPIOD, GPIO_PIN_2, // rx port, rx pin
  142. #endif
  143. #ifdef BSP_UART4_RX_USING_DMA
  144. .dma.rx = DRV_DMA_CONFIG(0, 0, 4),
  145. #endif
  146. #ifdef BSP_UART4_TX_USING_DMA
  147. .dma.tx = DRV_DMA_CONFIG(0, 7, 4),
  148. #endif
  149. },
  150. #endif
  151. #ifdef BSP_USING_UART5
  152. {
  153. "uart5",
  154. USART5, // uart peripheral index
  155. USART5_IRQn, // uart iqrn
  156. RCU_USART5, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock
  157. #if defined SOC_SERIES_GD32F4xx
  158. GPIOC, GPIO_AF_8, GPIO_PIN_6, // tx port, tx alternate, tx pin
  159. GPIOC, GPIO_AF_8, GPIO_PIN_7, // rx port, rx alternate, rx pin
  160. #else
  161. GPIOC, GPIO_PIN_6, // tx port, tx pin
  162. GPIOC, GPIO_PIN_7, // rx port, rx pin
  163. #endif
  164. #ifdef BSP_UART5_RX_USING_DMA
  165. .dma.rx = DRV_DMA_CONFIG(1, 1, 5),
  166. #endif
  167. #ifdef BSP_UART5_TX_USING_DMA
  168. .dma.tx = DRV_DMA_CONFIG(1, 7, 5),
  169. #endif
  170. },
  171. #endif
  172. #ifdef BSP_USING_UART6
  173. {
  174. "uart6",
  175. UART6, // uart peripheral index
  176. UART6_IRQn, // uart iqrn
  177. RCU_UART6, RCU_GPIOE, RCU_GPIOE, // periph clock, tx gpio clock, rt gpio clock
  178. #if defined SOC_SERIES_GD32F4xx
  179. GPIOE, GPIO_AF_8, GPIO_PIN_7, // tx port, tx alternate, tx pin
  180. GPIOE, GPIO_AF_8, GPIO_PIN_8, // rx port, rx alternate, rx pin
  181. #else
  182. GPIOE, GPIO_PIN_7, // tx port, tx pin
  183. GPIOE, GPIO_PIN_8, // rx port, rx pin
  184. #endif
  185. #ifdef BSP_UART6_RX_USING_DMA
  186. .dma.rx = DRV_DMA_CONFIG(0, 3, 5),
  187. #endif
  188. #ifdef BSP_UART6_TX_USING_DMA
  189. .dma.tx = DRV_DMA_CONFIG(0, 1, 5),
  190. #endif
  191. },
  192. #endif
  193. #ifdef BSP_USING_UART7
  194. {
  195. "uart7",
  196. UART7, // uart peripheral index
  197. UART7_IRQn, // uart iqrn
  198. RCU_UART7, RCU_GPIOE, RCU_GPIOE, // periph clock, tx gpio clock, rt gpio clock
  199. #if defined SOC_SERIES_GD32F4xx
  200. GPIOE, GPIO_AF_8, GPIO_PIN_0, // tx port, tx alternate, tx pin
  201. GPIOE, GPIO_AF_8, GPIO_PIN_1, // rx port, rx alternate, rx pin
  202. #else
  203. GPIOE, GPIO_PIN_0, // tx port, tx pin
  204. GPIOE, GPIO_PIN_1, // rx port, rx pin
  205. #endif
  206. #ifdef BSP_UART7_RX_USING_DMA
  207. .dma.rx = DRV_DMA_CONFIG(0, 6, 5),
  208. #endif
  209. #ifdef BSP_UART7_TX_USING_DMA
  210. .dma.tx = DRV_DMA_CONFIG(0, 0, 5),
  211. #endif
  212. },
  213. #endif
  214. };
  215. #ifdef RT_SERIAL_USING_DMA
  216. static void dma_recv_isr (struct rt_serial_device *serial)
  217. {
  218. struct gd32_uart *uart;
  219. rt_size_t recv_len, counter;
  220. rt_base_t level;
  221. RT_ASSERT(serial != RT_NULL);
  222. uart = rt_container_of(serial, struct gd32_uart, serial);
  223. recv_len = 0;
  224. level = rt_hw_interrupt_disable();
  225. counter = dma_transfer_number_get(uart->dma.rx.periph, uart->dma.rx.channel);
  226. if (counter <= uart->dma.last_index)
  227. {
  228. recv_len = uart->dma.last_index - counter;
  229. }
  230. else
  231. {
  232. recv_len = serial->config.dma_ping_bufsz + uart->dma.last_index - counter;
  233. }
  234. uart->dma.last_index = counter;
  235. rt_hw_interrupt_enable(level);
  236. if (recv_len)
  237. {
  238. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  239. }
  240. }
  241. #endif
  242. static void usart_isr (struct rt_serial_device *serial)
  243. {
  244. struct gd32_uart *uart;
  245. RT_ASSERT(serial != RT_NULL);
  246. uart = rt_container_of(serial, struct gd32_uart, serial);
  247. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_RBNE) != RESET)
  248. {
  249. struct rt_serial_rx_fifo *rx_fifo;
  250. rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
  251. RT_ASSERT(rx_fifo != RT_NULL);
  252. char chr = usart_data_receive(uart->periph);
  253. rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, &chr);
  254. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  255. /* Clear RXNE interrupt flag */
  256. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_RBNE);
  257. }
  258. else if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_TBE) != RESET)
  259. {
  260. rt_uint8_t put_char = 0;
  261. if (rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GETC, &put_char) == RT_EOK)
  262. {
  263. usart_data_transmit(uart->periph, put_char);
  264. }
  265. else
  266. {
  267. usart_interrupt_disable(uart->periph, USART_INT_TBE);
  268. usart_interrupt_enable(uart->periph, USART_INT_TC);
  269. }
  270. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_TBE);
  271. }
  272. else if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_TC) != RESET)
  273. {
  274. usart_interrupt_disable(uart->periph, USART_INT_TC);
  275. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  276. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_TC);
  277. }
  278. #ifdef RT_SERIAL_USING_DMA
  279. else if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_IDLE) != RESET)
  280. {
  281. volatile uint8_t data = (uint8_t)usart_data_receive(uart->periph);
  282. dma_recv_isr(serial);
  283. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_IDLE);
  284. }
  285. #endif
  286. else
  287. {
  288. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_ERR_ORERR) != RESET)
  289. {
  290. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_ERR_ORERR);
  291. }
  292. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_ERR_NERR) != RESET)
  293. {
  294. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_ERR_NERR);
  295. }
  296. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_ERR_FERR) != RESET)
  297. {
  298. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_ERR_FERR);
  299. }
  300. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_RBNE_ORERR) != RESET)
  301. {
  302. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_RBNE_ORERR);
  303. }
  304. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_PERR) != RESET)
  305. {
  306. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_PERR);
  307. }
  308. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_CTS) != RESET)
  309. {
  310. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_CTS);
  311. }
  312. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_LBD) != RESET)
  313. {
  314. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_LBD);
  315. }
  316. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_EB) != RESET)
  317. {
  318. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_EB);
  319. }
  320. if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_RT) != RESET)
  321. {
  322. usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_RT);
  323. }
  324. }
  325. }
  326. #if defined(BSP_UART0_RX_USING_DMA) || \
  327. defined(BSP_UART1_RX_USING_DMA) || \
  328. defined(BSP_UART2_RX_USING_DMA) || \
  329. defined(BSP_UART3_RX_USING_DMA) || \
  330. defined(BSP_UART4_RX_USING_DMA) || \
  331. defined(BSP_UART5_RX_USING_DMA) || \
  332. defined(BSP_UART6_RX_USING_DMA) || \
  333. defined(BSP_UART7_RX_USING_DMA)
  334. static void dma_rx_isr (struct rt_serial_device *serial)
  335. {
  336. struct gd32_uart *uart;
  337. RT_ASSERT(serial != RT_NULL);
  338. uart = rt_container_of(serial, struct gd32_uart, serial);
  339. if ((dma_interrupt_flag_get(uart->dma.rx.periph, uart->dma.rx.channel, DMA_INT_FLAG_HTF) != RESET) ||
  340. (dma_interrupt_flag_get(uart->dma.rx.periph, uart->dma.rx.channel, DMA_INT_FLAG_FTF) != RESET))
  341. {
  342. dma_recv_isr(serial);
  343. /* clear dma flag */
  344. dma_interrupt_flag_clear(uart->dma.rx.periph, uart->dma.rx.channel, DMA_INT_FLAG_HTF);
  345. dma_interrupt_flag_clear(uart->dma.rx.periph, uart->dma.rx.channel, DMA_INT_FLAG_FTF);
  346. }
  347. }
  348. #endif
  349. #if defined(BSP_UART0_TX_USING_DMA) || \
  350. defined(BSP_UART1_TX_USING_DMA) || \
  351. defined(BSP_UART2_TX_USING_DMA) || \
  352. defined(BSP_UART3_TX_USING_DMA) || \
  353. defined(BSP_UART4_TX_USING_DMA) || \
  354. defined(BSP_UART5_TX_USING_DMA) || \
  355. defined(BSP_UART6_TX_USING_DMA) || \
  356. defined(BSP_UART7_TX_USING_DMA)
  357. static void dma_tx_isr (struct rt_serial_device *serial)
  358. {
  359. struct gd32_uart *uart;
  360. RT_ASSERT(serial != RT_NULL);
  361. uart = rt_container_of(serial, struct gd32_uart, serial);
  362. if (dma_interrupt_flag_get(uart->dma.tx.periph, uart->dma.tx.channel, DMA_INT_FLAG_FTF) != RESET)
  363. {
  364. rt_size_t trans_total_index;
  365. /* clear dma flag */
  366. dma_interrupt_flag_clear(uart->dma.tx.periph, uart->dma.tx.channel, DMA_INT_FLAG_FTF);
  367. /* disable dma tx channel */
  368. dma_channel_disable(uart->dma.tx.periph, uart->dma.tx.channel);
  369. trans_total_index = dma_transfer_number_get(uart->dma.tx.periph, uart->dma.tx.channel);
  370. if (trans_total_index == 0)
  371. {
  372. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  373. }
  374. }
  375. }
  376. #endif
  377. #if defined(BSP_USING_UART0)
  378. void USART0_IRQHandler (void)
  379. {
  380. /* enter interrupt */
  381. rt_interrupt_enter();
  382. usart_isr(&uart_obj[UART0_INDEX].serial);
  383. /* leave interrupt */
  384. rt_interrupt_leave();
  385. }
  386. #endif /* BSP_USING_UART0 */
  387. #if defined(BSP_USING_UART1)
  388. void USART1_IRQHandler (void)
  389. {
  390. /* enter interrupt */
  391. rt_interrupt_enter();
  392. usart_isr(&uart_obj[UART1_INDEX].serial);
  393. /* leave interrupt */
  394. rt_interrupt_leave();
  395. }
  396. #endif /* BSP_USING_UART1 */
  397. #if defined(BSP_USING_UART2)
  398. void USART2_IRQHandler (void)
  399. {
  400. /* enter interrupt */
  401. rt_interrupt_enter();
  402. usart_isr(&uart_obj[UART2_INDEX].serial);
  403. /* leave interrupt */
  404. rt_interrupt_leave();
  405. }
  406. #endif /* BSP_USING_UART2 */
  407. #if defined(BSP_USING_UART3)
  408. void UART3_IRQHandler (void)
  409. {
  410. /* enter interrupt */
  411. rt_interrupt_enter();
  412. usart_isr(&uart_obj[UART3_INDEX].serial);
  413. /* leave interrupt */
  414. rt_interrupt_leave();
  415. }
  416. #endif /* BSP_USING_UART3 */
  417. #if defined(BSP_USING_UART4)
  418. void UART4_IRQHandler (void)
  419. {
  420. /* enter interrupt */
  421. rt_interrupt_enter();
  422. usart_isr(&uart_obj[UART4_INDEX].serial);
  423. /* leave interrupt */
  424. rt_interrupt_leave();
  425. }
  426. #endif /* BSP_USING_UART4 */
  427. #if defined(BSP_USING_UART5)
  428. void USART5_IRQHandler (void)
  429. {
  430. /* enter interrupt */
  431. rt_interrupt_enter();
  432. usart_isr(&uart_obj[UART5_INDEX].serial);
  433. /* leave interrupt */
  434. rt_interrupt_leave();
  435. }
  436. #endif /* BSP_USING_UART5 */
  437. #if defined(BSP_USING_UART6)
  438. void UART6_IRQHandler (void)
  439. {
  440. /* enter interrupt */
  441. rt_interrupt_enter();
  442. usart_isr(&uart_obj[UART6_INDEX].serial);
  443. /* leave interrupt */
  444. rt_interrupt_leave();
  445. }
  446. #endif /* BSP_USING_UART6 */
  447. #if defined(BSP_USING_UART7)
  448. void UART7_IRQHandler (void)
  449. {
  450. /* enter interrupt */
  451. rt_interrupt_enter();
  452. usart_isr(&uart_obj[UART7_INDEX].serial);
  453. /* leave interrupt */
  454. rt_interrupt_leave();
  455. }
  456. #endif /* BSP_USING_UART7 */
  457. #ifdef BSP_UART0_RX_USING_DMA
  458. void DMA1_Channel5_IRQHandler (void)
  459. {
  460. dma_rx_isr(&uart_obj[UART0_INDEX].serial);
  461. }
  462. #endif
  463. #ifdef BSP_UART0_TX_USING_DMA
  464. void DMA1_Channel7_IRQHandler (void)
  465. {
  466. dma_tx_isr(&uart_obj[UART0_INDEX].serial);
  467. }
  468. #endif
  469. #ifdef BSP_UART1_RX_USING_DMA
  470. void DMA0_Channel5_IRQHandler (void)
  471. {
  472. dma_rx_isr(&uart_obj[UART1_INDEX].serial);
  473. }
  474. #endif
  475. #ifdef BSP_UART1_TX_USING_DMA
  476. void DMA0_Channel6_IRQHandler (void)
  477. {
  478. dma_tx_isr(&uart_obj[UART1_INDEX].serial);
  479. }
  480. #endif
  481. #ifdef BSP_UART2_RX_USING_DMA
  482. void DMA0_Channel1_IRQHandler (void)
  483. {
  484. dma_rx_isr(&uart_obj[UART2_INDEX].serial);
  485. }
  486. #endif
  487. #ifdef BSP_UART2_TX_USING_DMA
  488. void DMA0_Channel3_IRQHandler (void)
  489. {
  490. dma_tx_isr(&uart_obj[UART2_INDEX].serial);
  491. }
  492. #endif
  493. #ifdef BSP_UART3_RX_USING_DMA
  494. void DMA0_Channel2_IRQHandler (void)
  495. {
  496. dma_rx_isr(&uart_obj[UART3_INDEX].serial);
  497. }
  498. #endif
  499. #ifdef BSP_UART3_TX_USING_DMA
  500. void DMA0_Channel4_IRQHandler (void)
  501. {
  502. dma_tx_isr(&uart_obj[UART3_INDEX].serial);
  503. }
  504. #endif
  505. #ifdef BSP_UART4_RX_USING_DMA
  506. void DMA0_Channel0_IRQHandler (void)
  507. {
  508. dma_rx_isr(&uart_obj[UART4_INDEX].serial);
  509. }
  510. #endif
  511. #ifdef BSP_UART4_TX_USING_DMA
  512. void DMA0_Channel7_IRQHandler (void)
  513. {
  514. dma_tx_isr(&uart_obj[UART4_INDEX].serial);
  515. }
  516. #endif
  517. #ifdef BSP_UART5_RX_USING_DMA
  518. void DMA1_Channel1_IRQHandler (void)
  519. {
  520. dma_rx_isr(&uart_obj[UART5_INDEX].serial);
  521. }
  522. #endif
  523. #ifdef BSP_UART5_TX_USING_DMA
  524. void DMA1_Channel7_IRQHandler (void)
  525. {
  526. dma_tx_isr(&uart_obj[UART5_INDEX].serial);
  527. }
  528. #endif
  529. #ifdef BSP_UART6_RX_USING_DMA
  530. void DMA0_Channel3_IRQHandler (void)
  531. {
  532. dma_rx_isr(&uart_obj[UART6_INDEX].serial);
  533. }
  534. #endif
  535. #ifdef BSP_UART6_TX_USING_DMA
  536. void DMA0_Channel1_IRQHandler (void)
  537. {
  538. dma_tx_isr(&uart_obj[UART6_INDEX].serial);
  539. }
  540. #endif
  541. #ifdef BSP_UART7_RX_USING_DMA
  542. void DMA0_Channel6_IRQHandler (void)
  543. {
  544. dma_rx_isr(&uart_obj[UART7_INDEX].serial);
  545. }
  546. #endif
  547. #ifdef BSP_UART7_TX_USING_DMA
  548. void DMA0_Channel0_IRQHandler (void)
  549. {
  550. dma_tx_isr(&uart_obj[UART7_INDEX].serial);
  551. }
  552. #endif
  553. /**
  554. * @brief UART MSP Initialization
  555. * This function configures the hardware resources used in this example:
  556. * - Peripheral's clock enable
  557. * - Peripheral's GPIO Configuration
  558. * - NVIC configuration for UART interrupt request enable
  559. * @param huart: UART handle pointer
  560. * @retval None
  561. */
  562. void gd32_uart_gpio_init (struct gd32_uart *uart)
  563. {
  564. /* enable USART clock */
  565. rcu_periph_clock_enable(uart->tx_gpio_clk);
  566. rcu_periph_clock_enable(uart->rx_gpio_clk);
  567. rcu_periph_clock_enable(uart->per_clk);
  568. #if defined SOC_SERIES_GD32F4xx
  569. /* connect port to USARTx_Tx */
  570. gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin);
  571. /* connect port to USARTx_Rx */
  572. gpio_af_set(uart->rx_port, uart->rx_af, uart->rx_pin);
  573. /* configure USART Tx as alternate function push-pull */
  574. gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->tx_pin);
  575. gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->tx_pin);
  576. /* configure USART Rx as alternate function push-pull */
  577. gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin);
  578. gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->rx_pin);
  579. #else
  580. /* connect port to USARTx_Tx */
  581. gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin);
  582. /* connect port to USARTx_Rx */
  583. gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin);
  584. #endif
  585. NVIC_SetPriority(uart->irqn, 0);
  586. NVIC_EnableIRQ(uart->irqn);
  587. }
  588. /**
  589. * @brief uart configure
  590. * @param serial, cfg
  591. * @retval None
  592. */
  593. static rt_err_t gd32_uart_configure (struct rt_serial_device *serial, struct serial_configure *cfg)
  594. {
  595. struct gd32_uart *uart;
  596. RT_ASSERT(serial != RT_NULL);
  597. RT_ASSERT(cfg != RT_NULL);
  598. uart = rt_container_of(serial, struct gd32_uart, serial);
  599. #ifdef RT_SERIAL_USING_DMA
  600. uart->dma.last_index = serial->config.dma_ping_bufsz;
  601. #endif
  602. gd32_uart_gpio_init(uart);
  603. usart_baudrate_set(uart->periph, cfg->baud_rate);
  604. switch (cfg->data_bits)
  605. {
  606. case DATA_BITS_9:
  607. usart_word_length_set(uart->periph, USART_WL_9BIT);
  608. break;
  609. default:
  610. usart_word_length_set(uart->periph, USART_WL_8BIT);
  611. break;
  612. }
  613. switch (cfg->stop_bits)
  614. {
  615. case STOP_BITS_2:
  616. usart_stop_bit_set(uart->periph, USART_STB_2BIT);
  617. break;
  618. default:
  619. usart_stop_bit_set(uart->periph, USART_STB_1BIT);
  620. break;
  621. }
  622. switch (cfg->parity)
  623. {
  624. case PARITY_ODD:
  625. usart_parity_config(uart->periph, USART_PM_ODD);
  626. break;
  627. case PARITY_EVEN:
  628. usart_parity_config(uart->periph, USART_PM_EVEN);
  629. break;
  630. default:
  631. usart_parity_config(uart->periph, USART_PM_NONE);
  632. break;
  633. }
  634. usart_receive_config(uart->periph, USART_RECEIVE_ENABLE);
  635. usart_transmit_config(uart->periph, USART_TRANSMIT_ENABLE);
  636. usart_enable(uart->periph);
  637. return RT_EOK;
  638. }
  639. #ifdef RT_SERIAL_USING_DMA
  640. static void _uart_dma_receive (struct gd32_uart *uart, rt_uint8_t *buffer, rt_uint32_t size)
  641. {
  642. dma_single_data_parameter_struct dma_init_struct = { 0 };
  643. /* clear all the interrupt flags */
  644. dma_flag_clear(uart->dma.rx.periph, uart->dma.rx.channel, DMA_FLAG_FEE);
  645. dma_flag_clear(uart->dma.rx.periph, uart->dma.rx.channel, DMA_FLAG_SDE);
  646. dma_flag_clear(uart->dma.rx.periph, uart->dma.rx.channel, DMA_FLAG_TAE);
  647. dma_flag_clear(uart->dma.rx.periph, uart->dma.rx.channel, DMA_FLAG_HTF);
  648. dma_flag_clear(uart->dma.rx.periph, uart->dma.rx.channel, DMA_FLAG_FTF);
  649. dma_channel_disable(uart->dma.rx.periph, uart->dma.rx.channel);
  650. dma_deinit(uart->dma.rx.periph, uart->dma.rx.channel);
  651. /* configure receive DMA */
  652. rcu_periph_clock_enable(uart->dma.rx.rcu);
  653. dma_deinit(uart->dma.rx.periph, uart->dma.rx.channel);
  654. dma_init_struct.number = size;
  655. dma_init_struct.memory0_addr = (uint32_t)buffer;
  656. dma_init_struct.periph_addr = (uint32_t)&USART_DATA(uart->periph);
  657. dma_init_struct.periph_memory_width = DMA_PERIPH_WIDTH_8BIT;
  658. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  659. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  660. dma_init_struct.circular_mode = DMA_CIRCULAR_MODE_ENABLE;
  661. dma_init_struct.direction = DMA_PERIPH_TO_MEMORY;
  662. dma_init_struct.priority = DMA_PRIORITY_HIGH;
  663. dma_single_data_mode_init(uart->dma.rx.periph, uart->dma.rx.channel, &dma_init_struct);
  664. dma_channel_subperipheral_select(uart->dma.rx.periph, uart->dma.rx.channel, uart->dma.rx.subperiph);
  665. /* enable transmit complete interrupt */
  666. nvic_irq_enable(uart->dma.rx.irq, 2, 0);
  667. dma_interrupt_enable(uart->dma.rx.periph, uart->dma.rx.channel, DMA_CHXCTL_HTFIE);
  668. dma_interrupt_enable(uart->dma.rx.periph, uart->dma.rx.channel, DMA_CHXCTL_FTFIE);
  669. /* enable dma channel */
  670. dma_channel_enable(uart->dma.rx.periph, uart->dma.rx.channel);
  671. /* enable usart idle interrupt */
  672. usart_interrupt_enable(uart->periph, USART_INT_IDLE);
  673. /* enable dma receive */
  674. usart_dma_receive_config(uart->periph, USART_RECEIVE_DMA_ENABLE);
  675. }
  676. static void _uart_dma_transmit (struct gd32_uart *uart, rt_uint8_t *buffer, rt_uint32_t size)
  677. {
  678. /* Set the data length and data pointer */
  679. DMA_CHM0ADDR(uart->dma.tx.periph, uart->dma.tx.channel) = (uint32_t)buffer;
  680. DMA_CHCNT(uart->dma.tx.periph, uart->dma.tx.channel) = size;
  681. /* enable dma transmit */
  682. usart_dma_transmit_config(uart->periph, USART_TRANSMIT_DMA_ENABLE);
  683. /* enable dma channel */
  684. dma_channel_enable(uart->dma.tx.periph, uart->dma.tx.channel);
  685. }
  686. static void gd32_dma_config (struct rt_serial_device *serial, rt_ubase_t flag)
  687. {
  688. struct gd32_uart *uart;
  689. dma_single_data_parameter_struct dma_init_struct = { 0 };
  690. RT_ASSERT(serial != RT_NULL);
  691. uart = rt_container_of(serial, struct gd32_uart, serial);
  692. RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
  693. /* enable rx dma */
  694. if (flag == RT_DEVICE_FLAG_DMA_TX)
  695. {
  696. /* clear all the interrupt flags */
  697. dma_flag_clear(uart->dma.tx.periph, uart->dma.tx.channel, DMA_FLAG_FEE);
  698. dma_flag_clear(uart->dma.tx.periph, uart->dma.tx.channel, DMA_FLAG_SDE);
  699. dma_flag_clear(uart->dma.tx.periph, uart->dma.tx.channel, DMA_FLAG_TAE);
  700. dma_flag_clear(uart->dma.tx.periph, uart->dma.tx.channel, DMA_FLAG_HTF);
  701. dma_flag_clear(uart->dma.tx.periph, uart->dma.tx.channel, DMA_FLAG_FTF);
  702. dma_channel_disable(uart->dma.tx.periph, uart->dma.tx.channel);
  703. dma_deinit(uart->dma.tx.periph, uart->dma.tx.channel);
  704. /* configure receive DMA */
  705. rcu_periph_clock_enable(uart->dma.tx.rcu);
  706. dma_deinit(uart->dma.tx.periph, uart->dma.tx.channel);
  707. dma_init_struct.periph_addr = (uint32_t)&USART_DATA(uart->periph);
  708. dma_init_struct.periph_memory_width = DMA_PERIPH_WIDTH_8BIT;
  709. dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_DISABLE;
  710. dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
  711. dma_init_struct.circular_mode = DMA_CIRCULAR_MODE_DISABLE;
  712. dma_init_struct.direction = DMA_MEMORY_TO_PERIPH;
  713. dma_init_struct.priority = DMA_PRIORITY_HIGH;
  714. dma_single_data_mode_init(uart->dma.tx.periph, uart->dma.tx.channel, &dma_init_struct);
  715. dma_channel_subperipheral_select(uart->dma.tx.periph, uart->dma.tx.channel, uart->dma.tx.subperiph);
  716. /* enable tx dma interrupt */
  717. nvic_irq_enable(uart->dma.tx.irq, 2, 0);
  718. /* enable transmit complete interrupt */
  719. dma_interrupt_enable(uart->dma.tx.periph, uart->dma.tx.channel, DMA_CHXCTL_FTFIE);
  720. }
  721. /* enable rx dma */
  722. if (flag == RT_DEVICE_FLAG_DMA_RX)
  723. {
  724. rt_uint8_t *ptr = NULL;
  725. rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, &ptr);
  726. /* start dma transfer */
  727. _uart_dma_receive(uart, ptr, serial->config.dma_ping_bufsz);
  728. }
  729. }
  730. #endif
  731. /**
  732. * @brief uart control
  733. * @param serial, arg
  734. * @retval None
  735. */
  736. static rt_err_t gd32_uart_control (struct rt_serial_device *serial, int cmd, void *arg)
  737. {
  738. struct gd32_uart *uart;
  739. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  740. RT_ASSERT(serial != RT_NULL);
  741. uart = rt_container_of(serial, struct gd32_uart, serial);
  742. if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
  743. {
  744. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
  745. ctrl_arg = RT_DEVICE_FLAG_DMA_RX;
  746. else
  747. ctrl_arg = RT_DEVICE_FLAG_INT_RX;
  748. }
  749. else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
  750. {
  751. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  752. ctrl_arg = RT_DEVICE_FLAG_DMA_TX;
  753. else
  754. ctrl_arg = RT_DEVICE_FLAG_INT_TX;
  755. }
  756. switch (cmd)
  757. {
  758. case RT_DEVICE_CTRL_CLR_INT:
  759. /* disable rx irq */
  760. NVIC_DisableIRQ(uart->irqn);
  761. /* disable interrupt */
  762. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
  763. {
  764. usart_interrupt_disable(uart->periph, USART_INT_RBNE);
  765. }
  766. else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
  767. {
  768. usart_interrupt_disable(uart->periph, USART_INT_TBE);
  769. }
  770. #ifdef RT_SERIAL_USING_DMA
  771. /* disable DMA */
  772. else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  773. {
  774. usart_interrupt_disable(uart->periph, USART_INT_RBNE);
  775. NVIC_DisableIRQ(uart->dma.rx.irq);
  776. dma_deinit(uart->dma.rx.periph, uart->dma.rx.channel);
  777. }
  778. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  779. {
  780. usart_interrupt_disable(uart->periph, USART_INT_TBE);
  781. NVIC_DisableIRQ(uart->dma.tx.irq);
  782. dma_deinit(uart->dma.tx.periph, uart->dma.tx.channel);
  783. }
  784. #endif
  785. break;
  786. case RT_DEVICE_CTRL_SET_INT:
  787. /* enable rx irq */
  788. NVIC_EnableIRQ(uart->irqn);
  789. /* enable interrupt */
  790. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
  791. {
  792. usart_interrupt_enable(uart->periph, USART_INT_RBNE);
  793. }
  794. else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
  795. {
  796. usart_interrupt_enable(uart->periph, USART_INT_TBE);
  797. }
  798. break;
  799. case RT_DEVICE_CTRL_CONFIG:
  800. if(ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX))
  801. {
  802. #ifdef RT_SERIAL_USING_DMA
  803. gd32_dma_config(serial, ctrl_arg);
  804. #endif
  805. }
  806. else
  807. {
  808. gd32_uart_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg);
  809. }
  810. break;
  811. case RT_DEVICE_CHECK_OPTMODE:
  812. if(ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
  813. return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
  814. else
  815. return RT_SERIAL_TX_BLOCKING_BUFFER;
  816. case RT_DEVICE_CTRL_CLOSE:
  817. usart_deinit(uart->periph);
  818. break;
  819. }
  820. return RT_EOK;
  821. }
  822. /**
  823. * @brief uart put char
  824. * @param serial, ch
  825. * @retval None
  826. */
  827. static int gd32_uart_putc (struct rt_serial_device *serial, char ch)
  828. {
  829. struct gd32_uart *uart;
  830. RT_ASSERT(serial != RT_NULL);
  831. uart = rt_container_of(serial, struct gd32_uart, serial);
  832. usart_data_transmit(uart->periph, ch);
  833. while((usart_flag_get(uart->periph, USART_FLAG_TBE) == RESET));
  834. return RT_EOK;
  835. }
  836. /**
  837. * @brief uart get char
  838. * @param serial
  839. * @retval None
  840. */
  841. static int gd32_uart_getc (struct rt_serial_device *serial)
  842. {
  843. int ch;
  844. struct gd32_uart *uart;
  845. RT_ASSERT(serial != RT_NULL);
  846. uart = rt_container_of(serial, struct gd32_uart, serial);
  847. ch = -1;
  848. if (usart_flag_get(uart->periph, USART_FLAG_RBNE) != RESET)
  849. ch = usart_data_receive(uart->periph);
  850. return ch;
  851. }
  852. static rt_ssize_t gd32_transmit (struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, rt_uint32_t tx_flag)
  853. {
  854. struct gd32_uart *uart;
  855. RT_ASSERT(buf != RT_NULL);
  856. RT_ASSERT(serial != RT_NULL);
  857. uart = rt_container_of(serial, struct gd32_uart, serial);
  858. if (size == 0)
  859. {
  860. return 0;
  861. }
  862. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  863. {
  864. #ifdef RT_SERIAL_USING_DMA
  865. _uart_dma_transmit(uart, buf, size);
  866. return size;
  867. #endif
  868. }
  869. gd32_uart_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)tx_flag);
  870. return size;
  871. }
  872. static const struct rt_uart_ops gd32_uart_ops =
  873. {
  874. .configure = gd32_uart_configure,
  875. .control = gd32_uart_control,
  876. .putc = gd32_uart_putc,
  877. .getc = gd32_uart_getc,
  878. .transmit = gd32_transmit,
  879. };
  880. static void gd32_uart_get_config (void)
  881. {
  882. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  883. #ifdef BSP_USING_UART0
  884. uart_obj[UART0_INDEX].uart_dma_flag = 0;
  885. uart_obj[UART0_INDEX].serial.config = config;
  886. uart_obj[UART0_INDEX].serial.config.rx_bufsz = BSP_UART0_RX_BUFSIZE;
  887. uart_obj[UART0_INDEX].serial.config.tx_bufsz = BSP_UART0_TX_BUFSIZE;
  888. #ifdef BSP_UART0_RX_USING_DMA
  889. uart_obj[UART0_INDEX].serial.config.dma_ping_bufsz = BSP_UART0_DMA_PING_BUFSIZE;
  890. uart_obj[UART0_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  891. #endif
  892. #ifdef BSP_UART0_TX_USING_DMA
  893. uart_obj[UART0_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  894. #endif
  895. #endif
  896. #ifdef BSP_USING_UART1
  897. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  898. uart_obj[UART1_INDEX].serial.config = config;
  899. uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
  900. uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
  901. #ifdef BSP_UART1_RX_USING_DMA
  902. uart_obj[UART1_INDEX].serial.config.dma_ping_bufsz = BSP_UART1_DMA_PING_BUFSIZE;
  903. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  904. #endif
  905. #ifdef BSP_UART1_TX_USING_DMA
  906. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  907. #endif
  908. #endif
  909. #ifdef BSP_USING_UART2
  910. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  911. uart_obj[UART2_INDEX].serial.config = config;
  912. uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE;
  913. uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE;
  914. #ifdef BSP_UART2_RX_USING_DMA
  915. uart_obj[UART2_INDEX].serial.config.dma_ping_bufsz = BSP_UART2_DMA_PING_BUFSIZE;
  916. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  917. #endif
  918. #ifdef BSP_UART2_TX_USING_DMA
  919. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  920. #endif
  921. #endif
  922. #ifdef BSP_USING_UART3
  923. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  924. uart_obj[UART3_INDEX].serial.config = config;
  925. uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
  926. uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
  927. #ifdef BSP_UART3_RX_USING_DMA
  928. uart_obj[UART3_INDEX].serial.config.dma_ping_bufsz = BSP_UART3_DMA_PING_BUFSIZE;
  929. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  930. #endif
  931. #ifdef BSP_UART3_TX_USING_DMA
  932. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  933. #endif
  934. #endif
  935. #ifdef BSP_USING_UART4
  936. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  937. uart_obj[UART4_INDEX].serial.config = config;
  938. uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
  939. uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
  940. #ifdef BSP_UART4_RX_USING_DMA
  941. uart_obj[UART4_INDEX].serial.config.dma_ping_bufsz = BSP_UART4_DMA_PING_BUFSIZE;
  942. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  943. #endif
  944. #ifdef BSP_UART4_TX_USING_DMA
  945. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  946. #endif
  947. #endif
  948. #ifdef BSP_USING_UART5
  949. uart_obj[UART5_INDEX].uart_dma_flag = 0;
  950. uart_obj[UART5_INDEX].serial.config = config;
  951. uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE;
  952. uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE;
  953. #ifdef BSP_UART5_RX_USING_DMA
  954. uart_obj[UART5_INDEX].serial.config.dma_ping_bufsz = BSP_UART5_DMA_PING_BUFSIZE;
  955. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  956. #endif
  957. #ifdef BSP_UART5_TX_USING_DMA
  958. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  959. #endif
  960. #endif
  961. #ifdef BSP_USING_UART6
  962. uart_obj[UART6_INDEX].uart_dma_flag = 0;
  963. uart_obj[UART6_INDEX].serial.config = config;
  964. uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
  965. uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
  966. #ifdef BSP_UART6_RX_USING_DMA
  967. uart_obj[UART6_INDEX].serial.config.dma_ping_bufsz = BSP_UART6_DMA_PING_BUFSIZE;
  968. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  969. #endif
  970. #ifdef BSP_UART6_TX_USING_DMA
  971. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  972. #endif
  973. #endif
  974. #ifdef BSP_USING_UART7
  975. uart_obj[UART7_INDEX].uart_dma_flag = 0;
  976. uart_obj[UART7_INDEX].serial.config = config;
  977. uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
  978. uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
  979. #ifdef BSP_UART7_RX_USING_DMA
  980. uart_obj[UART7_INDEX].serial.config.dma_ping_bufsz = BSP_UART7_DMA_PING_BUFSIZE;
  981. uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  982. #endif
  983. #ifdef BSP_UART7_TX_USING_DMA
  984. uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  985. #endif
  986. #endif
  987. }
  988. /**
  989. * @brief uart init
  990. * @param None
  991. * @retval None
  992. */
  993. int rt_hw_usart_init (void)
  994. {
  995. int i;
  996. int result;
  997. gd32_uart_get_config();
  998. for (i = 0; i < sizeof(uart_obj) / sizeof(uart_obj[0]); i++)
  999. {
  1000. uart_obj[i].serial.ops = &gd32_uart_ops;
  1001. /* register UART1 device */
  1002. result = rt_hw_serial_register(&uart_obj[i].serial,
  1003. uart_obj[i].device_name,
  1004. RT_DEVICE_FLAG_RDWR |
  1005. RT_DEVICE_FLAG_INT_RX |
  1006. uart_obj[i].uart_dma_flag,
  1007. (void *)&uart_obj[i]);
  1008. RT_ASSERT(result == RT_EOK);
  1009. }
  1010. return result;
  1011. }
  1012. #endif