drv_i2s.c 20 KB

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  1. /*
  2. * Copyright (c) 2022-2023 HPMicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. */
  7. #include <rtthread.h>
  8. #include <rtdevice.h>
  9. #define DBG_TAG "i2s"
  10. #define DBG_LVL DBG_INFO
  11. #include <rtdbg.h>
  12. #ifdef BSP_USING_I2S
  13. #include "hpm_i2s_drv.h"
  14. #include "board.h"
  15. #ifdef HPMSOC_HAS_HPMSDK_DMAV2
  16. #include "hpm_dmav2_drv.h"
  17. #else
  18. #include "hpm_dma_drv.h"
  19. #endif
  20. #include "hpm_dmamux_drv.h"
  21. #include "hpm_l1c_drv.h"
  22. #include "hpm_clock_drv.h"
  23. #include "hpm_dma_mgr.h"
  24. #include "drv_i2s.h"
  25. #include "drivers/dev_audio.h"
  26. static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* writeBuf, void* readBuf, rt_size_t size);
  27. /**
  28. * I2S state
  29. */
  30. typedef enum {
  31. hpm_i2s_state_stop,
  32. hpm_i2s_state_read,
  33. hpm_i2s_state_write,
  34. } hpm_i2s_state_t;
  35. struct hpm_i2s
  36. {
  37. struct rt_audio_device audio;
  38. struct rt_audio_configure audio_config;
  39. dma_resource_t rx_dma_resource;
  40. dma_resource_t tx_dma_resource;
  41. char *dev_name;
  42. I2S_Type *base;
  43. clock_name_t clk_name;
  44. i2s_transfer_config_t transfer;
  45. uint8_t rx_dma_req;
  46. uint8_t tx_dma_req;
  47. rt_uint8_t* tx_buff;
  48. rt_uint8_t* rx_buff;
  49. hpm_i2s_state_t i2s_state;
  50. };
  51. #if defined(BSP_USING_I2S0)
  52. ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s0_tx_buff[I2S_FIFO_SIZE];
  53. ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s0_rx_buff[I2S_FIFO_SIZE];
  54. #endif
  55. #if defined(BSP_USING_I2S1)
  56. ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s1_tx_buff[I2S_FIFO_SIZE];
  57. ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s1_rx_buff[I2S_FIFO_SIZE];
  58. #endif
  59. #if defined(BSP_USING_I2S2)
  60. ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s2_tx_buff[I2S_FIFO_SIZE];
  61. ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s2_rx_buff[I2S_FIFO_SIZE];
  62. #endif
  63. #if defined(BSP_USING_I2S3)
  64. ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s3_tx_buff[I2S_FIFO_SIZE];
  65. ATTR_ALIGN(HPM_L1C_CACHELINE_SIZE) uint8_t i2s3_rx_buff[I2S_FIFO_SIZE];
  66. #endif
  67. static struct hpm_i2s hpm_i2s_set[] =
  68. {
  69. #if defined(BSP_USING_I2S0) && defined(HPM_I2S0)
  70. {
  71. .dev_name = "i2s0",
  72. .base = HPM_I2S0,
  73. .clk_name = clock_i2s0,
  74. .rx_dma_req = HPM_DMA_SRC_I2S0_RX,
  75. .tx_dma_req = HPM_DMA_SRC_I2S0_TX,
  76. .tx_buff = i2s0_tx_buff,
  77. .rx_buff = i2s0_rx_buff,
  78. },
  79. #endif
  80. #if defined(BSP_USING_I2S1) && defined(HPM_I2S1)
  81. {
  82. .dev_name = "i2s1",
  83. .base = HPM_I2S1;
  84. .clk_name = clock_i2s1,
  85. .rx_dma_req = HPM_DMA_SRC_I2S1_RX,
  86. .tx_dma_req = HPM_DMA_SRC_I2S1_TX,
  87. .tx_buff = i2s1_tx_buff,
  88. .rx_buff = i2s1_rx_buff,
  89. },
  90. #endif
  91. #if defined(BSP_USING_I2S2) && defined(HPM_I2S2)
  92. {
  93. .dev_name = "i2s2",
  94. .base = HPM_I2S2,
  95. .clk_name = clock_i2s2,
  96. .rx_dma_req = HPM_DMA_SRC_I2S2_RX,
  97. .tx_dma_req = HPM_DMA_SRC_I2S2_TX,
  98. .tx_buff = i2s2_tx_buff,
  99. .rx_buff = i2s2_rx_buff,
  100. },
  101. #endif
  102. #if defined(BSP_USING_I2S3) && defined(HPM_I2S3)
  103. {
  104. .dev_name = "i2s3",
  105. .base = HPM_I2S3,
  106. .clk_name = clock_i2s3,
  107. .rx_dma_req = HPM_DMA_SRC_I2S3_RX,
  108. .tx_dma_req = HPM_DMA_SRC_I2S3_TX,
  109. .tx_buff = i2s3_tx_buff,
  110. .rx_buff = i2s3_rx_buff,
  111. },
  112. #endif
  113. };
  114. /* I2S TX DMA callback function: trigger next transfer */
  115. void i2s_tx_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data)
  116. {
  117. struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data;
  118. rt_audio_tx_complete(&hpm_audio->audio);
  119. }
  120. /* I2S RX DMA callback function: write data into record->pipe and trigger next transfer */
  121. void i2s_rx_dma_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data)
  122. {
  123. struct hpm_i2s* hpm_audio = (struct hpm_i2s*) user_data;
  124. rt_audio_rx_done(&hpm_audio->audio, hpm_audio->rx_buff, I2S_FIFO_SIZE);
  125. hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE);
  126. }
  127. static rt_err_t hpm_i2s_init(struct rt_audio_device* audio)
  128. {
  129. RT_ASSERT(audio != RT_NULL);
  130. rt_uint32_t mclk_hz;
  131. i2s_config_t i2s_config;
  132. i2s_transfer_config_t transfer;
  133. struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data;
  134. init_i2s_pins(hpm_audio->base);
  135. board_init_i2s_clock(hpm_audio->base);
  136. /* enable dma request */
  137. i2s_enable_rx_dma_request(hpm_audio->base);
  138. i2s_enable_tx_dma_request(hpm_audio->base);
  139. i2s_get_default_config(hpm_audio->base, &i2s_config);
  140. i2s_config.enable_mclk_out = true;
  141. i2s_init(hpm_audio->base, &i2s_config);
  142. mclk_hz = clock_get_frequency(hpm_audio->clk_name);
  143. i2s_get_default_transfer_config(&transfer);
  144. /* init I2S parameter */
  145. transfer.sample_rate = 48000U;
  146. transfer.protocol = I2S_PROTOCOL_LEFT_JUSTIFIED;
  147. transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); /* one channel */
  148. transfer.audio_depth = i2s_audio_depth_16_bits;
  149. transfer.master_mode = true;
  150. hpm_audio->transfer = transfer;
  151. /* record i2s parameter to audio_config */
  152. hpm_audio->audio_config.samplerate = 48000U;
  153. hpm_audio->audio_config.samplebits = 16;
  154. hpm_audio->audio_config.channels = 1;
  155. if (status_success != i2s_config_transfer(hpm_audio->base, mclk_hz, &transfer))
  156. {
  157. LOG_E("dao_i2s configure transfer failed\n");
  158. return -RT_ERROR;
  159. }
  160. hpm_audio->i2s_state = hpm_i2s_state_stop;
  161. return RT_EOK;
  162. }
  163. static rt_err_t hpm_i2s_getcaps(struct rt_audio_device* audio, struct rt_audio_caps* caps)
  164. {
  165. rt_err_t result = RT_EOK;
  166. RT_ASSERT(audio != RT_NULL);
  167. struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data;
  168. switch(caps->main_type)
  169. {
  170. case AUDIO_TYPE_INPUT:
  171. {
  172. switch(caps->sub_type)
  173. {
  174. case AUDIO_DSP_PARAM:
  175. {
  176. caps->udata.config.channels = hpm_audio->audio_config.channels;
  177. caps->udata.config.samplebits = hpm_audio->audio_config.samplebits;
  178. caps->udata.config.samplerate = hpm_audio->audio_config.samplerate;
  179. break;
  180. }
  181. case AUDIO_DSP_SAMPLERATE:
  182. {
  183. caps->udata.config.samplerate = hpm_audio->audio_config.samplerate;
  184. break;
  185. }
  186. case AUDIO_DSP_CHANNELS:
  187. {
  188. caps->udata.config.channels = hpm_audio->audio_config.channels;
  189. break;
  190. }
  191. case AUDIO_DSP_SAMPLEBITS:
  192. {
  193. caps->udata.config.samplebits = hpm_audio->audio_config.samplebits;
  194. break;
  195. }
  196. case AUDIO_PARM_I2S_DATA_LINE:
  197. {
  198. caps->udata.value = hpm_audio->transfer.data_line;
  199. break;
  200. }
  201. default:
  202. {
  203. result = -RT_ERROR;
  204. break;
  205. }
  206. }
  207. break;
  208. }
  209. case AUDIO_TYPE_OUTPUT:
  210. {
  211. switch(caps->sub_type)
  212. {
  213. case AUDIO_DSP_PARAM:
  214. {
  215. caps->udata.config.samplerate = hpm_audio->audio_config.samplerate;
  216. caps->udata.config.channels = hpm_audio->audio_config.channels;
  217. caps->udata.config.samplebits = hpm_audio->audio_config.samplebits;
  218. break;
  219. }
  220. case AUDIO_DSP_SAMPLERATE:
  221. {
  222. caps->udata.config.samplerate = hpm_audio->audio_config.samplerate;
  223. break;
  224. }
  225. case AUDIO_DSP_CHANNELS:
  226. {
  227. caps->udata.config.channels = hpm_audio->audio_config.channels;
  228. break;
  229. }
  230. case AUDIO_DSP_SAMPLEBITS:
  231. {
  232. caps->udata.config.samplebits = hpm_audio->audio_config.samplebits;
  233. break;
  234. }
  235. case AUDIO_PARM_I2S_DATA_LINE:
  236. {
  237. caps->udata.value = hpm_audio->transfer.data_line;
  238. break;
  239. }
  240. default:
  241. {
  242. result = -RT_ERROR;
  243. break;
  244. }
  245. }
  246. break;
  247. }
  248. default:
  249. result = -RT_ERROR;
  250. break;
  251. }
  252. return result;
  253. }
  254. static bool i2s_is_enabled(I2S_Type *ptr)
  255. {
  256. return ((ptr->CTRL & I2S_CTRL_I2S_EN_MASK) != 0);
  257. }
  258. static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio_caps* caps)
  259. {
  260. rt_err_t result = RT_EOK;
  261. RT_ASSERT(audio != RT_NULL);
  262. struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data;
  263. switch(caps->main_type)
  264. {
  265. case AUDIO_TYPE_OUTPUT:
  266. {
  267. switch(caps->sub_type)
  268. {
  269. case AUDIO_DSP_PARAM:
  270. {
  271. hpm_audio->audio_config.samplerate = caps->udata.config.samplerate;
  272. hpm_audio->audio_config.samplebits = caps->udata.config.samplebits;
  273. hpm_audio->audio_config.channels = caps->udata.config.channels;
  274. break;
  275. }
  276. case AUDIO_DSP_SAMPLERATE:
  277. {
  278. hpm_audio->audio_config.samplerate = caps->udata.config.samplerate;
  279. break;
  280. }
  281. case AUDIO_DSP_CHANNELS:
  282. {
  283. hpm_audio->audio_config.channels = caps->udata.config.channels;
  284. break;
  285. }
  286. case AUDIO_DSP_SAMPLEBITS:
  287. {
  288. hpm_audio->audio_config.samplebits = caps->udata.config.samplebits;
  289. break;
  290. }
  291. case AUDIO_PARM_I2S_DATA_LINE:
  292. {
  293. hpm_audio->transfer.data_line = caps->udata.value;
  294. break;
  295. }
  296. default:
  297. result = -RT_ERROR;
  298. break;
  299. }
  300. break;
  301. }
  302. case AUDIO_TYPE_INPUT:
  303. {
  304. switch(caps->sub_type)
  305. {
  306. case AUDIO_DSP_PARAM:
  307. {
  308. hpm_audio->audio_config.samplerate = caps->udata.config.samplerate;
  309. hpm_audio->audio_config.channels = caps->udata.config.channels;
  310. hpm_audio->audio_config.samplebits = caps->udata.config.samplebits;
  311. break;
  312. }
  313. case AUDIO_DSP_SAMPLERATE:
  314. {
  315. hpm_audio->audio_config.samplerate = caps->udata.config.samplerate;
  316. break;
  317. }
  318. case AUDIO_DSP_CHANNELS:
  319. {
  320. hpm_audio->audio_config.channels = caps->udata.config.channels;
  321. break;
  322. }
  323. case AUDIO_DSP_SAMPLEBITS:
  324. {
  325. hpm_audio->audio_config.samplebits = caps->udata.config.samplebits;
  326. break;
  327. }
  328. case AUDIO_PARM_I2S_DATA_LINE:
  329. {
  330. hpm_audio->transfer.data_line = caps->udata.value;
  331. break;
  332. }
  333. default:
  334. result = -RT_ERROR;
  335. break;
  336. }
  337. break;
  338. }
  339. default:
  340. break;
  341. }
  342. /* configure I2S transfer */
  343. if (hpm_audio->audio_config.channels == i2s_mono_left) {
  344. hpm_audio->transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0);
  345. } else if (hpm_audio->audio_config.channels == i2s_mono_right) {
  346. hpm_audio->transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(1);
  347. } else if(hpm_audio->audio_config.channels == 2) {
  348. hpm_audio->transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0) | I2S_CHANNEL_SLOT_MASK(1);
  349. } else {
  350. LOG_E("I2S not support channels number %d.\n", hpm_audio->audio_config.channels);
  351. return -RT_ERROR;
  352. }
  353. hpm_audio->transfer.sample_rate = hpm_audio->audio_config.samplerate;
  354. /* i2s dma only support sample bit: 16 and 32 bits */
  355. assert(hpm_audio->audio_config.samplebits == 16 || hpm_audio->audio_config.samplebits == 32);
  356. hpm_audio->transfer.audio_depth = hpm_audio->audio_config.samplebits;
  357. /* Stop I2S transfer if the I2S needs to be re-configured */
  358. bool is_enabled = i2s_is_enabled(hpm_audio->base);
  359. if (is_enabled)
  360. {
  361. if (hpm_audio->i2s_state == hpm_i2s_state_read)
  362. {
  363. dma_abort_channel(hpm_audio->rx_dma_resource.base, hpm_audio->rx_dma_resource.channel);
  364. }
  365. if (hpm_audio->i2s_state == hpm_i2s_state_write)
  366. {
  367. dma_abort_channel(hpm_audio->tx_dma_resource.base, hpm_audio->tx_dma_resource.channel);
  368. }
  369. }
  370. if (status_success != i2s_config_transfer(hpm_audio->base, clock_get_frequency(hpm_audio->clk_name), &hpm_audio->transfer))
  371. {
  372. LOG_E("%s configure transfer failed.\n", hpm_audio->dev_name);
  373. return -RT_ERROR;
  374. }
  375. /* Restore I2S to previous state */
  376. if (is_enabled)
  377. {
  378. i2s_enable(hpm_audio->base);
  379. }
  380. return result;
  381. }
  382. static rt_err_t hpm_i2s_start(struct rt_audio_device* audio, int stream)
  383. {
  384. RT_ASSERT(audio != RT_NULL);
  385. struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data;
  386. /* request DMA resource for audio data transfer */
  387. if (stream == AUDIO_STREAM_REPLAY) {
  388. i2s_disable(hpm_audio->base);
  389. i2s_disable_tx_dma_request(hpm_audio->base);
  390. dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource;
  391. if (dma_mgr_request_resource(dma_resource) == status_success) {
  392. uint8_t dmamux_ch;
  393. dma_mgr_install_chn_tc_callback(dma_resource, i2s_tx_dma_tc_callback, hpm_audio);
  394. dma_mgr_enable_dma_irq_with_priority(dma_resource, 1);
  395. dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource->base, dma_resource->channel);
  396. dmamux_config(HPM_DMAMUX, dmamux_ch, hpm_audio->tx_dma_req, true);
  397. } else {
  398. LOG_E("no dma resource available for I2S TX transfer.\n");
  399. return -RT_ERROR;
  400. }
  401. i2s_reset_tx(hpm_audio->base); /* disable and reset tx */
  402. /* fill 2 dummy data, it is suitable for 1/2 channel of audio */
  403. if (i2s_fill_tx_dummy_data(hpm_audio->base, hpm_audio->transfer.data_line , 2) != status_success) {
  404. return -RT_ERROR;
  405. }
  406. rt_audio_tx_complete(audio);
  407. i2s_enable(hpm_audio->base);
  408. i2s_enable_tx_dma_request(hpm_audio->base);
  409. } else if (stream == AUDIO_STREAM_RECORD) {
  410. i2s_disable(hpm_audio->base);
  411. i2s_disable_rx_dma_request(hpm_audio->base);
  412. dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource;
  413. if (dma_mgr_request_resource(dma_resource) == status_success) {
  414. uint8_t dmamux_ch;
  415. dma_mgr_install_chn_tc_callback(dma_resource, i2s_rx_dma_tc_callback, hpm_audio);
  416. dma_mgr_enable_dma_irq_with_priority(dma_resource, 1);
  417. dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(dma_resource->base, dma_resource->channel);
  418. dmamux_config(HPM_DMAMUX, dmamux_ch, hpm_audio->rx_dma_req, true);
  419. } else {
  420. LOG_E("no dma resource available for I2S RX transfer.\n");
  421. return -RT_ERROR;
  422. }
  423. i2s_reset_rx(hpm_audio->base); /* disable and reset rx */
  424. if (I2S_FIFO_SIZE != hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE)) {
  425. return -RT_ERROR;
  426. }
  427. i2s_enable(hpm_audio->base);
  428. i2s_enable_rx_dma_request(hpm_audio->base);
  429. } else {
  430. return -RT_ERROR;
  431. }
  432. return RT_EOK;
  433. }
  434. static rt_err_t hpm_i2s_stop(struct rt_audio_device* audio, int stream)
  435. {
  436. RT_ASSERT(audio != RT_NULL);
  437. struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data;
  438. i2s_disable(hpm_audio->base);
  439. if (stream == AUDIO_STREAM_REPLAY) {
  440. dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource;
  441. dma_abort_channel(dma_resource->base, dma_resource->channel);
  442. dma_mgr_release_resource(dma_resource);
  443. } else if (stream == AUDIO_STREAM_RECORD)
  444. {
  445. dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource;
  446. dma_abort_channel(dma_resource->base, dma_resource->channel);
  447. dma_mgr_release_resource(dma_resource);
  448. } else {
  449. return -RT_ERROR;
  450. }
  451. hpm_audio->i2s_state = hpm_i2s_state_stop;
  452. return RT_EOK;
  453. }
  454. static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* writeBuf, void* readBuf, rt_size_t size)
  455. {
  456. RT_ASSERT(audio != RT_NULL);
  457. struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data;
  458. /* i2s dma only support sample bit: 16 and 32 bits */
  459. uint8_t data_width;
  460. uint8_t data_shift_byte;
  461. if (hpm_audio->transfer.audio_depth == i2s_audio_depth_16_bits) {
  462. data_width = DMA_TRANSFER_WIDTH_HALF_WORD;
  463. data_shift_byte = 2U ; /* put 16bit data on high bit of register */
  464. } else {
  465. data_width = DMA_TRANSFER_WIDTH_WORD;
  466. data_shift_byte = 0U;
  467. }
  468. if(writeBuf != RT_NULL)
  469. {
  470. dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource;
  471. dma_channel_config_t ch_config = {0};
  472. dma_default_channel_config(dma_resource->base, &ch_config);
  473. ch_config.src_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)writeBuf);
  474. ch_config.dst_addr = (uint32_t)&hpm_audio->base->TXD[hpm_audio->transfer.data_line] + data_shift_byte;
  475. ch_config.src_width = data_width;
  476. ch_config.dst_width = data_width;
  477. ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT;
  478. ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED;
  479. ch_config.size_in_byte = size;
  480. ch_config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE;
  481. ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T;
  482. if (l1c_dc_is_enabled()) {
  483. /* cache writeback for sent buff */
  484. l1c_dc_writeback((uint32_t)writeBuf, size);
  485. }
  486. hpm_audio->i2s_state = hpm_i2s_state_write;
  487. if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config, true)) {
  488. LOG_E("dma setup channel failed\n");
  489. return -RT_ERROR;
  490. }
  491. } else if (readBuf != RT_NULL){
  492. dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource;
  493. dma_channel_config_t ch_config = {0};
  494. dma_default_channel_config(dma_resource->base, &ch_config);
  495. ch_config.src_addr = (uint32_t)&hpm_audio->base->RXD[hpm_audio->transfer.data_line] + data_shift_byte;
  496. ch_config.dst_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)readBuf);
  497. ch_config.src_width = data_width;
  498. ch_config.dst_width = data_width;
  499. ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED;
  500. ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT;
  501. ch_config.size_in_byte = size;
  502. ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE;
  503. ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T;
  504. hpm_audio->i2s_state = hpm_i2s_state_read;
  505. if (status_success != dma_setup_channel(dma_resource->base, dma_resource->channel, &ch_config, true)) {
  506. LOG_E("dma setup channel failed\n");
  507. return -RT_ERROR;
  508. }
  509. if (l1c_dc_is_enabled()) {
  510. /* cache invalidate for receive buff */
  511. l1c_dc_invalidate((uint32_t)readBuf, size);
  512. }
  513. }
  514. return size;
  515. }
  516. static void hpm_i2s_buffer_info(struct rt_audio_device* audio, struct rt_audio_buf_info* info)
  517. {
  518. RT_ASSERT(audio != RT_NULL);
  519. struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data;
  520. /**
  521. * AUD_FIFO
  522. * +----------------+----------------+
  523. * | block1 | block2 |
  524. * +----------------+----------------+
  525. * \ block_size /
  526. */
  527. info->buffer = hpm_audio->tx_buff;
  528. info->total_size = I2S_FIFO_SIZE;
  529. info->block_size = I2S_FIFO_SIZE / 2;
  530. info->block_count = 2;
  531. }
  532. static struct rt_audio_ops hpm_i2s_ops =
  533. {
  534. .getcaps = hpm_i2s_getcaps,
  535. .configure = hpm_i2s_configure,
  536. .init = hpm_i2s_init,
  537. .start = hpm_i2s_start,
  538. .stop = hpm_i2s_stop,
  539. .transmit = hpm_i2s_transmit,
  540. .buffer_info = hpm_i2s_buffer_info,
  541. };
  542. int rt_hw_i2s_init(void)
  543. {
  544. rt_err_t ret = RT_EOK;
  545. for (uint32_t i = 0; i < sizeof(hpm_i2s_set) / sizeof(hpm_i2s_set[0]); i++) {
  546. hpm_i2s_set[i].audio.ops = &hpm_i2s_ops;
  547. ret = rt_audio_register(&hpm_i2s_set[i].audio, hpm_i2s_set[i].dev_name, RT_DEVICE_FLAG_RDWR, &hpm_i2s_set[i]);
  548. if (ret != RT_EOK)
  549. {
  550. LOG_E("rt audio %s register failed, status=%d\n", hpm_i2s_set[i].dev_name, ret);
  551. }
  552. }
  553. return RT_EOK;
  554. }
  555. INIT_DEVICE_EXPORT(rt_hw_i2s_init);
  556. #endif /* BSP_USING_I2S */