dma_config.h 7.3 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-01-02 SummerGift first version
  9. * 2019-01-08 SummerGift clean up the code
  10. */
  11. #ifndef __DMA_CONFIG_H__
  12. #define __DMA_CONFIG_H__
  13. #include <rtthread.h>
  14. #ifdef __cplusplus
  15. extern "C" {
  16. #endif
  17. /* DMA1 channel1 */
  18. #if defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE)
  19. #define ADC1_DMA_IRQHandler DMA1_Channel1_IRQHandler
  20. #define ADC1_DMA_RCC RCC_AHBENR_DMA1EN
  21. #define ADC1_DMA_INSTANCE DMA1_Channel1
  22. #define ADC1_DMA_IRQ DMA1_Channel1_IRQn
  23. #endif
  24. /* DMA1 channel2 */
  25. #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
  26. #define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
  27. #define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
  28. #define SPI1_RX_DMA_INSTANCE DMA1_Channel2
  29. #define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
  30. #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
  31. #define UART3_DMA_TX_IRQHandler DMA1_Channel2_IRQHandler
  32. #define UART3_TX_DMA_RCC RCC_AHBENR_DMA1EN
  33. #define UART3_TX_DMA_INSTANCE DMA1_Channel2
  34. #define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn
  35. #endif
  36. /* DMA1 channel3 */
  37. #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
  38. #define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
  39. #define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
  40. #define SPI1_TX_DMA_INSTANCE DMA1_Channel3
  41. #define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
  42. #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
  43. #define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
  44. #define UART3_RX_DMA_RCC RCC_AHBENR_DMA1EN
  45. #define UART3_RX_DMA_INSTANCE DMA1_Channel3
  46. #define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
  47. #endif
  48. /* DMA1 channel4 */
  49. #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
  50. #define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
  51. #define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
  52. #define SPI2_RX_DMA_INSTANCE DMA1_Channel4
  53. #define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
  54. #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
  55. #define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
  56. #define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN
  57. #define UART1_TX_DMA_INSTANCE DMA1_Channel4
  58. #define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn
  59. #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
  60. #define I2C2_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
  61. #define I2C2_TX_DMA_RCC RCC_AHBENR_DMA1EN
  62. #define I2C2_TX_DMA_INSTANCE DMA1_Channel4
  63. #define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn
  64. #endif
  65. /* DMA1 channel5 */
  66. #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
  67. #define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
  68. #define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
  69. #define SPI2_TX_DMA_INSTANCE DMA1_Channel5
  70. #define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn
  71. #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
  72. #define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
  73. #define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
  74. #define UART1_RX_DMA_INSTANCE DMA1_Channel5
  75. #define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn
  76. #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
  77. #define I2C2_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
  78. #define I2C2_RX_DMA_RCC RCC_AHBENR_DMA1EN
  79. #define I2C2_RX_DMA_INSTANCE DMA1_Channel5
  80. #define I2C2_RX_DMA_IRQ DMA1_Channel5_IRQn
  81. #endif
  82. /* DMA1 channel6 */
  83. #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
  84. #define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
  85. #define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
  86. #define UART2_RX_DMA_INSTANCE DMA1_Channel6
  87. #define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn
  88. #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
  89. #define I2C1_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler
  90. #define I2C1_TX_DMA_RCC RCC_AHBENR_DMA1EN
  91. #define I2C1_TX_DMA_INSTANCE DMA1_Channel6
  92. #define I2C1_TX_DMA_IRQ DMA1_Channel6_IRQn
  93. #endif
  94. /* DMA1 channel7 */
  95. #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
  96. #define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler
  97. #define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN
  98. #define UART2_TX_DMA_INSTANCE DMA1_Channel7
  99. #define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn
  100. #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
  101. #define I2C1_DMA_RX_IRQHandler DMA1_Channel7_IRQHandler
  102. #define I2C1_RX_DMA_RCC RCC_AHBENR_DMA1EN
  103. #define I2C1_RX_DMA_INSTANCE DMA1_Channel7
  104. #define I2C1_RX_DMA_IRQ DMA1_Channel7_IRQn
  105. #endif
  106. /* DMA2 channel1 */
  107. #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
  108. #define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
  109. #define SPI3_RX_DMA_RCC RCC_AHBENR_DMA2EN
  110. #define SPI3_RX_DMA_INSTANCE DMA2_Channel1
  111. #define SPI3_RX_DMA_IRQ DMA2_Channel1_IRQn
  112. #endif
  113. /* DMA2 channel2 */
  114. #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
  115. #define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
  116. #define SPI3_TX_DMA_RCC RCC_AHBENR_DMA2EN
  117. #define SPI3_TX_DMA_INSTANCE DMA2_Channel2
  118. #define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn
  119. #endif
  120. /* DMA2 channel3 */
  121. #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
  122. #define UART4_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
  123. #define UART4_RX_DMA_RCC RCC_AHBENR_DMA2EN
  124. #define UART4_RX_DMA_INSTANCE DMA2_Channel3
  125. #define UART4_RX_DMA_IRQ DMA2_Channel3_IRQn
  126. #endif
  127. /* DMA2 channel4 */
  128. #if defined(BSP_SDIO_TX_USING_DMA) && !defined(SDIO_TX_DMA_INSTANCE)
  129. #define SDIO_DMA_TX_IRQHandler DMA2_Channel4_5_IRQHandler
  130. #define SDIO_TX_DMA_RCC RCC_AHBENR_DMA2EN
  131. #define SDIO_TX_DMA_INSTANCE DMA2_Channel4
  132. #define SDIO_TX_DMA_IRQ DMA2_Channel4_5_IRQn
  133. #elif defined(BSP_SDIO_RX_USING_DMA) && !defined(SDIO_RX_DMA_INSTANCE)
  134. #define SDIO_DMA_RX_IRQHandler DMA2_Channel4_5_IRQHandler
  135. #define SDIO_RX_DMA_RCC RCC_AHBENR_DMA2EN
  136. #define SDIO_RX_DMA_INSTANCE DMA2_Channel4
  137. #define SDIO_RX_DMA_IRQ DMA2_Channel4_5_IRQn
  138. #endif
  139. /* DMA2 channel5 */
  140. #if defined(BSP_ADC3_USING_DMA) && !defined(ADC3_DMA_INSTANCE)
  141. #define ADC3_DMA_IRQHandler DMA2_Channel4_5_IRQHandler
  142. #define ADC3_DMA_RCC RCC_AHBENR_DMA2EN
  143. #define ADC3_DMA_INSTANCE DMA2_Channel5
  144. #define ADC3_DMA_IRQ DMA2_Channel4_5_IRQn
  145. #elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
  146. #define UART4_DMA_TX_IRQHandler DMA2_Channel4_5_IRQHandler
  147. #define UART4_TX_DMA_RCC RCC_AHBENR_DMA2EN
  148. #define UART4_TX_DMA_INSTANCE DMA2_Channel5
  149. #define UART4_TX_DMA_IRQ DMA2_Channel4_5_IRQn
  150. #endif
  151. #ifdef __cplusplus
  152. }
  153. #endif
  154. #endif /* __DMA_CONFIG_H__ */