adc.c 53 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470
  1. //*****************************************************************************
  2. //
  3. // adc.c - Driver for the ADC.
  4. //
  5. // Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Texas Instruments (TI) is supplying this software for use solely and
  9. // exclusively on TI's microcontroller products. The software is owned by
  10. // TI and/or its suppliers, and is protected under applicable copyright
  11. // laws. You may not combine this software with "viral" open-source
  12. // software in order to form a larger program.
  13. //
  14. // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
  15. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
  16. // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  17. // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
  18. // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  19. // DAMAGES, FOR ANY REASON WHATSOEVER.
  20. //
  21. // This is part of revision 6459 of the Stellaris Peripheral Driver Library.
  22. //
  23. //*****************************************************************************
  24. //*****************************************************************************
  25. //
  26. //! \addtogroup adc_api
  27. //! @{
  28. //
  29. //*****************************************************************************
  30. #include "inc/hw_adc.h"
  31. #include "inc/hw_ints.h"
  32. #include "inc/hw_memmap.h"
  33. #include "inc/hw_types.h"
  34. #include "driverlib/adc.h"
  35. #include "driverlib/debug.h"
  36. #include "driverlib/interrupt.h"
  37. //*****************************************************************************
  38. //
  39. // These defines are used by the ADC driver to simplify access to the ADC
  40. // sequencer's registers.
  41. //
  42. //*****************************************************************************
  43. #define ADC_SEQ (ADC_O_SSMUX0)
  44. #define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
  45. #define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
  46. #define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
  47. #define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
  48. #define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
  49. #define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0)
  50. #define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0)
  51. //*****************************************************************************
  52. //
  53. // The currently configured software oversampling factor for each of the ADC
  54. // sequencers.
  55. //
  56. //*****************************************************************************
  57. static unsigned char g_pucOversampleFactor[3];
  58. //*****************************************************************************
  59. //
  60. //! Registers an interrupt handler for an ADC interrupt.
  61. //!
  62. //! \param ulBase is the base address of the ADC module.
  63. //! \param ulSequenceNum is the sample sequence number.
  64. //! \param pfnHandler is a pointer to the function to be called when the
  65. //! ADC sample sequence interrupt occurs.
  66. //!
  67. //! This function sets the handler to be called when a sample sequence
  68. //! interrupt occurs. This will enable the global interrupt in the interrupt
  69. //! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
  70. //! is the interrupt handler's responsibility to clear the interrupt source via
  71. //! ADCIntClear().
  72. //!
  73. //! \sa IntRegister() for important information about registering interrupt
  74. //! handlers.
  75. //!
  76. //! \return None.
  77. //
  78. //*****************************************************************************
  79. void
  80. ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
  81. void (*pfnHandler)(void))
  82. {
  83. unsigned long ulInt;
  84. //
  85. // Check the arguments.
  86. //
  87. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  88. ASSERT(ulSequenceNum < 4);
  89. //
  90. // Determine the interrupt to register based on the sequence number.
  91. //
  92. ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) :
  93. (INT_ADC1SS0 + ulSequenceNum));
  94. //
  95. // Register the interrupt handler.
  96. //
  97. IntRegister(ulInt, pfnHandler);
  98. //
  99. // Enable the timer interrupt.
  100. //
  101. IntEnable(ulInt);
  102. }
  103. //*****************************************************************************
  104. //
  105. //! Unregisters the interrupt handler for an ADC interrupt.
  106. //!
  107. //! \param ulBase is the base address of the ADC module.
  108. //! \param ulSequenceNum is the sample sequence number.
  109. //!
  110. //! This function unregisters the interrupt handler. This will disable the
  111. //! global interrupt in the interrupt controller; the sequence interrupt must
  112. //! be disabled via ADCIntDisable().
  113. //!
  114. //! \sa IntRegister() for important information about registering interrupt
  115. //! handlers.
  116. //!
  117. //! \return None.
  118. //
  119. //*****************************************************************************
  120. void
  121. ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
  122. {
  123. unsigned long ulInt;
  124. //
  125. // Check the arguments.
  126. //
  127. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  128. ASSERT(ulSequenceNum < 4);
  129. //
  130. // Determine the interrupt to unregister based on the sequence number.
  131. //
  132. ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) :
  133. (INT_ADC1SS0 + ulSequenceNum));
  134. //
  135. // Disable the interrupt.
  136. //
  137. IntDisable(ulInt);
  138. //
  139. // Unregister the interrupt handler.
  140. //
  141. IntUnregister(ulInt);
  142. }
  143. //*****************************************************************************
  144. //
  145. //! Disables a sample sequence interrupt.
  146. //!
  147. //! \param ulBase is the base address of the ADC module.
  148. //! \param ulSequenceNum is the sample sequence number.
  149. //!
  150. //! This function disables the requested sample sequence interrupt.
  151. //!
  152. //! \return None.
  153. //
  154. //*****************************************************************************
  155. void
  156. ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
  157. {
  158. //
  159. // Check the arguments.
  160. //
  161. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  162. ASSERT(ulSequenceNum < 4);
  163. //
  164. // Disable this sample sequence interrupt.
  165. //
  166. HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum);
  167. }
  168. //*****************************************************************************
  169. //
  170. //! Enables a sample sequence interrupt.
  171. //!
  172. //! \param ulBase is the base address of the ADC module.
  173. //! \param ulSequenceNum is the sample sequence number.
  174. //!
  175. //! This function enables the requested sample sequence interrupt. Any
  176. //! outstanding interrupts are cleared before enabling the sample sequence
  177. //! interrupt.
  178. //!
  179. //! \return None.
  180. //
  181. //*****************************************************************************
  182. void
  183. ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
  184. {
  185. //
  186. // Check the arguments.
  187. //
  188. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  189. ASSERT(ulSequenceNum < 4);
  190. //
  191. // Clear any outstanding interrupts on this sample sequence.
  192. //
  193. HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
  194. //
  195. // Enable this sample sequence interrupt.
  196. //
  197. HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum;
  198. }
  199. //*****************************************************************************
  200. //
  201. //! Gets the current interrupt status.
  202. //!
  203. //! \param ulBase is the base address of the ADC module.
  204. //! \param ulSequenceNum is the sample sequence number.
  205. //! \param bMasked is false if the raw interrupt status is required and true if
  206. //! the masked interrupt status is required.
  207. //!
  208. //! This returns the interrupt status for the specified sample sequence.
  209. //! Either the raw interrupt status or the status of interrupts that are
  210. //! allowed to reflect to the processor can be returned.
  211. //!
  212. //! \return The current raw or masked interrupt status.
  213. //
  214. //*****************************************************************************
  215. unsigned long
  216. ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
  217. tBoolean bMasked)
  218. {
  219. unsigned long ulTemp;
  220. //
  221. // Check the arguments.
  222. //
  223. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  224. ASSERT(ulSequenceNum < 4);
  225. //
  226. // Return either the interrupt status or the raw interrupt status as
  227. // requested.
  228. //
  229. if(bMasked)
  230. {
  231. ulTemp = HWREG(ulBase + ADC_O_ISC) & (0x10001 << ulSequenceNum);
  232. }
  233. else
  234. {
  235. ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum));
  236. //
  237. // If the digital comparator status bit is set, reflect it to the
  238. // appropriate sequence bit.
  239. //
  240. if(ulTemp & 0x10000)
  241. {
  242. ulTemp |= 0xF0000;
  243. ulTemp &= ~(0x10000 << ulSequenceNum);
  244. }
  245. }
  246. //
  247. // Return the interrupt status
  248. //
  249. return(ulTemp);
  250. }
  251. //*****************************************************************************
  252. //
  253. //! Clears sample sequence interrupt source.
  254. //!
  255. //! \param ulBase is the base address of the ADC module.
  256. //! \param ulSequenceNum is the sample sequence number.
  257. //!
  258. //! The specified sample sequence interrupt is cleared, so that it no longer
  259. //! asserts. This must be done in the interrupt handler to keep it from being
  260. //! called again immediately upon exit.
  261. //!
  262. //! \note Since there is a write buffer in the Cortex-M3 processor, it may take
  263. //! several clock cycles before the interrupt source is actually cleared.
  264. //! Therefore, it is recommended that the interrupt source be cleared early in
  265. //! the interrupt handler (as opposed to the very last action) to avoid
  266. //! returning from the interrupt handler before the interrupt source is
  267. //! actually cleared. Failure to do so may result in the interrupt handler
  268. //! being immediately reentered (since NVIC still sees the interrupt source
  269. //! asserted).
  270. //!
  271. //! \return None.
  272. //
  273. //*****************************************************************************
  274. void
  275. ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)
  276. {
  277. //
  278. // Check the arugments.
  279. //
  280. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  281. ASSERT(ulSequenceNum < 4);
  282. //
  283. // Clear the interrupt.
  284. //
  285. HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
  286. }
  287. //*****************************************************************************
  288. //
  289. //! Enables a sample sequence.
  290. //!
  291. //! \param ulBase is the base address of the ADC module.
  292. //! \param ulSequenceNum is the sample sequence number.
  293. //!
  294. //! Allows the specified sample sequence to be captured when its trigger is
  295. //! detected. A sample sequence must be configured before it is enabled.
  296. //!
  297. //! \return None.
  298. //
  299. //*****************************************************************************
  300. void
  301. ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)
  302. {
  303. //
  304. // Check the arugments.
  305. //
  306. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  307. ASSERT(ulSequenceNum < 4);
  308. //
  309. // Enable the specified sequence.
  310. //
  311. HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum;
  312. }
  313. //*****************************************************************************
  314. //
  315. //! Disables a sample sequence.
  316. //!
  317. //! \param ulBase is the base address of the ADC module.
  318. //! \param ulSequenceNum is the sample sequence number.
  319. //!
  320. //! Prevents the specified sample sequence from being captured when its trigger
  321. //! is detected. A sample sequence should be disabled before it is configured.
  322. //!
  323. //! \return None.
  324. //
  325. //*****************************************************************************
  326. void
  327. ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
  328. {
  329. //
  330. // Check the arugments.
  331. //
  332. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  333. ASSERT(ulSequenceNum < 4);
  334. //
  335. // Disable the specified sequences.
  336. //
  337. HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum);
  338. }
  339. //*****************************************************************************
  340. //
  341. //! Configures the trigger source and priority of a sample sequence.
  342. //!
  343. //! \param ulBase is the base address of the ADC module.
  344. //! \param ulSequenceNum is the sample sequence number.
  345. //! \param ulTrigger is the trigger source that initiates the sample sequence;
  346. //! must be one of the \b ADC_TRIGGER_* values.
  347. //! \param ulPriority is the relative priority of the sample sequence with
  348. //! respect to the other sample sequences.
  349. //!
  350. //! This function configures the initiation criteria for a sample sequence.
  351. //! Valid sample sequences range from zero to three; sequence zero will capture
  352. //! up to eight samples, sequences one and two will capture up to four samples,
  353. //! and sequence three will capture a single sample. The trigger condition and
  354. //! priority (with respect to other sample sequence execution) is set.
  355. //!
  356. //! The \e ulTrigger parameter can take on the following values:
  357. //!
  358. //! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
  359. //! ADCProcessorTrigger() function.
  360. //! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
  361. //! comparator; configured with ComparatorConfigure().
  362. //! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
  363. //! comparator; configured with ComparatorConfigure().
  364. //! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
  365. //! comparator; configured with ComparatorConfigure().
  366. //! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
  367. //! B4 pin.
  368. //! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
  369. //! TimerControlTrigger().
  370. //! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
  371. //! configured with PWMGenIntTrigEnable().
  372. //! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
  373. //! configured with PWMGenIntTrigEnable().
  374. //! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
  375. //! configured with PWMGenIntTrigEnable().
  376. //! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator;
  377. //! configured with PWMGenIntTrigEnable().
  378. //! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
  379. //! sample sequence to capture repeatedly (so long as
  380. //! there is not a higher priority source active).
  381. //!
  382. //! Note that not all trigger sources are available on all Stellaris family
  383. //! members; consult the data sheet for the device in question to determine the
  384. //! availability of triggers.
  385. //!
  386. //! The \e ulPriority parameter is a value between 0 and 3, where 0 represents
  387. //! the highest priority and 3 the lowest. Note that when programming the
  388. //! priority among a set of sample sequences, each must have unique priority;
  389. //! it is up to the caller to guarantee the uniqueness of the priorities.
  390. //!
  391. //! \return None.
  392. //
  393. //*****************************************************************************
  394. void
  395. ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
  396. unsigned long ulTrigger, unsigned long ulPriority)
  397. {
  398. //
  399. // Check the arugments.
  400. //
  401. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  402. ASSERT(ulSequenceNum < 4);
  403. ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||
  404. (ulTrigger == ADC_TRIGGER_COMP0) ||
  405. (ulTrigger == ADC_TRIGGER_COMP1) ||
  406. (ulTrigger == ADC_TRIGGER_COMP2) ||
  407. (ulTrigger == ADC_TRIGGER_EXTERNAL) ||
  408. (ulTrigger == ADC_TRIGGER_TIMER) ||
  409. (ulTrigger == ADC_TRIGGER_PWM0) ||
  410. (ulTrigger == ADC_TRIGGER_PWM1) ||
  411. (ulTrigger == ADC_TRIGGER_PWM2) ||
  412. (ulTrigger == ADC_TRIGGER_PWM3) ||
  413. (ulTrigger == ADC_TRIGGER_ALWAYS));
  414. ASSERT(ulPriority < 4);
  415. //
  416. // Compute the shift for the bits that control this sample sequence.
  417. //
  418. ulSequenceNum *= 4;
  419. //
  420. // Set the trigger event for this sample sequence.
  421. //
  422. HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) &
  423. ~(0xf << ulSequenceNum)) |
  424. ((ulTrigger & 0xf) << ulSequenceNum));
  425. //
  426. // Set the priority for this sample sequence.
  427. //
  428. HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) &
  429. ~(0xf << ulSequenceNum)) |
  430. ((ulPriority & 0x3) << ulSequenceNum));
  431. }
  432. //*****************************************************************************
  433. //
  434. //! Configure a step of the sample sequencer.
  435. //!
  436. //! \param ulBase is the base address of the ADC module.
  437. //! \param ulSequenceNum is the sample sequence number.
  438. //! \param ulStep is the step to be configured.
  439. //! \param ulConfig is the configuration of this step; must be a logical OR of
  440. //! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
  441. //! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15). For parts
  442. //! with the digital comparator feature, the follow values may also be OR'd
  443. //! into the \e ulConfig value to enable the digital comparater feature:
  444. //! \b ADC_CTL_CE and one of the comparater selects (\b ADC_CTL_CMP0 through
  445. //! \b ADC_CTL_CMP7).
  446. //!
  447. //! This function will set the configuration of the ADC for one step of a
  448. //! sample sequence. The ADC can be configured for single-ended or
  449. //! differential operation (the \b ADC_CTL_D bit selects differential
  450. //! operation when set), the channel to be sampled can be chosen (the
  451. //! \b ADC_CTL_CH0 through \b ADC_CTL_CH15 values), and the internal
  452. //! temperature sensor can be selected (the \b ADC_CTL_TS bit). Additionally,
  453. //! this step can be defined as the last in the sequence (the \b ADC_CTL_END
  454. //! bit) and it can be configured to cause an interrupt when the step is
  455. //! complete (the \b ADC_CTL_IE bit). If the digital comparators are present
  456. //! on the device, this step may also be configured send the ADC sample to
  457. //! the selected comparator (the \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7
  458. //! values) by using the \b ADC_CTL_CE bit. The configuration is used by the
  459. //! ADC at the appropriate time when the trigger for this sequence occurs.
  460. //!
  461. //! \note If the Digitial Comparator is present and enabled using the
  462. //! \b ADC_CTL_CE bit, the ADC sample will NOT be written into the ADC
  463. //! sequence data FIFO.
  464. //!
  465. //! The \e ulStep parameter determines the order in which the samples are
  466. //! captured by the ADC when the trigger occurs. It can range from zero to
  467. //! seven for the first sample sequence, from zero to three for the second and
  468. //! third sample sequence, and can only be zero for the fourth sample sequence.
  469. //!
  470. //! Differential mode only works with adjacent channel pairs (for example, 0
  471. //! and 1). The channel select must be the number of the channel pair to
  472. //! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
  473. //! and 3) or undefined results will be returned by the ADC. Additionally, if
  474. //! differential mode is selected when the temperature sensor is being sampled,
  475. //! undefined results will be returned by the ADC.
  476. //!
  477. //! It is the responsibility of the caller to ensure that a valid configuration
  478. //! is specified; this function does not check the validity of the specified
  479. //! configuration.
  480. //!
  481. //! \return None.
  482. //
  483. //*****************************************************************************
  484. void
  485. ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
  486. unsigned long ulStep, unsigned long ulConfig)
  487. {
  488. unsigned long ulTemp;
  489. //
  490. // Check the arugments.
  491. //
  492. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  493. ASSERT(ulSequenceNum < 4);
  494. ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||
  495. ((ulSequenceNum == 1) && (ulStep < 4)) ||
  496. ((ulSequenceNum == 2) && (ulStep < 4)) ||
  497. ((ulSequenceNum == 3) && (ulStep < 1)));
  498. //
  499. // Get the offset of the sequence to be configured.
  500. //
  501. ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
  502. //
  503. // Compute the shift for the bits that control this step.
  504. //
  505. ulStep *= 4;
  506. //
  507. // Set the analog mux value for this step.
  508. //
  509. HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
  510. ~(0x0000000f << ulStep)) |
  511. ((ulConfig & 0x0f) << ulStep));
  512. //
  513. // Set the control value for this step.
  514. //
  515. HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
  516. ~(0x0000000f << ulStep)) |
  517. (((ulConfig & 0xf0) >> 4) << ulStep));
  518. //
  519. // Enable digital comparator if specified in the ulConfig bit-fields.
  520. //
  521. if(ulConfig & 0x000F0000)
  522. {
  523. //
  524. // Program the comparator for the specified step.
  525. //
  526. ulTemp = HWREG(ulBase + ADC_SSDC);
  527. ulTemp &= ~(0xF << ulStep);
  528. ulTemp |= (((ulConfig & 0x00070000) >> 16) << ulStep);
  529. HWREG(ulBase + ADC_SSDC) = ulTemp;
  530. //
  531. // Enable the comparator.
  532. //
  533. ulTemp = HWREG(ulBase + ADC_SSOP);
  534. ulTemp |= (1 << ulStep);
  535. HWREG(ulBase + ADC_SSOP) = ulTemp;
  536. }
  537. //
  538. // Disable digital comparator if not specified.
  539. //
  540. else
  541. {
  542. ulTemp = HWREG(ulBase + ADC_SSOP);
  543. ulTemp &= ~(1 << ulStep);
  544. HWREG(ulBase + ADC_SSOP) = ulTemp;
  545. }
  546. }
  547. //*****************************************************************************
  548. //
  549. //! Determines if a sample sequence overflow occurred.
  550. //!
  551. //! \param ulBase is the base address of the ADC module.
  552. //! \param ulSequenceNum is the sample sequence number.
  553. //!
  554. //! This determines if a sample sequence overflow has occurred. This will
  555. //! happen if the captured samples are not read from the FIFO before the next
  556. //! trigger occurs.
  557. //!
  558. //! \return Returns zero if there was not an overflow, and non-zero if there
  559. //! was.
  560. //
  561. //*****************************************************************************
  562. long
  563. ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
  564. {
  565. //
  566. // Check the arguments.
  567. //
  568. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  569. ASSERT(ulSequenceNum < 4);
  570. //
  571. // Determine if there was an overflow on this sequence.
  572. //
  573. return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum));
  574. }
  575. //*****************************************************************************
  576. //
  577. //! Clears the overflow condition on a sample sequence.
  578. //!
  579. //! \param ulBase is the base address of the ADC module.
  580. //! \param ulSequenceNum is the sample sequence number.
  581. //!
  582. //! This will clear an overflow condition on one of the sample sequences. The
  583. //! overflow condition must be cleared in order to detect a subsequent overflow
  584. //! condition (it otherwise causes no harm).
  585. //!
  586. //! \return None.
  587. //
  588. //*****************************************************************************
  589. void
  590. ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
  591. {
  592. //
  593. // Check the arguments.
  594. //
  595. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  596. ASSERT(ulSequenceNum < 4);
  597. //
  598. // Clear the overflow condition for this sequence.
  599. //
  600. HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum;
  601. }
  602. //*****************************************************************************
  603. //
  604. //! Determines if a sample sequence underflow occurred.
  605. //!
  606. //! \param ulBase is the base address of the ADC module.
  607. //! \param ulSequenceNum is the sample sequence number.
  608. //!
  609. //! This determines if a sample sequence underflow has occurred. This will
  610. //! happen if too many samples are read from the FIFO.
  611. //!
  612. //! \return Returns zero if there was not an underflow, and non-zero if there
  613. //! was.
  614. //
  615. //*****************************************************************************
  616. long
  617. ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
  618. {
  619. //
  620. // Check the arguments.
  621. //
  622. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  623. ASSERT(ulSequenceNum < 4);
  624. //
  625. // Determine if there was an underflow on this sequence.
  626. //
  627. return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum));
  628. }
  629. //*****************************************************************************
  630. //
  631. //! Clears the underflow condition on a sample sequence.
  632. //!
  633. //! \param ulBase is the base address of the ADC module.
  634. //! \param ulSequenceNum is the sample sequence number.
  635. //!
  636. //! This will clear an underflow condition on one of the sample sequences. The
  637. //! underflow condition must be cleared in order to detect a subsequent
  638. //! underflow condition (it otherwise causes no harm).
  639. //!
  640. //! \return None.
  641. //
  642. //*****************************************************************************
  643. void
  644. ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
  645. {
  646. //
  647. // Check the arguments.
  648. //
  649. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  650. ASSERT(ulSequenceNum < 4);
  651. //
  652. // Clear the underflow condition for this sequence.
  653. //
  654. HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum;
  655. }
  656. //*****************************************************************************
  657. //
  658. //! Gets the captured data for a sample sequence.
  659. //!
  660. //! \param ulBase is the base address of the ADC module.
  661. //! \param ulSequenceNum is the sample sequence number.
  662. //! \param pulBuffer is the address where the data is stored.
  663. //!
  664. //! This function copies data from the specified sample sequence output FIFO to
  665. //! a memory resident buffer. The number of samples available in the hardware
  666. //! FIFO are copied into the buffer, which is assumed to be large enough to
  667. //! hold that many samples. This will only return the samples that are
  668. //! presently available, which may not be the entire sample sequence if it is
  669. //! in the process of being executed.
  670. //!
  671. //! \return Returns the number of samples copied to the buffer.
  672. //
  673. //*****************************************************************************
  674. long
  675. ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
  676. unsigned long *pulBuffer)
  677. {
  678. unsigned long ulCount;
  679. //
  680. // Check the arguments.
  681. //
  682. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  683. ASSERT(ulSequenceNum < 4);
  684. //
  685. // Get the offset of the sequence to be read.
  686. //
  687. ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
  688. //
  689. // Read samples from the FIFO until it is empty.
  690. //
  691. ulCount = 0;
  692. while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8))
  693. {
  694. //
  695. // Read the FIFO and copy it to the destination.
  696. //
  697. *pulBuffer++ = HWREG(ulBase + ADC_SSFIFO);
  698. //
  699. // Increment the count of samples read.
  700. //
  701. ulCount++;
  702. }
  703. //
  704. // Return the number of samples read.
  705. //
  706. return(ulCount);
  707. }
  708. //*****************************************************************************
  709. //
  710. //! Causes a processor trigger for a sample sequence.
  711. //!
  712. //! \param ulBase is the base address of the ADC module.
  713. //! \param ulSequenceNum is the sample sequence number, with
  714. //! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it.
  715. //!
  716. //! This function triggers a processor-initiated sample sequence if the sample
  717. //! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR. If
  718. //! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the
  719. //! processor-initiated trigger is delayed until a later processor-initiated
  720. //! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL,
  721. //! allowing multiple ADCs to start from a processor-initiated trigger in a
  722. //! synchronous manner.
  723. //!
  724. //! \return None.
  725. //
  726. //*****************************************************************************
  727. void
  728. ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
  729. {
  730. //
  731. // Check the arguments.
  732. //
  733. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  734. ASSERT((ulSequenceNum & 0xf) < 4);
  735. //
  736. // Generate a processor trigger for this sample sequence.
  737. //
  738. HWREG(ulBase + ADC_O_PSSI) = ((ulSequenceNum & 0xffff0000) |
  739. (1 << (ulSequenceNum & 0xf)));
  740. }
  741. //*****************************************************************************
  742. //
  743. //! Configures the software oversampling factor of the ADC.
  744. //!
  745. //! \param ulBase is the base address of the ADC module.
  746. //! \param ulSequenceNum is the sample sequence number.
  747. //! \param ulFactor is the number of samples to be averaged.
  748. //!
  749. //! This function configures the software oversampling for the ADC, which can
  750. //! be used to provide better resolution on the sampled data. Oversampling is
  751. //! accomplished by averaging multiple samples from the same analog input.
  752. //! Three different oversampling rates are supported; 2x, 4x, and 8x.
  753. //!
  754. //! Oversampling is only supported on the sample sequencers that are more than
  755. //! one sample in depth (that is, the fourth sample sequencer is not
  756. //! supported). Oversampling by 2x (for example) divides the depth of the
  757. //! sample sequencer by two; so 2x oversampling on the first sample sequencer
  758. //! can only provide four samples per trigger. This also means that 8x
  759. //! oversampling is only available on the first sample sequencer.
  760. //!
  761. //! \return None.
  762. //
  763. //*****************************************************************************
  764. void
  765. ADCSoftwareOversampleConfigure(unsigned long ulBase,
  766. unsigned long ulSequenceNum,
  767. unsigned long ulFactor)
  768. {
  769. unsigned long ulValue;
  770. //
  771. // Check the arguments.
  772. //
  773. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  774. ASSERT(ulSequenceNum < 3);
  775. ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&
  776. ((ulSequenceNum == 0) || (ulFactor != 8)));
  777. //
  778. // Convert the oversampling factor to a shift factor.
  779. //
  780. for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
  781. {
  782. }
  783. //
  784. // Save the sfiht factor.
  785. //
  786. g_pucOversampleFactor[ulSequenceNum] = ulValue;
  787. }
  788. //*****************************************************************************
  789. //
  790. //! Configures a step of the software oversampled sequencer.
  791. //!
  792. //! \param ulBase is the base address of the ADC module.
  793. //! \param ulSequenceNum is the sample sequence number.
  794. //! \param ulStep is the step to be configured.
  795. //! \param ulConfig is the configuration of this step.
  796. //!
  797. //! This function configures a step of the sample sequencer when using the
  798. //! software oversampling feature. The number of steps available depends on
  799. //! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value
  800. //! of \e ulConfig is the same as defined for ADCSequenceStepConfigure().
  801. //!
  802. //! \return None.
  803. //
  804. //*****************************************************************************
  805. void
  806. ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
  807. unsigned long ulSequenceNum,
  808. unsigned long ulStep,
  809. unsigned long ulConfig)
  810. {
  811. //
  812. // Check the arguments.
  813. //
  814. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  815. ASSERT(ulSequenceNum < 3);
  816. ASSERT(((ulSequenceNum == 0) &&
  817. (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
  818. (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum])));
  819. //
  820. // Get the offset of the sequence to be configured.
  821. //
  822. ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
  823. //
  824. // Compute the shift for the bits that control this step.
  825. //
  826. ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum];
  827. //
  828. // Loop through the hardware steps that make up this step of the software
  829. // oversampled sequence.
  830. //
  831. for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum];
  832. ulSequenceNum; ulSequenceNum--)
  833. {
  834. //
  835. // Set the analog mux value for this step.
  836. //
  837. HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
  838. ~(0x0000000f << ulStep)) |
  839. ((ulConfig & 0x0f) << ulStep));
  840. //
  841. // Set the control value for this step.
  842. //
  843. HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
  844. ~(0x0000000f << ulStep)) |
  845. (((ulConfig & 0xf0) >> 4) << ulStep));
  846. if(ulSequenceNum != 1)
  847. {
  848. HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 |
  849. ADC_SSCTL0_END0) << ulStep);
  850. }
  851. //
  852. // Go to the next hardware step.
  853. //
  854. ulStep += 4;
  855. }
  856. }
  857. //*****************************************************************************
  858. //
  859. //! Gets the captured data for a sample sequence using software oversampling.
  860. //!
  861. //! \param ulBase is the base address of the ADC module.
  862. //! \param ulSequenceNum is the sample sequence number.
  863. //! \param pulBuffer is the address where the data is stored.
  864. //! \param ulCount is the number of samples to be read.
  865. //!
  866. //! This function copies data from the specified sample sequence output FIFO to
  867. //! a memory resident buffer with software oversampling applied. The requested
  868. //! number of samples are copied into the data buffer; if there are not enough
  869. //! samples in the hardware FIFO to satisfy this many oversampled data items
  870. //! then incorrect results will be returned. It is the caller's responsibility
  871. //! to read only the samples that are available and wait until enough data is
  872. //! available, for example as a result of receiving an interrupt.
  873. //!
  874. //! \return None.
  875. //
  876. //*****************************************************************************
  877. void
  878. ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
  879. unsigned long *pulBuffer, unsigned long ulCount)
  880. {
  881. unsigned long ulIdx, ulAccum;
  882. //
  883. // Check the arguments.
  884. //
  885. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  886. ASSERT(ulSequenceNum < 3);
  887. ASSERT(((ulSequenceNum == 0) &&
  888. (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
  889. (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum])));
  890. //
  891. // Get the offset of the sequence to be read.
  892. //
  893. ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
  894. //
  895. // Read the samples from the FIFO until it is empty.
  896. //
  897. while(ulCount--)
  898. {
  899. //
  900. // Compute the sum of the samples.
  901. //
  902. ulAccum = 0;
  903. for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--)
  904. {
  905. //
  906. // Read the FIFO and add it to the accumulator.
  907. //
  908. ulAccum += HWREG(ulBase + ADC_SSFIFO);
  909. }
  910. //
  911. // Write the averaged sample to the output buffer.
  912. //
  913. *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum];
  914. }
  915. }
  916. //*****************************************************************************
  917. //
  918. //! Configures the hardware oversampling factor of the ADC.
  919. //!
  920. //! \param ulBase is the base address of the ADC module.
  921. //! \param ulFactor is the number of samples to be averaged.
  922. //!
  923. //! This function configures the hardware oversampling for the ADC, which can
  924. //! be used to provide better resolution on the sampled data. Oversampling is
  925. //! accomplished by averaging multiple samples from the same analog input. Six
  926. //! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
  927. //! Specifying an oversampling factor of zero will disable hardware
  928. //! oversampling.
  929. //!
  930. //! Hardware oversampling applies uniformly to all sample sequencers. It does
  931. //! not reduce the depth of the sample sequencers like the software
  932. //! oversampling APIs; each sample written into the sample sequence FIFO is a
  933. //! fully oversampled analog input reading.
  934. //!
  935. //! Enabling hardware averaging increases the precision of the ADC at the cost
  936. //! of throughput. For example, enabling 4x oversampling reduces the
  937. //! throughput of a 250 Ksps ADC to 62.5 Ksps.
  938. //!
  939. //! \note Hardware oversampling is available beginning with Rev C0 of the
  940. //! Stellaris microcontroller.
  941. //!
  942. //! \return None.
  943. //
  944. //*****************************************************************************
  945. void
  946. ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
  947. {
  948. unsigned long ulValue;
  949. //
  950. // Check the arguments.
  951. //
  952. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  953. ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
  954. (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
  955. (ulFactor == 64)));
  956. //
  957. // Convert the oversampling factor to a shift factor.
  958. //
  959. for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
  960. {
  961. }
  962. //
  963. // Write the shift factor to the ADC to configure the hardware oversampler.
  964. //
  965. HWREG(ulBase + ADC_O_SAC) = ulValue;
  966. }
  967. //*****************************************************************************
  968. //
  969. //! Configures an ADC digital comparator.
  970. //!
  971. //! \param ulBase is the base address of the ADC module.
  972. //! \param ulComp is the index of the comparator to configure.
  973. //! \param ulConfig is the configuration of the comparator.
  974. //!
  975. //! This function will configure a comparator. The \e ulConfig parameter is
  976. //! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and
  977. //! \b ADC_COMP_INT_xxx values.
  978. //!
  979. //! The \b ADC_COMP_TRIG_xxx term can take on the following values:
  980. //!
  981. //! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition.
  982. //! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when
  983. //! ADC output is in the low-band.
  984. //! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC
  985. //! output transitions into the low-band.
  986. //! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when
  987. //! ADC output is in the low-band only if ADC output has been in the high-band
  988. //! since the last trigger output.
  989. //! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC
  990. //! output transitions into low-band only if ADC output has been in the
  991. //! high-band since the last trigger output.
  992. //! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when
  993. //! ADC output is in the mid-band.
  994. //! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC
  995. //! output transitions into the mid-band.
  996. //! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when
  997. //! ADC output is in the high-band.
  998. //! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC
  999. //! output transitions into the high-band.
  1000. //! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when
  1001. //! ADC output is in the high-band only if ADC output has been in the low-band
  1002. //! since the last trigger output.
  1003. //! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC
  1004. //! output transitions into high-band only if ADC output has been in the
  1005. //! low-band since the last trigger output.
  1006. //!
  1007. //! The \b ADC_COMP_INT_xxx term can take on the following values:
  1008. //!
  1009. //! - \b ADC_COMP_INT_NONE to never generate ADC interrupt.
  1010. //! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC
  1011. //! output is in the low-band.
  1012. //! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output
  1013. //! transitions into the low-band.
  1014. //! - \b ADC_COMP__INT_LOW_HALWAYS to always generate ADC interrupt when ADC
  1015. //! output is in the low-band only if ADC output has been in the high-band
  1016. //! since the last trigger output.
  1017. //! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output
  1018. //! transitions into low-band only if ADC output has been in the high-band
  1019. //! since the last trigger output.
  1020. //! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC
  1021. //! output is in the mid-band.
  1022. //! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output
  1023. //! transitions into the mid-band.
  1024. //! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC
  1025. //! output is in the high-band.
  1026. //! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output
  1027. //! transitions into the high-band.
  1028. //! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC
  1029. //! output is in the high-band only if ADC output has been in the low-band
  1030. //! since the last trigger output.
  1031. //! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output
  1032. //! transitions into high-band only if ADC output has been in the low-band
  1033. //! since the last trigger output.
  1034. //!
  1035. //! \return None.
  1036. //
  1037. //*****************************************************************************
  1038. void
  1039. ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
  1040. unsigned long ulConfig)
  1041. {
  1042. //
  1043. // Check the arguments.
  1044. //
  1045. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1046. ASSERT(ulComp < 8);
  1047. //
  1048. // Save the new setting.
  1049. //
  1050. HWREG(ulBase + ADC_O_DCCTL0 + (ulComp * 4)) = ulConfig;
  1051. }
  1052. //*****************************************************************************
  1053. //
  1054. //! Defines the ADC digital comparator regions.
  1055. //!
  1056. //! \param ulBase is the base address of the ADC module.
  1057. //! \param ulComp is the index of the comparator to configure.
  1058. //! \param ulLowRef is the reference point for the low/mid band threshold.
  1059. //! \param ulHighRef is the reference point for the mid/high band threshold.
  1060. //!
  1061. //! The ADC digital comparator operation is based on three ADC value regions:
  1062. //! - \b low-band is defined as any ADC value less than or equal to the
  1063. //! \e ulLowRef value.
  1064. //! - \b mid-band is defined as any ADC value greater than the \e ulLowRef
  1065. //! value but less than or equal to the \e ulHighRef value.
  1066. //! - \b high-band is defined as any ADC value greater than the \e ulHighRef
  1067. //! value.
  1068. //!
  1069. //! \return None.
  1070. //
  1071. //*****************************************************************************
  1072. void
  1073. ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
  1074. unsigned long ulLowRef, unsigned long ulHighRef)
  1075. {
  1076. //
  1077. // Check the arguments.
  1078. //
  1079. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1080. ASSERT(ulComp < 8);
  1081. ASSERT((ulLowRef < 1024) && (ulLowRef <= ulHighRef));
  1082. ASSERT(ulHighRef < 1024);
  1083. //
  1084. // Save the new region settings.
  1085. //
  1086. HWREG(ulBase + ADC_O_DCCMP0 + (ulComp * 4)) = (ulHighRef << 16) | ulLowRef;
  1087. }
  1088. //*****************************************************************************
  1089. //
  1090. //! Resets the current ADC digital comparator conditions.
  1091. //!
  1092. //! \param ulBase is the base address of the ADC module.
  1093. //! \param ulComp is the index of the comparator.
  1094. //! \param bTrigger is the flag to indicate reset of Trigger conditions.
  1095. //! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
  1096. //!
  1097. //! Because the digital comparator uses current and previous ADC values, this
  1098. //! function is provide to allow the comparator to be reset to its initial
  1099. //! value to prevent stale data from being used when a sequence is enabled.
  1100. //!
  1101. //! \return None.
  1102. //
  1103. //*****************************************************************************
  1104. void
  1105. ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
  1106. tBoolean bTrigger, tBoolean bInterrupt)
  1107. {
  1108. unsigned long ulTemp = 0;
  1109. //
  1110. // Check the arguments.
  1111. //
  1112. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1113. ASSERT(ulComp < 8);
  1114. //
  1115. // Set the appropriate bits to reset the trigger and/or interrupt
  1116. // comparator conditions.
  1117. //
  1118. if(bTrigger)
  1119. {
  1120. ulTemp |= (1 << (16 + ulComp));
  1121. }
  1122. if(bInterrupt)
  1123. {
  1124. ulTemp |= (1 << ulComp);
  1125. }
  1126. HWREG(ulBase + ADC_O_DCRIC) = ulTemp;
  1127. }
  1128. //*****************************************************************************
  1129. //
  1130. //! Disables a sample sequence comparator interrupt.
  1131. //!
  1132. //! \param ulBase is the base address of the ADC module.
  1133. //! \param ulSequenceNum is the sample sequence number.
  1134. //!
  1135. //! This function disables the requested sample sequence comparator interrupt.
  1136. //!
  1137. //! \return None.
  1138. //
  1139. //*****************************************************************************
  1140. void
  1141. ADCComparatorIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
  1142. {
  1143. //
  1144. // Check the arguments.
  1145. //
  1146. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1147. ASSERT(ulSequenceNum < 4);
  1148. //
  1149. // Disable this sample sequence comparator interrupt.
  1150. //
  1151. HWREG(ulBase + ADC_O_IM) &= ~(0x10000 << ulSequenceNum);
  1152. }
  1153. //*****************************************************************************
  1154. //
  1155. //! Enables a sample sequence comparator interrupt.
  1156. //!
  1157. //! \param ulBase is the base address of the ADC module.
  1158. //! \param ulSequenceNum is the sample sequence number.
  1159. //!
  1160. //! This function enables the requested sample sequence comparator interrupt.
  1161. //!
  1162. //! \return None.
  1163. //
  1164. //*****************************************************************************
  1165. void
  1166. ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
  1167. {
  1168. //
  1169. // Check the arguments.
  1170. //
  1171. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1172. ASSERT(ulSequenceNum < 4);
  1173. //
  1174. // Enable this sample sequence interrupt.
  1175. //
  1176. HWREG(ulBase + ADC_O_IM) |= 0x10000 << ulSequenceNum;
  1177. }
  1178. //*****************************************************************************
  1179. //
  1180. //! Gets the current comparator interrupt status.
  1181. //!
  1182. //! \param ulBase is the base address of the ADC module.
  1183. //!
  1184. //! This returns the digitial comparator interrupt status bits. This status
  1185. //! is sequence agnostic.
  1186. //!
  1187. //! \return The current comparator interrupt status.
  1188. //
  1189. //*****************************************************************************
  1190. unsigned long
  1191. ADCComparatorIntStatus(unsigned long ulBase)
  1192. {
  1193. //
  1194. // Check the arguments.
  1195. //
  1196. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1197. //
  1198. // Return the digitial comparator interrupt status.
  1199. //
  1200. return(HWREG(ulBase + ADC_O_DCISC));
  1201. }
  1202. //*****************************************************************************
  1203. //
  1204. //! Clears sample sequence comparator interrupt source.
  1205. //!
  1206. //! \param ulBase is the base address of the ADC module.
  1207. //! \param ulStatus is the bit-mapped interrupts status to clear.
  1208. //!
  1209. //! The specified interrupt status is cleared.
  1210. //!
  1211. //! \return None.
  1212. //
  1213. //*****************************************************************************
  1214. void
  1215. ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus)
  1216. {
  1217. //
  1218. // Check the arguments.
  1219. //
  1220. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1221. //
  1222. // Clear the interrupt.
  1223. //
  1224. HWREG(ulBase + ADC_O_DCISC) = ulStatus;
  1225. }
  1226. //*****************************************************************************
  1227. //
  1228. //! Selects the ADC reference.
  1229. //!
  1230. //! \param ulBase is the base address of the ADC module.
  1231. //! \param ulRef is the reference to use.
  1232. //!
  1233. //! The ADC reference is set as specified by \e ulRef. It must be one of
  1234. //! \b ADC_REF_INT or \b ADC_REF_EXT_3V, for internal or external reference.
  1235. //! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and
  1236. //! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then a 3V
  1237. //! reference must be supplied to the AVREF pin.
  1238. //!
  1239. //! \note The ADC reference can only be selected on parts that have an external
  1240. //! reference. Consult the data sheet for your part to determine if there is
  1241. //! an external reference.
  1242. //!
  1243. //! \return None.
  1244. //
  1245. //*****************************************************************************
  1246. void
  1247. ADCReferenceSet(unsigned long ulBase, unsigned long ulRef)
  1248. {
  1249. //
  1250. // Check the arguments.
  1251. //
  1252. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1253. ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V));
  1254. //
  1255. // Set the reference.
  1256. //
  1257. HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF) |
  1258. ulRef;
  1259. }
  1260. //*****************************************************************************
  1261. //
  1262. //! Returns the current setting of the ADC reference.
  1263. //!
  1264. //! \param ulBase is the base address of the ADC module.
  1265. //!
  1266. //! Returns the value of the ADC reference setting. The returned value will be
  1267. //! one of \b ADC_REF_INT or \b ADC_REF_EXT_3V.
  1268. //!
  1269. //! \note The value returned by this function is only meaningful if used on a
  1270. //! part that is capable of using an external reference. Consult the data
  1271. //! sheet for your part to determine if it has an external reference input.
  1272. //!
  1273. //! \return The current setting of the ADC reference.
  1274. //
  1275. //*****************************************************************************
  1276. unsigned long
  1277. ADCReferenceGet(unsigned long ulBase)
  1278. {
  1279. //
  1280. // Check the arguments.
  1281. //
  1282. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1283. //
  1284. // Return the value of the reference.
  1285. //
  1286. return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF);
  1287. }
  1288. //*****************************************************************************
  1289. //
  1290. //! Sets the phase delay between a trigger and the start of a sequence.
  1291. //!
  1292. //! \param ulBase is the base address of the ADC module.
  1293. //! \param ulPhase is the phase delay, specified as one of \b ADC_PHASE_0,
  1294. //! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
  1295. //! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
  1296. //! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
  1297. //! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
  1298. //!
  1299. //! This function sets the phase delay between the detection of an ADC trigger
  1300. //! event and the start of the sample sequence. By selecting a different phase
  1301. //! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and
  1302. //! \b ADC_PHASE_180) and having each ADC module sample the same analog input,
  1303. //! it is possible to increase the sampling rate of the analog input (with
  1304. //! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1,
  1305. //! N+3, N+5, and so on, coming from the second ADC). The ADC module has a
  1306. //! single phase delay that is applied to all sample sequences within that
  1307. //! module.
  1308. //!
  1309. //! \note This capability is not available on all parts.
  1310. //!
  1311. //! \return None.
  1312. //
  1313. //*****************************************************************************
  1314. void
  1315. ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase)
  1316. {
  1317. //
  1318. // Check the arguments.
  1319. //
  1320. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1321. ASSERT((ulPhase == ADC_PHASE_0) || (ulPhase == ADC_PHASE_22_5) ||
  1322. (ulPhase == ADC_PHASE_45) || (ulPhase == ADC_PHASE_67_5) ||
  1323. (ulPhase == ADC_PHASE_90) || (ulPhase == ADC_PHASE_112_5) ||
  1324. (ulPhase == ADC_PHASE_135) || (ulPhase == ADC_PHASE_157_5) ||
  1325. (ulPhase == ADC_PHASE_180) || (ulPhase == ADC_PHASE_202_5) ||
  1326. (ulPhase == ADC_PHASE_225) || (ulPhase == ADC_PHASE_247_5) ||
  1327. (ulPhase == ADC_PHASE_270) || (ulPhase == ADC_PHASE_292_5) ||
  1328. (ulPhase == ADC_PHASE_315) || (ulPhase == ADC_PHASE_337_5));
  1329. //
  1330. // Set the phase delay.
  1331. //
  1332. HWREG(ulBase + ADC_O_SPC) = ulPhase;
  1333. }
  1334. //*****************************************************************************
  1335. //
  1336. //! Gets the phase delay between a trigger and the start of a sequence.
  1337. //!
  1338. //! \param ulBase is the base address of the ADC module.
  1339. //!
  1340. //! This function gets the current phase delay between the detection of an ADC
  1341. //! trigger event and the start of the sample sequence.
  1342. //!
  1343. //! \return Returns the phase delay, specified as one of \b ADC_PHASE_0,
  1344. //! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
  1345. //! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
  1346. //! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
  1347. //! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
  1348. //
  1349. //*****************************************************************************
  1350. unsigned long
  1351. ADCPhaseDelayGet(unsigned long ulBase)
  1352. {
  1353. //
  1354. // Check the arguments.
  1355. //
  1356. ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
  1357. //
  1358. // Return the phase delay.
  1359. //
  1360. return(HWREG(ulBase + ADC_O_SPC));
  1361. }
  1362. //*****************************************************************************
  1363. //
  1364. // Close the Doxygen group.
  1365. //! @}
  1366. //
  1367. //*****************************************************************************