ethernet.c 44 KB

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  1. //*****************************************************************************
  2. //
  3. // ethernet.c - Driver for the Integrated Ethernet Controller
  4. //
  5. // Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Texas Instruments (TI) is supplying this software for use solely and
  9. // exclusively on TI's microcontroller products. The software is owned by
  10. // TI and/or its suppliers, and is protected under applicable copyright
  11. // laws. You may not combine this software with "viral" open-source
  12. // software in order to form a larger program.
  13. //
  14. // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
  15. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
  16. // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  17. // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
  18. // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  19. // DAMAGES, FOR ANY REASON WHATSOEVER.
  20. //
  21. // This is part of revision 6459 of the Stellaris Peripheral Driver Library.
  22. //
  23. //*****************************************************************************
  24. //*****************************************************************************
  25. //
  26. //! \addtogroup ethernet_api
  27. //! @{
  28. //
  29. //*****************************************************************************
  30. #include "inc/hw_ethernet.h"
  31. #include "inc/hw_ints.h"
  32. #include "inc/hw_memmap.h"
  33. #include "inc/hw_types.h"
  34. #include "driverlib/debug.h"
  35. #include "driverlib/ethernet.h"
  36. #include "driverlib/interrupt.h"
  37. //*****************************************************************************
  38. //
  39. //! Initializes the Ethernet controller for operation.
  40. //!
  41. //! \param ulBase is the base address of the controller.
  42. //! \param ulEthClk is the rate of the clock supplied to the Ethernet module.
  43. //!
  44. //! This function will prepare the Ethernet controller for first time use in
  45. //! a given hardware/software configuration. This function should be called
  46. //! before any other Ethernet API functions are called.
  47. //!
  48. //! The peripheral clock will be the same as the processor clock. This will be
  49. //! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
  50. //! if it is constant and known (to save the code/execution overhead of a call
  51. //! to SysCtlClockGet()).
  52. //!
  53. //! This function replaces the original EthernetInit() API and performs the
  54. //! same actions. A macro is provided in <tt>ethernet.h</tt> to map the
  55. //! original API to this API.
  56. //!
  57. //! \note If the device configuration is changed (for example, the system clock
  58. //! is reprogrammed to a different speed), then the Ethernet controller must be
  59. //! disabled by calling the EthernetDisable() function and the controller must
  60. //! be reinitialized by calling the EthernetInitExpClk() function again. After
  61. //! the controller has been reinitialized, the controller should be
  62. //! reconfigured using the appropriate Ethernet API calls.
  63. //!
  64. //! \return None.
  65. //
  66. //*****************************************************************************
  67. void
  68. EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk)
  69. {
  70. unsigned long ulDiv;
  71. //
  72. // Check the arguments.
  73. //
  74. ASSERT(ulBase == ETH_BASE);
  75. //
  76. // Set the Management Clock Divider register for access to the PHY
  77. // register set (via EthernetPHYRead/Write).
  78. //
  79. // The MDC clock divided down from the system clock using the following
  80. // formula. A maximum of 2.5MHz is allowed for F(mdc).
  81. //
  82. // F(mdc) = F(sys) / (2 * (div + 1))
  83. // div = (F(sys) / (2 * F(mdc))) - 1
  84. // div = (F(sys) / 2 / F(mdc)) - 1
  85. //
  86. // Note: Because we should round up, to ensure we don't violate the
  87. // maximum clock speed, we can simplify this as follows:
  88. //
  89. // div = F(sys) / 2 / F(mdc)
  90. //
  91. // For example, given a system clock of 6.0MHz, and a div value of 1,
  92. // the mdc clock would be programmed as 1.5 MHz.
  93. //
  94. ulDiv = (ulEthClk / 2) / 2500000;
  95. HWREG(ulBase + MAC_O_MDV) = (ulDiv & MAC_MDV_DIV_M);
  96. }
  97. //*****************************************************************************
  98. //
  99. //! Sets the configuration of the Ethernet controller.
  100. //!
  101. //! \param ulBase is the base address of the controller.
  102. //! \param ulConfig is the configuration for the controller.
  103. //!
  104. //! After the EthernetInitExpClk() function has been called, this API function
  105. //! can be used to configure the various features of the Ethernet controller.
  106. //!
  107. //! The Ethernet controller provides three control registers that are used
  108. //! to configure the controller's operation. The transmit control register
  109. //! provides settings to enable full duplex operation, to auto-generate the
  110. //! frame check sequence, and to pad the transmit packets to the minimum
  111. //! length as required by the IEEE standard. The receive control register
  112. //! provides settings to enable reception of packets with bad frame check
  113. //! sequence values and to enable multi-cast or promiscuous modes. The
  114. //! timestamp control register provides settings that enable support logic in
  115. //! the controller that allow the use of the General Purpose Timer 3 to capture
  116. //! timestamps for the transmitted and received packets.
  117. //!
  118. //! The \e ulConfig parameter is the logical OR of the following values:
  119. //!
  120. //! - \b ETH_CFG_TS_TSEN - Enable TX and RX interrupt status as CCP timer
  121. //! inputs
  122. //! - \b ETH_CFG_RX_BADCRCDIS - Disable reception of packets with a bad CRC
  123. //! - \b ETH_CFG_RX_PRMSEN - Enable promiscuous mode reception (all packets)
  124. //! - \b ETH_CFG_RX_AMULEN - Enable reception of multicast packets
  125. //! - \b ETH_CFG_TX_DPLXEN - Enable full duplex transmit mode
  126. //! - \b ETH_CFG_TX_CRCEN - Enable transmit with auto CRC generation
  127. //! - \b ETH_CFG_TX_PADEN - Enable padding of transmit data to minimum size
  128. //!
  129. //! These bit-mapped values are programmed into the transmit, receive, and/or
  130. //! timestamp control register.
  131. //!
  132. //! \return None.
  133. //
  134. //*****************************************************************************
  135. void
  136. EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig)
  137. {
  138. unsigned long ulTemp;
  139. //
  140. // Check the arguments.
  141. //
  142. ASSERT(ulBase == ETH_BASE);
  143. ASSERT((ulConfig & ~(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
  144. ETH_CFG_TX_PADEN | ETH_CFG_RX_BADCRCDIS |
  145. ETH_CFG_RX_PRMSEN | ETH_CFG_RX_AMULEN |
  146. ETH_CFG_TS_TSEN)) == 0);
  147. //
  148. // Setup the Transmit Control Register.
  149. //
  150. ulTemp = HWREG(ulBase + MAC_O_TCTL);
  151. ulTemp &= ~(MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN);
  152. ulTemp |= ulConfig & 0x0FF;
  153. HWREG(ulBase + MAC_O_TCTL) = ulTemp;
  154. //
  155. // Setup the Receive Control Register.
  156. //
  157. ulTemp = HWREG(ulBase + MAC_O_RCTL);
  158. ulTemp &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL);
  159. ulTemp |= (ulConfig >> 8) & 0x0FF;
  160. HWREG(ulBase + MAC_O_RCTL) = ulTemp;
  161. //
  162. // Setup the Time Stamp Configuration register.
  163. //
  164. ulTemp = HWREG(ulBase + MAC_O_TS);
  165. ulTemp &= ~(MAC_TS_TSEN);
  166. ulTemp |= (ulConfig >> 16) & 0x0FF;
  167. HWREG(ulBase + MAC_O_TS) = ulTemp;
  168. }
  169. //*****************************************************************************
  170. //
  171. //! Gets the current configuration of the Ethernet controller.
  172. //!
  173. //! \param ulBase is the base address of the controller.
  174. //!
  175. //! This function will query the control registers of the Ethernet controller
  176. //! and return a bit-mapped configuration value.
  177. //!
  178. //! \sa The description of the EthernetConfigSet() function provides detailed
  179. //! information for the bit-mapped configuration values that will be returned.
  180. //!
  181. //! \return Returns the bit-mapped Ethernet controller configuration value.
  182. //
  183. //*****************************************************************************
  184. unsigned long
  185. EthernetConfigGet(unsigned long ulBase)
  186. {
  187. unsigned long ulConfig;
  188. //
  189. // Check the arguments.
  190. //
  191. ASSERT(ulBase == ETH_BASE);
  192. //
  193. // Read and return the Ethernet controller configuration parameters,
  194. // properly shifted into the appropriate bit field positions.
  195. //
  196. ulConfig = HWREG(ulBase + MAC_O_TS) << 16;
  197. ulConfig |= (HWREG(ulBase + MAC_O_RCTL) & ~(MAC_RCTL_RXEN)) << 8;
  198. ulConfig |= HWREG(ulBase + MAC_O_TCTL) & ~(MAC_TCTL_TXEN);
  199. return(ulConfig);
  200. }
  201. //*****************************************************************************
  202. //
  203. //! Sets the MAC address of the Ethernet controller.
  204. //!
  205. //! \param ulBase is the base address of the controller.
  206. //! \param pucMACAddr is the pointer to the array of MAC-48 address octets.
  207. //!
  208. //! This function will program the IEEE-defined MAC-48 address specified in
  209. //! \e pucMACAddr into the Ethernet controller. This address is used by the
  210. //! Ethernet controller for hardware-level filtering of incoming Ethernet
  211. //! packets (when promiscuous mode is not enabled).
  212. //!
  213. //! The MAC-48 address is defined as 6 octets, illustrated by the following
  214. //! example address. The numbers are shown in hexadecimal format.
  215. //!
  216. //! AC-DE-48-00-00-80
  217. //!
  218. //! In this representation, the first three octets (AC-DE-48) are the
  219. //! Organizationally Unique Identifier (OUI). This is a number assigned by
  220. //! the IEEE to an organization that requests a block of MAC addresses. The
  221. //! last three octets (00-00-80) are a 24-bit number managed by the OUI owner
  222. //! to uniquely identify a piece of hardware within that organization that is
  223. //! to be connected to the Ethernet.
  224. //!
  225. //! In this representation, the octets are transmitted from left to right,
  226. //! with the ``AC'' octet being transmitted first and the ``80'' octet being
  227. //! transmitted last. Within an octet, the bits are transmitted LSB to MSB.
  228. //! For this address, the first bit to be transmitted would be ``0'', the LSB
  229. //! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of
  230. //! ``80''.
  231. //!
  232. //! \return None.
  233. //
  234. //*****************************************************************************
  235. void
  236. EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr)
  237. {
  238. unsigned long ulTemp;
  239. unsigned char *pucTemp = (unsigned char *)&ulTemp;
  240. //
  241. // Check the arguments.
  242. //
  243. ASSERT(ulBase == ETH_BASE);
  244. ASSERT(pucMACAddr != 0);
  245. //
  246. // Program the MAC Address into the device. The first four bytes of the
  247. // MAC Address are placed into the IA0 register. The remaining two bytes
  248. // of the MAC address are placed into the IA1 register.
  249. //
  250. pucTemp[0] = pucMACAddr[0];
  251. pucTemp[1] = pucMACAddr[1];
  252. pucTemp[2] = pucMACAddr[2];
  253. pucTemp[3] = pucMACAddr[3];
  254. HWREG(ulBase + MAC_O_IA0) = ulTemp;
  255. ulTemp = 0;
  256. pucTemp[0] = pucMACAddr[4];
  257. pucTemp[1] = pucMACAddr[5];
  258. HWREG(ulBase + MAC_O_IA1) = ulTemp;
  259. }
  260. //*****************************************************************************
  261. //
  262. //! Gets the MAC address of the Ethernet controller.
  263. //!
  264. //! \param ulBase is the base address of the controller.
  265. //! \param pucMACAddr is the pointer to the location in which to store the
  266. //! array of MAC-48 address octets.
  267. //!
  268. //! This function will read the currently programmed MAC address into the
  269. //! \e pucMACAddr buffer.
  270. //!
  271. //! \sa Refer to EthernetMACAddrSet() API description for more details about
  272. //! the MAC address format.
  273. //!
  274. //! \return None.
  275. //
  276. //*****************************************************************************
  277. void
  278. EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr)
  279. {
  280. unsigned long ulTemp;
  281. unsigned char *pucTemp = (unsigned char *)&ulTemp;
  282. //
  283. // Check the arguments.
  284. //
  285. ASSERT(ulBase == ETH_BASE);
  286. ASSERT(pucMACAddr != 0);
  287. //
  288. // Read the MAC address from the device. The first four bytes of the
  289. // MAC address are read from the IA0 register. The remaining two bytes
  290. // of the MAC addres
  291. //
  292. ulTemp = HWREG(ulBase + MAC_O_IA0);
  293. pucMACAddr[0] = pucTemp[0];
  294. pucMACAddr[1] = pucTemp[1];
  295. pucMACAddr[2] = pucTemp[2];
  296. pucMACAddr[3] = pucTemp[3];
  297. ulTemp = HWREG(ulBase + MAC_O_IA1);
  298. pucMACAddr[4] = pucTemp[0];
  299. pucMACAddr[5] = pucTemp[1];
  300. }
  301. //*****************************************************************************
  302. //
  303. //! Enables the Ethernet controller for normal operation.
  304. //!
  305. //! \param ulBase is the base address of the controller.
  306. //!
  307. //! Once the Ethernet controller has been configured using the
  308. //! EthernetConfigSet() function and the MAC address has been programmed using
  309. //! the EthernetMACAddrSet() function, this API function can be called to
  310. //! enable the controller for normal operation.
  311. //!
  312. //! This function will enable the controller's transmitter and receiver, and
  313. //! will reset the receive FIFO.
  314. //!
  315. //! \return None.
  316. //
  317. //*****************************************************************************
  318. void
  319. EthernetEnable(unsigned long ulBase)
  320. {
  321. //
  322. // Check the arguments.
  323. //
  324. ASSERT(ulBase == ETH_BASE);
  325. //
  326. // Reset the receive FIFO.
  327. //
  328. HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
  329. //
  330. // Enable the Ethernet receiver.
  331. //
  332. HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RXEN;
  333. //
  334. // Enable Ethernet transmitter.
  335. //
  336. HWREG(ulBase + MAC_O_TCTL) |= MAC_TCTL_TXEN;
  337. //
  338. // Reset the receive FIFO again, after the receiver has been enabled.
  339. //
  340. HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
  341. }
  342. //*****************************************************************************
  343. //
  344. //! Disables the Ethernet controller.
  345. //!
  346. //! \param ulBase is the base address of the controller.
  347. //!
  348. //! When terminating operations on the Ethernet interface, this function should
  349. //! be called. This function will disable the transmitter and receiver, and
  350. //! will clear out the receive FIFO.
  351. //!
  352. //! \return None.
  353. //
  354. //*****************************************************************************
  355. void
  356. EthernetDisable(unsigned long ulBase)
  357. {
  358. //
  359. // Check the arguments.
  360. //
  361. ASSERT(ulBase == ETH_BASE);
  362. //
  363. // Reset the receive FIFO.
  364. //
  365. HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
  366. //
  367. // Disable the Ethernet transmitter.
  368. //
  369. HWREG(ulBase + MAC_O_TCTL) &= ~(MAC_TCTL_TXEN);
  370. //
  371. // Disable the Ethernet receiver.
  372. //
  373. HWREG(ulBase + MAC_O_RCTL) &= ~(MAC_RCTL_RXEN);
  374. //
  375. // Reset the receive FIFO again, after the receiver has been disabled.
  376. //
  377. HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
  378. }
  379. //*****************************************************************************
  380. //
  381. //! Check for packet available from the Ethernet controller.
  382. //!
  383. //! \param ulBase is the base address of the controller.
  384. //!
  385. //! The Ethernet controller provides a register that contains the number of
  386. //! packets available in the receive FIFO. When the last bytes of a packet are
  387. //! successfully received (that is, the frame check sequence bytes), the packet
  388. //! count is incremented. Once the packet has been fully read (including the
  389. //! frame check sequence bytes) from the FIFO, the packet count will be
  390. //! decremented.
  391. //!
  392. //! \return Returns \b true if there are one or more packets available in the
  393. //! receive FIFO, including the current packet being read, and \b false
  394. //! otherwise.
  395. //
  396. //*****************************************************************************
  397. tBoolean
  398. EthernetPacketAvail(unsigned long ulBase)
  399. {
  400. //
  401. // Check the arguments.
  402. //
  403. ASSERT(ulBase == ETH_BASE);
  404. //
  405. // Return the availability of packets.
  406. //
  407. return((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) ? true : false);
  408. }
  409. //*****************************************************************************
  410. //
  411. //! Checks for packet space available in the Ethernet controller.
  412. //!
  413. //! \param ulBase is the base address of the controller.
  414. //!
  415. //! The Ethernet controller's transmit FIFO is designed to support a single
  416. //! packet at a time. After the packet has been written into the FIFO, the
  417. //! transmit request bit must be set to enable the transmission of the packet.
  418. //! Only after the packet has been transmitted can a new packet be written
  419. //! into the FIFO. This function will simply check to see if a packet is
  420. //! in progress. If so, there is no space available in the transmit FIFO.
  421. //!
  422. //! \return Returns \b true if a space is available in the transmit FIFO, and
  423. //! \b false otherwise.
  424. //
  425. //*****************************************************************************
  426. tBoolean
  427. EthernetSpaceAvail(unsigned long ulBase)
  428. {
  429. //
  430. // Check the arguments.
  431. //
  432. ASSERT(ulBase == ETH_BASE);
  433. //
  434. // Return the availability of space.
  435. //
  436. return((HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) ? false : true);
  437. }
  438. //*****************************************************************************
  439. //
  440. //! \internal
  441. //!
  442. //! Internal function for reading a packet from the Ethernet controller.
  443. //!
  444. //! \param ulBase is the base address of the controller.
  445. //! \param pucBuf is the pointer to the packet buffer.
  446. //! \param lBufLen is the maximum number of bytes to be read into the buffer.
  447. //!
  448. //! Based on the following table of how the receive frame is stored in the
  449. //! receive FIFO, this function will extract a packet from the FIFO and store
  450. //! it in the packet buffer that was passed in.
  451. //!
  452. //! Format of the data in the RX FIFO is as follows:
  453. //!
  454. //! \verbatim
  455. //! +---------+----------+----------+----------+----------+
  456. //! | | 31:24 | 23:16 | 15:8 | 7:0 |
  457. //! +---------+----------+----------+----------+----------+
  458. //! | Word 0 | DA 2 | DA 1 | FL MSB | FL LSB |
  459. //! +---------+----------+----------+----------+----------+
  460. //! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
  461. //! +---------+----------+----------+----------+----------+
  462. //! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
  463. //! +---------+----------+----------+----------+----------+
  464. //! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
  465. //! +---------+----------+----------+----------+----------+
  466. //! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
  467. //! +---------+----------+----------+----------+----------+
  468. //! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
  469. //! +---------+----------+----------+----------+----------+
  470. //! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
  471. //! +---------+----------+----------+----------+----------+
  472. //! | ... | | | | |
  473. //! +---------+----------+----------+----------+----------+
  474. //! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
  475. //! +---------+----------+----------+----------+----------+
  476. //! | Word Y | FCS 4 | FCS 3 | FCS 2 | FCS 1 |
  477. //! +---------+----------+----------+----------+----------+
  478. //! \endverbatim
  479. //!
  480. //! Where FL is Frame Length, (FL + DA + SA + FT + DATA + FCS) Bytes.
  481. //! Where DA is Destination (MAC) Address.
  482. //! Where SA is Source (MAC) Address.
  483. //! Where FT is Frame Type (or Frame Length for Ethernet).
  484. //! Where DATA is Payload Data for the Ethernet Frame.
  485. //! Where FCS is the Frame Check Sequence.
  486. //!
  487. //! \return Returns the negated packet length \b -n if the packet is too large
  488. //! for \e pucBuf, and returns the packet length \b n otherwise.
  489. //
  490. //*****************************************************************************
  491. static long
  492. EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf,
  493. long lBufLen)
  494. {
  495. unsigned long ulTemp;
  496. long lFrameLen, lTempLen;
  497. long i = 0;
  498. //
  499. // Read WORD 0 (see format above) from the FIFO, set the receive
  500. // Frame Length and store the first two bytes of the destination
  501. // address in the receive buffer.
  502. //
  503. ulTemp = HWREG(ulBase + MAC_O_DATA);
  504. lFrameLen = (long)(ulTemp & 0xFFFF);
  505. pucBuf[i++] = (unsigned char) ((ulTemp >> 16) & 0xff);
  506. pucBuf[i++] = (unsigned char) ((ulTemp >> 24) & 0xff);
  507. //
  508. // Read all but the last WORD into the receive buffer.
  509. //
  510. lTempLen = (lBufLen < (lFrameLen - 6)) ? lBufLen : (lFrameLen - 6);
  511. while(i <= (lTempLen - 4))
  512. {
  513. *(unsigned long *)&pucBuf[i] = HWREG(ulBase + MAC_O_DATA);
  514. i += 4;
  515. }
  516. //
  517. // Read the last 1, 2, or 3 BYTES into the buffer
  518. //
  519. if(i < lTempLen)
  520. {
  521. ulTemp = HWREG(ulBase + MAC_O_DATA);
  522. if(i == lTempLen - 3)
  523. {
  524. pucBuf[i++] = ((ulTemp >> 0) & 0xff);
  525. pucBuf[i++] = ((ulTemp >> 8) & 0xff);
  526. pucBuf[i++] = ((ulTemp >> 16) & 0xff);
  527. i += 1;
  528. }
  529. else if(i == lTempLen - 2)
  530. {
  531. pucBuf[i++] = ((ulTemp >> 0) & 0xff);
  532. pucBuf[i++] = ((ulTemp >> 8) & 0xff);
  533. i += 2;
  534. }
  535. else if(i == lTempLen - 1)
  536. {
  537. pucBuf[i++] = ((ulTemp >> 0) & 0xff);
  538. i += 3;
  539. }
  540. }
  541. //
  542. // Read any remaining WORDS (that did not fit into the buffer).
  543. //
  544. while(i < (lFrameLen - 2))
  545. {
  546. ulTemp = HWREG(ulBase + MAC_O_DATA);
  547. i += 4;
  548. }
  549. //
  550. // If frame was larger than the buffer, return the "negative" frame length
  551. //
  552. lFrameLen -= 6;
  553. if(lFrameLen > lBufLen)
  554. {
  555. return(-lFrameLen);
  556. }
  557. //
  558. // Return the Frame Length
  559. //
  560. return(lFrameLen);
  561. }
  562. //*****************************************************************************
  563. //
  564. //! Receives a packet from the Ethernet controller.
  565. //!
  566. //! \param ulBase is the base address of the controller.
  567. //! \param pucBuf is the pointer to the packet buffer.
  568. //! \param lBufLen is the maximum number of bytes to be read into the buffer.
  569. //!
  570. //! This function reads a packet from the receive FIFO of the controller and
  571. //! places it into \e pucBuf. If no packet is available the function will
  572. //! return immediately. Otherwise, the function will read the entire packet
  573. //! from the receive FIFO. If there are more bytes in the packet than will fit
  574. //! into \e pucBuf (as specified by \e lBufLen), the function will return the
  575. //! negated length of the packet and the buffer will contain \e lBufLen bytes
  576. //! of the packet. Otherwise, the function will return the length of the
  577. //! packet that was read and \e pucBuf will contain the entire packet
  578. //! (excluding the frame check sequence bytes).
  579. //!
  580. //! This function replaces the original EthernetPacketNonBlockingGet() API and
  581. //! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
  582. //! map the original API to this API.
  583. //!
  584. //! \note This function will return immediately if no packet is available.
  585. //!
  586. //! \return Returns \b 0 if no packet is available, the negated packet length
  587. //! \b -n if the packet is too large for \e pucBuf, and the packet length \b n
  588. //! otherwise.
  589. //
  590. //*****************************************************************************
  591. long
  592. EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
  593. long lBufLen)
  594. {
  595. //
  596. // Check the arguments.
  597. //
  598. ASSERT(ulBase == ETH_BASE);
  599. ASSERT(pucBuf != 0);
  600. ASSERT(lBufLen > 0);
  601. //
  602. // Check to see if any packets are available.
  603. //
  604. if((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
  605. {
  606. return(0);
  607. }
  608. //
  609. // Read the packet, and return.
  610. //
  611. return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
  612. }
  613. //*****************************************************************************
  614. //
  615. //! Waits for a packet from the Ethernet controller.
  616. //!
  617. //! \param ulBase is the base address of the controller.
  618. //! \param pucBuf is the pointer to the packet buffer.
  619. //! \param lBufLen is the maximum number of bytes to be read into the buffer.
  620. //!
  621. //! This function reads a packet from the receive FIFO of the controller and
  622. //! places it into \e pucBuf. The function will wait until a packet is
  623. //! available in the FIFO. Then the function will read the entire packet
  624. //! from the receive FIFO. If there are more bytes in the packet than will
  625. //! fit into \e pucBuf (as specified by \e lBufLen), the function will return
  626. //! the negated length of the packet and the buffer will contain \e lBufLen
  627. //! bytes of the packet. Otherwise, the function will return the length of
  628. //! the packet that was read and \e pucBuf will contain the entire packet
  629. //! (excluding the frame check sequence bytes).
  630. //!
  631. //! \note This function is blocking and will not return until a packet arrives.
  632. //!
  633. //! \return Returns the negated packet length \b -n if the packet is too large
  634. //! for \e pucBuf, and returns the packet length \b n otherwise.
  635. //
  636. //*****************************************************************************
  637. long
  638. EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
  639. long lBufLen)
  640. {
  641. //
  642. // Check the arguments.
  643. //
  644. ASSERT(ulBase == ETH_BASE);
  645. ASSERT(pucBuf != 0);
  646. ASSERT(lBufLen > 0);
  647. //
  648. // Wait for a packet to become available
  649. //
  650. while((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
  651. {
  652. }
  653. //
  654. // Read the packet
  655. //
  656. return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
  657. }
  658. //*****************************************************************************
  659. //
  660. //! \internal
  661. //!
  662. //! Internal function for sending a packet to the Ethernet controller.
  663. //!
  664. //! \param ulBase is the base address of the controller.
  665. //! \param pucBuf is the pointer to the packet buffer.
  666. //! \param lBufLen is number of bytes in the packet to be transmitted.
  667. //!
  668. //! Puts a packet into the transmit FIFO of the controller.
  669. //!
  670. //! Format of the data in the TX FIFO is as follows:
  671. //!
  672. //! \verbatim
  673. //! +---------+----------+----------+----------+----------+
  674. //! | | 31:24 | 23:16 | 15:8 | 7:0 |
  675. //! +---------+----------+----------+----------+----------+
  676. //! | Word 0 | DA 2 | DA 1 | PL MSB | PL LSB |
  677. //! +---------+----------+----------+----------+----------+
  678. //! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
  679. //! +---------+----------+----------+----------+----------+
  680. //! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
  681. //! +---------+----------+----------+----------+----------+
  682. //! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
  683. //! +---------+----------+----------+----------+----------+
  684. //! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
  685. //! +---------+----------+----------+----------+----------+
  686. //! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
  687. //! +---------+----------+----------+----------+----------+
  688. //! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
  689. //! +---------+----------+----------+----------+----------+
  690. //! | ... | | | | |
  691. //! +---------+----------+----------+----------+----------+
  692. //! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
  693. //! +---------+----------+----------+----------+----------+
  694. //! \endverbatim
  695. //!
  696. //! Where PL is Payload Length, (DATA) only
  697. //! Where DA is Destination (MAC) Address
  698. //! Where SA is Source (MAC) Address
  699. //! Where FT is Frame Type (or Frame Length for Ethernet)
  700. //! Where DATA is Payload Data for the Ethernet Frame
  701. //!
  702. //! \return Returns the negated packet length \b -lBufLen if the packet is too
  703. //! large for FIFO, and the packet length \b lBufLen otherwise.
  704. //
  705. //*****************************************************************************
  706. static long
  707. EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf,
  708. long lBufLen)
  709. {
  710. unsigned long ulTemp;
  711. long i = 0;
  712. //
  713. // If the packet is too large, return the negative packet length as
  714. // an error code.
  715. //
  716. if(lBufLen > (2048 - 2))
  717. {
  718. return(-lBufLen);
  719. }
  720. //
  721. // Build and write WORD 0 (see format above) to the transmit FIFO.
  722. //
  723. ulTemp = (unsigned long)(lBufLen - 14);
  724. ulTemp |= (pucBuf[i++] << 16);
  725. ulTemp |= (pucBuf[i++] << 24);
  726. HWREG(ulBase + MAC_O_DATA) = ulTemp;
  727. //
  728. // Write each subsequent WORD n to the transmit FIFO, except for the last
  729. // WORD (if the word does not contain 4 bytes).
  730. //
  731. while(i <= (lBufLen - 4))
  732. {
  733. HWREG(ulBase + MAC_O_DATA) = *(unsigned long *)&pucBuf[i];
  734. i += 4;
  735. }
  736. //
  737. // Build the last word of the remaining 1, 2, or 3 bytes, and store
  738. // the WORD into the transmit FIFO.
  739. //
  740. if(i != lBufLen)
  741. {
  742. if(i == (lBufLen - 3))
  743. {
  744. ulTemp = (pucBuf[i++] << 0);
  745. ulTemp |= (pucBuf[i++] << 8);
  746. ulTemp |= (pucBuf[i++] << 16);
  747. HWREG(ulBase + MAC_O_DATA) = ulTemp;
  748. }
  749. else if(i == (lBufLen - 2))
  750. {
  751. ulTemp = (pucBuf[i++] << 0);
  752. ulTemp |= (pucBuf[i++] << 8);
  753. HWREG(ulBase + MAC_O_DATA) = ulTemp;
  754. }
  755. else if(i == (lBufLen - 1))
  756. {
  757. ulTemp = (pucBuf[i++] << 0);
  758. HWREG(ulBase + MAC_O_DATA) = ulTemp;
  759. }
  760. }
  761. //
  762. // Activate the transmitter
  763. //
  764. HWREG(ulBase + MAC_O_TR) = MAC_TR_NEWTX;
  765. //
  766. // Return the Buffer Length transmitted.
  767. //
  768. return(lBufLen);
  769. }
  770. //*****************************************************************************
  771. //
  772. //! Sends a packet to the Ethernet controller.
  773. //!
  774. //! \param ulBase is the base address of the controller.
  775. //! \param pucBuf is the pointer to the packet buffer.
  776. //! \param lBufLen is number of bytes in the packet to be transmitted.
  777. //!
  778. //! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
  779. //! into the transmit FIFO of the controller and then activates the
  780. //! transmitter for this packet. If no space is available in the FIFO, the
  781. //! function will return immediately. If space is available, the
  782. //! function will return once \e lBufLen bytes of the packet have been placed
  783. //! into the FIFO and the transmitter has been started. The function will not
  784. //! wait for the transmission to complete. The function will return the
  785. //! negated \e lBufLen if the length is larger than the space available in
  786. //! the transmit FIFO.
  787. //!
  788. //! This function replaces the original EthernetPacketNonBlockingPut() API and
  789. //! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
  790. //! map the original API to this API.
  791. //!
  792. //! \note This function does not block and will return immediately if no space
  793. //! is available for the transmit packet.
  794. //!
  795. //! \return Returns \b 0 if no space is available in the transmit FIFO, the
  796. //! negated packet length \b -lBufLen if the packet is too large for FIFO, and
  797. //! the packet length \b lBufLen otherwise.
  798. //
  799. //*****************************************************************************
  800. long
  801. EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
  802. long lBufLen)
  803. {
  804. //
  805. // Check the arguments.
  806. //
  807. ASSERT(ulBase == ETH_BASE);
  808. ASSERT(pucBuf != 0);
  809. ASSERT(lBufLen > 0);
  810. //
  811. // Check if the transmit FIFO is in use and return the appropriate code.
  812. //
  813. if(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
  814. {
  815. return(0);
  816. }
  817. //
  818. // Send the packet and return.
  819. //
  820. return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
  821. }
  822. //*****************************************************************************
  823. //
  824. //! Waits to send a packet from the Ethernet controller.
  825. //!
  826. //! \param ulBase is the base address of the controller.
  827. //! \param pucBuf is the pointer to the packet buffer.
  828. //! \param lBufLen is number of bytes in the packet to be transmitted.
  829. //!
  830. //! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
  831. //! into the transmit FIFO of the controller and then activates the transmitter
  832. //! for this packet. This function will wait until the transmit FIFO is empty.
  833. //! Once space is available, the function will return once \e lBufLen bytes of
  834. //! the packet have been placed into the FIFO and the transmitter has been
  835. //! started. The function will not wait for the transmission to complete. The
  836. //! function will return the negated \e lBufLen if the length is larger than
  837. //! the space available in the transmit FIFO.
  838. //!
  839. //! \note This function blocks and will wait until space is available for the
  840. //! transmit packet before returning.
  841. //!
  842. //! \return Returns the negated packet length \b -lBufLen if the packet is too
  843. //! large for FIFO, and the packet length \b lBufLen otherwise.
  844. //
  845. //*****************************************************************************
  846. long
  847. EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
  848. long lBufLen)
  849. {
  850. //
  851. // Check the arguments.
  852. //
  853. ASSERT(ulBase == ETH_BASE);
  854. ASSERT(pucBuf != 0);
  855. ASSERT(lBufLen > 0);
  856. //
  857. // Wait for current packet (if any) to complete.
  858. //
  859. while(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
  860. {
  861. }
  862. //
  863. // Send the packet and return.
  864. //
  865. return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
  866. }
  867. //*****************************************************************************
  868. //
  869. //! Registers an interrupt handler for an Ethernet interrupt.
  870. //!
  871. //! \param ulBase is the base address of the controller.
  872. //! \param pfnHandler is a pointer to the function to be called when the
  873. //! enabled Ethernet interrupts occur.
  874. //!
  875. //! This function sets the handler to be called when the Ethernet interrupt
  876. //! occurs. This will enable the global interrupt in the interrupt controller;
  877. //! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It
  878. //! is the interrupt handler's responsibility to clear the interrupt source.
  879. //!
  880. //! \sa IntRegister() for important information about registering interrupt
  881. //! handlers.
  882. //!
  883. //! \return None.
  884. //
  885. //*****************************************************************************
  886. void
  887. EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
  888. {
  889. //
  890. // Check the arguments.
  891. //
  892. ASSERT(ulBase == ETH_BASE);
  893. ASSERT(pfnHandler != 0);
  894. //
  895. // Register the interrupt handler.
  896. //
  897. IntRegister(INT_ETH, pfnHandler);
  898. //
  899. // Enable the Ethernet interrupt.
  900. //
  901. IntEnable(INT_ETH);
  902. }
  903. //*****************************************************************************
  904. //
  905. //! Unregisters an interrupt handler for an Ethernet interrupt.
  906. //!
  907. //! \param ulBase is the base address of the controller.
  908. //!
  909. //! This function unregisters the interrupt handler. This will disable the
  910. //! global interrupt in the interrupt controller so that the interrupt handler
  911. //! no longer is called.
  912. //!
  913. //! \sa IntRegister() for important information about registering interrupt
  914. //! handlers.
  915. //!
  916. //! \return None.
  917. //
  918. //*****************************************************************************
  919. void
  920. EthernetIntUnregister(unsigned long ulBase)
  921. {
  922. //
  923. // Check the arguments.
  924. //
  925. ASSERT(ulBase == ETH_BASE);
  926. //
  927. // Disable the interrupt.
  928. //
  929. IntDisable(INT_ETH);
  930. //
  931. // Unregister the interrupt handler.
  932. //
  933. IntUnregister(INT_ETH);
  934. }
  935. //*****************************************************************************
  936. //
  937. //! Enables individual Ethernet interrupt sources.
  938. //!
  939. //! \param ulBase is the base address of the controller.
  940. //! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
  941. //!
  942. //! Enables the indicated Ethernet interrupt sources. Only the sources that
  943. //! are enabled can be reflected to the processor interrupt; disabled sources
  944. //! have no effect on the processor.
  945. //!
  946. //! The \e ulIntFlags parameter is the logical OR of any of the following:
  947. //!
  948. //! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated
  949. //! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17,
  950. //! must be read to determine which PHY interrupt has occurred. This register
  951. //! can be read using the EthernetPHYRead() API function.
  952. //! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the
  953. //! management interface has completed successfully.
  954. //! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred
  955. //! during reception of a frame. This error can indicate a length mismatch, a
  956. //! CRC failure, or an error indication from the PHY.
  957. //! - \b ETH_INT_RXOF - This interrupt indicates that a frame has been received
  958. //! that exceeds the available space in the RX FIFO.
  959. //! - \b ETH_INT_TX - This interrupt indicates that the packet stored in the TX
  960. //! FIFO has been successfully transmitted.
  961. //! - \b ETH_INT_TXER - This interrupt indicates that an error has occurred
  962. //! during the transmission of a packet. This error can be either a retry
  963. //! failure during the back-off process, or an invalid length stored in the TX
  964. //! FIFO.
  965. //! - \b ETH_INT_RX - This interrupt indicates that one (or more) packets are
  966. //! available in the RX FIFO for processing.
  967. //!
  968. //! \return None.
  969. //
  970. //*****************************************************************************
  971. void
  972. EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
  973. {
  974. //
  975. // Check the arguments.
  976. //
  977. ASSERT(ulBase == ETH_BASE);
  978. ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
  979. ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
  980. ETH_INT_RX)));
  981. //
  982. // Enable the specified interrupts.
  983. //
  984. HWREG(ulBase + MAC_O_IM) |= ulIntFlags;
  985. }
  986. //*****************************************************************************
  987. //
  988. //! Disables individual Ethernet interrupt sources.
  989. //!
  990. //! \param ulBase is the base address of the controller.
  991. //! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
  992. //!
  993. //! Disables the indicated Ethernet interrupt sources. Only the sources that
  994. //! are enabled can be reflected to the processor interrupt; disabled sources
  995. //! have no effect on the processor.
  996. //!
  997. //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
  998. //! parameter to EthernetIntEnable().
  999. //!
  1000. //! \return None.
  1001. //
  1002. //*****************************************************************************
  1003. void
  1004. EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
  1005. {
  1006. //
  1007. // Check the arguments.
  1008. //
  1009. ASSERT(ulBase == ETH_BASE);
  1010. ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
  1011. ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
  1012. ETH_INT_RX)));
  1013. //
  1014. // Disable the specified interrupts.
  1015. //
  1016. HWREG(ulBase + MAC_O_IM) &= ~ulIntFlags;
  1017. }
  1018. //*****************************************************************************
  1019. //
  1020. //! Gets the current Ethernet interrupt status.
  1021. //!
  1022. //! \param ulBase is the base address of the controller.
  1023. //! \param bMasked is false if the raw interrupt status is required and true
  1024. //! if the masked interrupt status is required.
  1025. //!
  1026. //! This returns the interrupt status for the Ethernet controller. Either the
  1027. //! raw interrupt status or the status of interrupts that are allowed to
  1028. //! reflect to the processor can be returned.
  1029. //!
  1030. //! \return Returns the current interrupt status, enumerated as a bit field of
  1031. //! values described in EthernetIntEnable().
  1032. //
  1033. //*****************************************************************************
  1034. unsigned long
  1035. EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
  1036. {
  1037. unsigned long ulStatus;
  1038. //
  1039. // Check the arguments.
  1040. //
  1041. ASSERT(ulBase == ETH_BASE);
  1042. //
  1043. // Read the unmasked status.
  1044. //
  1045. ulStatus = HWREG(ulBase + MAC_O_RIS);
  1046. //
  1047. // If masked status is requested, mask it off.
  1048. //
  1049. if(bMasked)
  1050. {
  1051. ulStatus &= HWREG(ulBase + MAC_O_IM);
  1052. }
  1053. //
  1054. // Return the interrupt status value.
  1055. //
  1056. return(ulStatus);
  1057. }
  1058. //*****************************************************************************
  1059. //
  1060. //! Clears Ethernet interrupt sources.
  1061. //!
  1062. //! \param ulBase is the base address of the controller.
  1063. //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
  1064. //!
  1065. //! The specified Ethernet interrupt sources are cleared so that they no longer
  1066. //! assert. This must be done in the interrupt handler to keep it from being
  1067. //! called again immediately upon exit.
  1068. //!
  1069. //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
  1070. //! parameter to EthernetIntEnable().
  1071. //!
  1072. //! \note Since there is a write buffer in the Cortex-M3 processor, it may take
  1073. //! several clock cycles before the interrupt source is actually cleared.
  1074. //! Therefore, it is recommended that the interrupt source be cleared early in
  1075. //! the interrupt handler (as opposed to the very last action) to avoid
  1076. //! returning from the interrupt handler before the interrupt source is
  1077. //! actually cleared. Failure to do so may result in the interrupt handler
  1078. //! being immediately reentered (since NVIC still sees the interrupt source
  1079. //! asserted).
  1080. //!
  1081. //! \return None.
  1082. //
  1083. //*****************************************************************************
  1084. void
  1085. EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
  1086. {
  1087. //
  1088. // Check the arguments.
  1089. //
  1090. ASSERT(ulBase == ETH_BASE);
  1091. ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
  1092. ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
  1093. ETH_INT_RX)));
  1094. //
  1095. // Clear the requested interrupt sources.
  1096. //
  1097. HWREG(ulBase + MAC_O_IACK) = ulIntFlags;
  1098. }
  1099. //*****************************************************************************
  1100. //
  1101. //! Writes to the PHY register.
  1102. //!
  1103. //! \param ulBase is the base address of the controller.
  1104. //! \param ucRegAddr is the address of the PHY register to be accessed.
  1105. //! \param ulData is the data to be written to the PHY register.
  1106. //!
  1107. //! This function will write the \e ulData to the PHY register specified by
  1108. //! \e ucRegAddr.
  1109. //!
  1110. //! \return None.
  1111. //
  1112. //*****************************************************************************
  1113. void
  1114. EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
  1115. unsigned long ulData)
  1116. {
  1117. //
  1118. // Check the arguments.
  1119. //
  1120. ASSERT(ulBase == ETH_BASE);
  1121. //
  1122. // Wait for any pending transaction to complete.
  1123. //
  1124. while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
  1125. {
  1126. }
  1127. //
  1128. // Program the DATA to be written.
  1129. //
  1130. HWREG(ulBase + MAC_O_MTXD) = ulData & MAC_MTXD_MDTX_M;
  1131. //
  1132. // Program the PHY register address and initiate the transaction.
  1133. //
  1134. HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
  1135. MAC_MCTL_WRITE | MAC_MCTL_START);
  1136. //
  1137. // Wait for the write transaction to complete.
  1138. //
  1139. while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
  1140. {
  1141. }
  1142. }
  1143. //*****************************************************************************
  1144. //
  1145. //! Reads from a PHY register.
  1146. //!
  1147. //! \param ulBase is the base address of the controller.
  1148. //! \param ucRegAddr is the address of the PHY register to be accessed.
  1149. //!
  1150. //! This function will return the contents of the PHY register specified by
  1151. //! \e ucRegAddr.
  1152. //!
  1153. //! \return Returns the 16-bit value read from the PHY.
  1154. //
  1155. //*****************************************************************************
  1156. unsigned long
  1157. EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr)
  1158. {
  1159. //
  1160. // Check the arguments.
  1161. //
  1162. ASSERT(ulBase == ETH_BASE);
  1163. //
  1164. // Wait for any pending transaction to complete.
  1165. //
  1166. while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
  1167. {
  1168. }
  1169. //
  1170. // Program the PHY register address and initiate the transaction.
  1171. //
  1172. HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
  1173. MAC_MCTL_START);
  1174. //
  1175. // Wait for the transaction to complete.
  1176. //
  1177. while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
  1178. {
  1179. }
  1180. //
  1181. // Return the PHY data that was read.
  1182. //
  1183. return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M);
  1184. }
  1185. //*****************************************************************************
  1186. //
  1187. // Close the Doxygen group.
  1188. //! @}
  1189. //
  1190. //*****************************************************************************