sysctl.h 27 KB

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  1. //*****************************************************************************
  2. //
  3. // sysctl.h - Prototypes for the system control driver.
  4. //
  5. // Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Texas Instruments (TI) is supplying this software for use solely and
  9. // exclusively on TI's microcontroller products. The software is owned by
  10. // TI and/or its suppliers, and is protected under applicable copyright
  11. // laws. You may not combine this software with "viral" open-source
  12. // software in order to form a larger program.
  13. //
  14. // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
  15. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
  16. // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  17. // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
  18. // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  19. // DAMAGES, FOR ANY REASON WHATSOEVER.
  20. //
  21. // This is part of revision 6459 of the Stellaris Peripheral Driver Library.
  22. //
  23. //*****************************************************************************
  24. #ifndef __SYSCTL_H__
  25. #define __SYSCTL_H__
  26. //*****************************************************************************
  27. //
  28. // If building with a C++ compiler, make all of the definitions in this header
  29. // have a C binding.
  30. //
  31. //*****************************************************************************
  32. #ifdef __cplusplus
  33. extern "C"
  34. {
  35. #endif
  36. //*****************************************************************************
  37. //
  38. // The following are values that can be passed to the
  39. // SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
  40. // SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
  41. // ulPeripheral parameter. The peripherals in the fourth group (upper nibble
  42. // is 3) can only be used with the SysCtlPeripheralPresent() API.
  43. //
  44. //*****************************************************************************
  45. #ifndef DEPRECATED
  46. #define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
  47. #endif
  48. #define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
  49. #define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
  50. #ifndef DEPRECATED
  51. #define SYSCTL_PERIPH_ADC 0x00100001 // ADC
  52. #endif
  53. #define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
  54. #define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
  55. #define SYSCTL_PERIPH_PWM 0x00100010 // PWM
  56. #define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
  57. #define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
  58. #define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
  59. #define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
  60. #define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
  61. #define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
  62. #define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
  63. #ifndef DEPRECATED
  64. #define SYSCTL_PERIPH_SSI 0x10000010 // SSI
  65. #endif
  66. #define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
  67. #define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
  68. #ifndef DEPRECATED
  69. #define SYSCTL_PERIPH_QEI 0x10000100 // QEI
  70. #endif
  71. #define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
  72. #define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
  73. #ifndef DEPRECATED
  74. #define SYSCTL_PERIPH_I2C 0x10001000 // I2C
  75. #endif
  76. #define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
  77. #define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
  78. #define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
  79. #define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
  80. #define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
  81. #define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
  82. #define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
  83. #define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
  84. #define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
  85. #define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
  86. #define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
  87. #define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
  88. #define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
  89. #define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
  90. #define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
  91. #define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
  92. #define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
  93. #define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
  94. #define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
  95. #define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
  96. #define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
  97. #define SYSCTL_PERIPH_USB0 0x20100001 // USB0
  98. #define SYSCTL_PERIPH_ETH 0x20105000 // ETH
  99. #define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
  100. #define SYSCTL_PERIPH_PLL 0x30000010 // PLL
  101. #define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
  102. #define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
  103. //*****************************************************************************
  104. //
  105. // The following are values that can be passed to the SysCtlPinPresent() API
  106. // as the ulPin parameter.
  107. //
  108. //*****************************************************************************
  109. #define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
  110. #define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
  111. #define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
  112. #define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
  113. #define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
  114. #define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
  115. #define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
  116. #define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
  117. #define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
  118. #define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
  119. #define SYSCTL_PIN_C0O 0x00000100 // C0o pin
  120. #define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
  121. #define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
  122. #define SYSCTL_PIN_C1O 0x00000800 // C1o pin
  123. #define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
  124. #define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
  125. #define SYSCTL_PIN_C2O 0x00004000 // C2o pin
  126. #define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
  127. #define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
  128. #define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
  129. #define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
  130. #define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
  131. #define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
  132. #define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
  133. #define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
  134. #define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
  135. #define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
  136. #define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
  137. #define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
  138. #define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
  139. #define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
  140. #define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
  141. #define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
  142. //*****************************************************************************
  143. //
  144. // The following are values that can be passed to the SysCtlLDOSet() API as
  145. // the ulVoltage value, or returned by the SysCtlLDOGet() API.
  146. //
  147. //*****************************************************************************
  148. #define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
  149. #define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
  150. #define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
  151. #define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
  152. #define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
  153. #define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
  154. #define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
  155. #define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
  156. #define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
  157. #define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
  158. #define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
  159. //*****************************************************************************
  160. //
  161. // The following are values that can be passed to the SysCtlLDOConfigSet() API.
  162. //
  163. //*****************************************************************************
  164. #define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
  165. #define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
  166. //*****************************************************************************
  167. //
  168. // The following are values that can be passed to the SysCtlIntEnable(),
  169. // SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
  170. // by the SysCtlIntStatus() API.
  171. //
  172. //*****************************************************************************
  173. #define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
  174. #define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
  175. #define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
  176. #define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
  177. #define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
  178. #define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
  179. #define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
  180. #define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
  181. #define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
  182. //*****************************************************************************
  183. //
  184. // The following are values that can be passed to the SysCtlResetCauseClear()
  185. // API or returned by the SysCtlResetCauseGet() API.
  186. //
  187. //*****************************************************************************
  188. #define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
  189. #define SYSCTL_CAUSE_SW 0x00000010 // Software reset
  190. #define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
  191. #define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
  192. #define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
  193. #define SYSCTL_CAUSE_EXT 0x00000001 // External reset
  194. //*****************************************************************************
  195. //
  196. // The following are values that can be passed to the SysCtlBrownOutConfigSet()
  197. // API as the ulConfig parameter.
  198. //
  199. //*****************************************************************************
  200. #define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
  201. #define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
  202. //*****************************************************************************
  203. //
  204. // The following are values that can be passed to the SysCtlPWMClockSet() API
  205. // as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
  206. // API.
  207. //
  208. //*****************************************************************************
  209. #define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
  210. #define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
  211. #define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
  212. #define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
  213. #define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
  214. #define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
  215. #define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
  216. //*****************************************************************************
  217. //
  218. // The following are values that can be passed to the SysCtlADCSpeedSet() API
  219. // as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
  220. // API.
  221. //
  222. //*****************************************************************************
  223. #define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second
  224. #define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second
  225. #define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second
  226. #define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
  227. //*****************************************************************************
  228. //
  229. // The following are values that can be passed to the SysCtlClockSet() API as
  230. // the ulConfig parameter.
  231. //
  232. //*****************************************************************************
  233. #define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
  234. #define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
  235. #define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
  236. #define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
  237. #define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
  238. #define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
  239. #define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
  240. #define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
  241. #define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
  242. #define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
  243. #define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
  244. #define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
  245. #define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
  246. #define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
  247. #define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
  248. #define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
  249. #define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
  250. #define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
  251. #define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
  252. #define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
  253. #define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
  254. #define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
  255. #define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
  256. #define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
  257. #define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
  258. #define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
  259. #define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
  260. #define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
  261. #define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
  262. #define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
  263. #define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
  264. #define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
  265. #define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
  266. #define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
  267. #define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
  268. #define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
  269. #define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
  270. #define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
  271. #define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
  272. #define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
  273. #define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
  274. #define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
  275. #define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
  276. #define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
  277. #define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
  278. #define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
  279. #define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
  280. #define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
  281. #define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
  282. #define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
  283. #define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
  284. #define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
  285. #define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
  286. #define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
  287. #define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
  288. #define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
  289. #define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
  290. #define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
  291. #define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
  292. #define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
  293. #define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
  294. #define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
  295. #define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
  296. #define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
  297. #define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
  298. #define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
  299. #define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
  300. #define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
  301. #define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
  302. #define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
  303. #define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
  304. #define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
  305. #define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
  306. #define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
  307. #define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
  308. #define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
  309. #define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
  310. #define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
  311. #define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
  312. #define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
  313. #define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
  314. #define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
  315. #define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
  316. #define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
  317. #define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
  318. #define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
  319. #define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
  320. #define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
  321. #define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
  322. #define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
  323. #define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
  324. #define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
  325. #define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
  326. #define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
  327. #define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
  328. #define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
  329. #define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
  330. #define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
  331. #define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
  332. #define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
  333. #define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
  334. #define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
  335. #define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
  336. #define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
  337. #define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
  338. #define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
  339. #define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
  340. #define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
  341. #define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
  342. #define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
  343. #define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
  344. #define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
  345. #define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
  346. #define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
  347. #define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
  348. #define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
  349. #define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
  350. #define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
  351. #define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
  352. #define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
  353. #define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
  354. #define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
  355. #define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
  356. #define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
  357. #define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
  358. #define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
  359. #define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
  360. #define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
  361. #define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
  362. #define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
  363. #define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
  364. #define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
  365. #define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
  366. #define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
  367. #define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
  368. #define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
  369. #define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
  370. #define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
  371. #define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
  372. #define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
  373. #define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
  374. #define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
  375. #define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
  376. #define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
  377. #define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
  378. #define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
  379. #define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
  380. #define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
  381. #define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
  382. #define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
  383. #define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
  384. #define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
  385. #define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
  386. #define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
  387. #define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
  388. #define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
  389. #define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
  390. #define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc.
  391. #define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
  392. #define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
  393. //*****************************************************************************
  394. //
  395. // Prototypes for the APIs.
  396. //
  397. //*****************************************************************************
  398. extern unsigned long SysCtlSRAMSizeGet(void);
  399. extern unsigned long SysCtlFlashSizeGet(void);
  400. extern tBoolean SysCtlPinPresent(unsigned long ulPin);
  401. extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
  402. extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
  403. extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
  404. extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
  405. extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
  406. extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
  407. extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
  408. extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
  409. extern void SysCtlPeripheralClockGating(tBoolean bEnable);
  410. extern void SysCtlIntRegister(void (*pfnHandler)(void));
  411. extern void SysCtlIntUnregister(void);
  412. extern void SysCtlIntEnable(unsigned long ulInts);
  413. extern void SysCtlIntDisable(unsigned long ulInts);
  414. extern void SysCtlIntClear(unsigned long ulInts);
  415. extern unsigned long SysCtlIntStatus(tBoolean bMasked);
  416. extern void SysCtlLDOSet(unsigned long ulVoltage);
  417. extern unsigned long SysCtlLDOGet(void);
  418. extern void SysCtlLDOConfigSet(unsigned long ulConfig);
  419. extern void SysCtlReset(void);
  420. extern void SysCtlSleep(void);
  421. extern void SysCtlDeepSleep(void);
  422. extern unsigned long SysCtlResetCauseGet(void);
  423. extern void SysCtlResetCauseClear(unsigned long ulCauses);
  424. extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
  425. unsigned long ulDelay);
  426. extern void SysCtlDelay(unsigned long ulCount);
  427. extern void SysCtlClockSet(unsigned long ulConfig);
  428. extern unsigned long SysCtlClockGet(void);
  429. extern void SysCtlPWMClockSet(unsigned long ulConfig);
  430. extern unsigned long SysCtlPWMClockGet(void);
  431. extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
  432. extern unsigned long SysCtlADCSpeedGet(void);
  433. extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
  434. extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
  435. extern void SysCtlPLLVerificationSet(tBoolean bEnable);
  436. extern void SysCtlClkVerificationClear(void);
  437. extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
  438. extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
  439. extern void SysCtlUSBPLLEnable(void);
  440. extern void SysCtlUSBPLLDisable(void);
  441. extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
  442. unsigned long ulMClk);
  443. //*****************************************************************************
  444. //
  445. // Mark the end of the C bindings section for C++ compilers.
  446. //
  447. //*****************************************************************************
  448. #ifdef __cplusplus
  449. }
  450. #endif
  451. #endif // __SYSCTL_H__