watchdog.c 17 KB

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  1. //*****************************************************************************
  2. //
  3. // watchdog.c - Driver for the Watchdog Timer Module.
  4. //
  5. // Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Texas Instruments (TI) is supplying this software for use solely and
  9. // exclusively on TI's microcontroller products. The software is owned by
  10. // TI and/or its suppliers, and is protected under applicable copyright
  11. // laws. You may not combine this software with "viral" open-source
  12. // software in order to form a larger program.
  13. //
  14. // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
  15. // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
  16. // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  17. // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
  18. // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
  19. // DAMAGES, FOR ANY REASON WHATSOEVER.
  20. //
  21. // This is part of revision 6459 of the Stellaris Peripheral Driver Library.
  22. //
  23. //*****************************************************************************
  24. //*****************************************************************************
  25. //
  26. //! \addtogroup watchdog_api
  27. //! @{
  28. //
  29. //*****************************************************************************
  30. #include "inc/hw_ints.h"
  31. #include "inc/hw_memmap.h"
  32. #include "inc/hw_types.h"
  33. #include "inc/hw_watchdog.h"
  34. #include "driverlib/debug.h"
  35. #include "driverlib/interrupt.h"
  36. #include "driverlib/watchdog.h"
  37. //*****************************************************************************
  38. //
  39. //! Determines if the watchdog timer is enabled.
  40. //!
  41. //! \param ulBase is the base address of the watchdog timer module.
  42. //!
  43. //! This will check to see if the watchdog timer is enabled.
  44. //!
  45. //! \return Returns \b true if the watchdog timer is enabled, and \b false
  46. //! if it is not.
  47. //
  48. //*****************************************************************************
  49. tBoolean
  50. WatchdogRunning(unsigned long ulBase)
  51. {
  52. //
  53. // Check the arguments.
  54. //
  55. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  56. //
  57. // See if the watchdog timer module is enabled, and return.
  58. //
  59. return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
  60. }
  61. //*****************************************************************************
  62. //
  63. //! Enables the watchdog timer.
  64. //!
  65. //! \param ulBase is the base address of the watchdog timer module.
  66. //!
  67. //! This will enable the watchdog timer counter and interrupt.
  68. //!
  69. //! \note This function will have no effect if the watchdog timer has
  70. //! been locked.
  71. //!
  72. //! \sa WatchdogLock(), WatchdogUnlock()
  73. //!
  74. //! \return None.
  75. //
  76. //*****************************************************************************
  77. void
  78. WatchdogEnable(unsigned long ulBase)
  79. {
  80. //
  81. // Check the arguments.
  82. //
  83. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  84. //
  85. // Enable the watchdog timer module.
  86. //
  87. HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
  88. }
  89. //*****************************************************************************
  90. //
  91. //! Enables the watchdog timer reset.
  92. //!
  93. //! \param ulBase is the base address of the watchdog timer module.
  94. //!
  95. //! Enables the capability of the watchdog timer to issue a reset to the
  96. //! processor upon a second timeout condition.
  97. //!
  98. //! \note This function will have no effect if the watchdog timer has
  99. //! been locked.
  100. //!
  101. //! \sa WatchdogLock(), WatchdogUnlock()
  102. //!
  103. //! \return None.
  104. //
  105. //*****************************************************************************
  106. void
  107. WatchdogResetEnable(unsigned long ulBase)
  108. {
  109. //
  110. // Check the arguments.
  111. //
  112. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  113. //
  114. // Enable the watchdog reset.
  115. //
  116. HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN;
  117. }
  118. //*****************************************************************************
  119. //
  120. //! Disables the watchdog timer reset.
  121. //!
  122. //! \param ulBase is the base address of the watchdog timer module.
  123. //!
  124. //! Disables the capability of the watchdog timer to issue a reset to the
  125. //! processor upon a second timeout condition.
  126. //!
  127. //! \note This function will have no effect if the watchdog timer has
  128. //! been locked.
  129. //!
  130. //! \sa WatchdogLock(), WatchdogUnlock()
  131. //!
  132. //! \return None.
  133. //
  134. //*****************************************************************************
  135. void
  136. WatchdogResetDisable(unsigned long ulBase)
  137. {
  138. //
  139. // Check the arguments.
  140. //
  141. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  142. //
  143. // Disable the watchdog reset.
  144. //
  145. HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
  146. }
  147. //*****************************************************************************
  148. //
  149. //! Enables the watchdog timer lock mechanism.
  150. //!
  151. //! \param ulBase is the base address of the watchdog timer module.
  152. //!
  153. //! Locks out write access to the watchdog timer configuration registers.
  154. //!
  155. //! \return None.
  156. //
  157. //*****************************************************************************
  158. void
  159. WatchdogLock(unsigned long ulBase)
  160. {
  161. //
  162. // Check the arguments.
  163. //
  164. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  165. //
  166. // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
  167. // register causes the lock to go into effect.
  168. //
  169. HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
  170. }
  171. //*****************************************************************************
  172. //
  173. //! Disables the watchdog timer lock mechanism.
  174. //!
  175. //! \param ulBase is the base address of the watchdog timer module.
  176. //!
  177. //! Enables write access to the watchdog timer configuration registers.
  178. //!
  179. //! \return None.
  180. //
  181. //*****************************************************************************
  182. void
  183. WatchdogUnlock(unsigned long ulBase)
  184. {
  185. //
  186. // Check the arguments.
  187. //
  188. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  189. //
  190. // Unlock watchdog register writes.
  191. //
  192. HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
  193. }
  194. //*****************************************************************************
  195. //
  196. //! Gets the state of the watchdog timer lock mechanism.
  197. //!
  198. //! \param ulBase is the base address of the watchdog timer module.
  199. //!
  200. //! Returns the lock state of the watchdog timer registers.
  201. //!
  202. //! \return Returns \b true if the watchdog timer registers are locked, and
  203. //! \b false if they are not locked.
  204. //
  205. //*****************************************************************************
  206. tBoolean
  207. WatchdogLockState(unsigned long ulBase)
  208. {
  209. //
  210. // Check the arguments.
  211. //
  212. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  213. //
  214. // Get the lock state.
  215. //
  216. return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
  217. }
  218. //*****************************************************************************
  219. //
  220. //! Sets the watchdog timer reload value.
  221. //!
  222. //! \param ulBase is the base address of the watchdog timer module.
  223. //! \param ulLoadVal is the load value for the watchdog timer.
  224. //!
  225. //! This function sets the value to load into the watchdog timer when the count
  226. //! reaches zero for the first time; if the watchdog timer is running when this
  227. //! function is called, then the value will be immediately loaded into the
  228. //! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
  229. //! interrupt is immediately generated.
  230. //!
  231. //! \note This function will have no effect if the watchdog timer has
  232. //! been locked.
  233. //!
  234. //! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
  235. //!
  236. //! \return None.
  237. //
  238. //*****************************************************************************
  239. void
  240. WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
  241. {
  242. //
  243. // Check the arguments.
  244. //
  245. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  246. //
  247. // Set the load register.
  248. //
  249. HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
  250. }
  251. //*****************************************************************************
  252. //
  253. //! Gets the watchdog timer reload value.
  254. //!
  255. //! \param ulBase is the base address of the watchdog timer module.
  256. //!
  257. //! This function gets the value that is loaded into the watchdog timer when
  258. //! the count reaches zero for the first time.
  259. //!
  260. //! \sa WatchdogReloadSet()
  261. //!
  262. //! \return None.
  263. //
  264. //*****************************************************************************
  265. unsigned long
  266. WatchdogReloadGet(unsigned long ulBase)
  267. {
  268. //
  269. // Check the arguments.
  270. //
  271. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  272. //
  273. // Get the load register.
  274. //
  275. return(HWREG(ulBase + WDT_O_LOAD));
  276. }
  277. //*****************************************************************************
  278. //
  279. //! Gets the current watchdog timer value.
  280. //!
  281. //! \param ulBase is the base address of the watchdog timer module.
  282. //!
  283. //! This function reads the current value of the watchdog timer.
  284. //!
  285. //! \return Returns the current value of the watchdog timer.
  286. //
  287. //*****************************************************************************
  288. unsigned long
  289. WatchdogValueGet(unsigned long ulBase)
  290. {
  291. //
  292. // Check the arguments.
  293. //
  294. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  295. //
  296. // Get the current watchdog timer register value.
  297. //
  298. return(HWREG(ulBase + WDT_O_VALUE));
  299. }
  300. //*****************************************************************************
  301. //
  302. //! Registers an interrupt handler for watchdog timer interrupt.
  303. //!
  304. //! \param ulBase is the base address of the watchdog timer module.
  305. //! \param pfnHandler is a pointer to the function to be called when the
  306. //! watchdog timer interrupt occurs.
  307. //!
  308. //! This function does the actual registering of the interrupt handler. This
  309. //! will enable the global interrupt in the interrupt controller; the watchdog
  310. //! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
  311. //! handler's responsibility to clear the interrupt source via
  312. //! WatchdogIntClear().
  313. //!
  314. //! \sa IntRegister() for important information about registering interrupt
  315. //! handlers.
  316. //!
  317. //! \return None.
  318. //
  319. //*****************************************************************************
  320. void
  321. WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
  322. {
  323. //
  324. // Check the arguments.
  325. //
  326. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  327. //
  328. // Register the interrupt handler.
  329. //
  330. IntRegister(INT_WATCHDOG, pfnHandler);
  331. //
  332. // Enable the watchdog timer interrupt.
  333. //
  334. IntEnable(INT_WATCHDOG);
  335. }
  336. //*****************************************************************************
  337. //
  338. //! Unregisters an interrupt handler for the watchdog timer interrupt.
  339. //!
  340. //! \param ulBase is the base address of the watchdog timer module.
  341. //!
  342. //! This function does the actual unregistering of the interrupt handler. This
  343. //! function will clear the handler to be called when a watchdog timer
  344. //! interrupt occurs. This will also mask off the interrupt in the interrupt
  345. //! controller so that the interrupt handler no longer is called.
  346. //!
  347. //! \sa IntRegister() for important information about registering interrupt
  348. //! handlers.
  349. //!
  350. //! \return None.
  351. //
  352. //*****************************************************************************
  353. void
  354. WatchdogIntUnregister(unsigned long ulBase)
  355. {
  356. //
  357. // Check the arguments.
  358. //
  359. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  360. //
  361. // Disable the interrupt.
  362. //
  363. IntDisable(INT_WATCHDOG);
  364. //
  365. // Unregister the interrupt handler.
  366. //
  367. IntUnregister(INT_WATCHDOG);
  368. }
  369. //*****************************************************************************
  370. //
  371. //! Enables the watchdog timer interrupt.
  372. //!
  373. //! \param ulBase is the base address of the watchdog timer module.
  374. //!
  375. //! Enables the watchdog timer interrupt.
  376. //!
  377. //! \note This function will have no effect if the watchdog timer has
  378. //! been locked.
  379. //!
  380. //! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()
  381. //!
  382. //! \return None.
  383. //
  384. //*****************************************************************************
  385. void
  386. WatchdogIntEnable(unsigned long ulBase)
  387. {
  388. //
  389. // Check the arguments.
  390. //
  391. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  392. //
  393. // Enable the watchdog interrupt.
  394. //
  395. HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
  396. }
  397. //*****************************************************************************
  398. //
  399. //! Gets the current watchdog timer interrupt status.
  400. //!
  401. //! \param ulBase is the base address of the watchdog timer module.
  402. //! \param bMasked is \b false if the raw interrupt status is required and
  403. //! \b true if the masked interrupt status is required.
  404. //!
  405. //! This returns the interrupt status for the watchdog timer module. Either
  406. //! the raw interrupt status or the status of interrupt that is allowed to
  407. //! reflect to the processor can be returned.
  408. //!
  409. //! \return Returns the current interrupt status, where a 1 indicates that the
  410. //! watchdog interrupt is active, and a 0 indicates that it is not active.
  411. //
  412. //*****************************************************************************
  413. unsigned long
  414. WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
  415. {
  416. //
  417. // Check the arguments.
  418. //
  419. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  420. //
  421. // Return either the interrupt status or the raw interrupt status as
  422. // requested.
  423. //
  424. if(bMasked)
  425. {
  426. return(HWREG(ulBase + WDT_O_MIS));
  427. }
  428. else
  429. {
  430. return(HWREG(ulBase + WDT_O_RIS));
  431. }
  432. }
  433. //*****************************************************************************
  434. //
  435. //! Clears the watchdog timer interrupt.
  436. //!
  437. //! \param ulBase is the base address of the watchdog timer module.
  438. //!
  439. //! The watchdog timer interrupt source is cleared, so that it no longer
  440. //! asserts.
  441. //!
  442. //! \note Since there is a write buffer in the Cortex-M3 processor, it may take
  443. //! several clock cycles before the interrupt source is actually cleared.
  444. //! Therefore, it is recommended that the interrupt source be cleared early in
  445. //! the interrupt handler (as opposed to the very last action) to avoid
  446. //! returning from the interrupt handler before the interrupt source is
  447. //! actually cleared. Failure to do so may result in the interrupt handler
  448. //! being immediately reentered (since NVIC still sees the interrupt source
  449. //! asserted).
  450. //!
  451. //! \return None.
  452. //
  453. //*****************************************************************************
  454. void
  455. WatchdogIntClear(unsigned long ulBase)
  456. {
  457. //
  458. // Check the arguments.
  459. //
  460. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  461. //
  462. // Clear the interrupt source.
  463. //
  464. HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
  465. }
  466. //*****************************************************************************
  467. //
  468. //! Enables stalling of the watchdog timer during debug events.
  469. //!
  470. //! \param ulBase is the base address of the watchdog timer module.
  471. //!
  472. //! This function allows the watchdog timer to stop counting when the processor
  473. //! is stopped by the debugger. By doing so, the watchdog is prevented from
  474. //! expiring (typically almost immediately from a human time perspective) and
  475. //! resetting the system (if reset is enabled). The watchdog will instead
  476. //! expired after the appropriate number of processor cycles have been executed
  477. //! while debugging (or at the appropriate time after the processor has been
  478. //! restarted).
  479. //!
  480. //! \return None.
  481. //
  482. //*****************************************************************************
  483. void
  484. WatchdogStallEnable(unsigned long ulBase)
  485. {
  486. //
  487. // Check the arguments.
  488. //
  489. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  490. //
  491. // Enable timer stalling.
  492. //
  493. HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
  494. }
  495. //*****************************************************************************
  496. //
  497. //! Disables stalling of the watchdog timer during debug events.
  498. //!
  499. //! \param ulBase is the base address of the watchdog timer module.
  500. //!
  501. //! This function disables the debug mode stall of the watchdog timer. By
  502. //! doing so, the watchdog timer continues to count regardless of the processor
  503. //! debug state.
  504. //!
  505. //! \return None.
  506. //
  507. //*****************************************************************************
  508. void
  509. WatchdogStallDisable(unsigned long ulBase)
  510. {
  511. //
  512. // Check the arguments.
  513. //
  514. ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
  515. //
  516. // Disable timer stalling.
  517. //
  518. HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
  519. }
  520. //*****************************************************************************
  521. //
  522. // Close the Doxygen group.
  523. //! @}
  524. //
  525. //*****************************************************************************