usb_hc_ehci.c 41 KB

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  1. /*
  2. * Copyright (c) 2022, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usb_ehci_priv.h"
  7. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  8. #include "usb_ohci_priv.h"
  9. #endif
  10. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  11. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  12. #define EHCI_TUNE_RL_TT 0
  13. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  14. #define EHCI_TUNE_MULT_TT 1
  15. struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS];
  16. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw ehci_qh_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_EHCI_QH_NUM];
  17. /* The head of the asynchronous queue */
  18. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_async_qh_head[CONFIG_USBHOST_MAX_BUS];
  19. /* The head of the periodic queue */
  20. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_periodic_qh_head[CONFIG_USBHOST_MAX_BUS];
  21. /* The frame list */
  22. USB_NOCACHE_RAM_SECTION uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)] __attribute__((aligned(4096)));
  23. static struct ehci_qh_hw *ehci_qh_alloc(struct usbh_bus *bus)
  24. {
  25. struct ehci_qh_hw *qh;
  26. struct ehci_qtd_hw *qtd;
  27. size_t flags;
  28. flags = usb_osal_enter_critical_section();
  29. for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) {
  30. if (!g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i]) {
  31. g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i] = true;
  32. usb_osal_leave_critical_section(flags);
  33. qh = &ehci_qh_pool[bus->hcd.hcd_id][i];
  34. memset(&qh->hw, 0, sizeof(struct ehci_qh));
  35. qh->hw.hlp = QTD_LIST_END;
  36. qh->hw.overlay.next_qtd = QTD_LIST_END;
  37. qh->hw.overlay.alt_next_qtd = QTD_LIST_END;
  38. qh->urb = NULL;
  39. for (uint32_t j = 0; j < CONFIG_USB_EHCI_QTD_NUM; j++) {
  40. qtd = &qh->qtd_pool[j];
  41. qtd->hw.next_qtd = QTD_LIST_END;
  42. qtd->hw.alt_next_qtd = QTD_LIST_END;
  43. qtd->hw.token = QTD_TOKEN_STATUS_HALTED;
  44. qtd->urb = NULL;
  45. }
  46. return qh;
  47. }
  48. }
  49. usb_osal_leave_critical_section(flags);
  50. return NULL;
  51. }
  52. static void ehci_qh_free(struct usbh_bus *bus, struct ehci_qh_hw *qh)
  53. {
  54. size_t flags;
  55. for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) {
  56. if (&ehci_qh_pool[bus->hcd.hcd_id][i] == qh) {
  57. flags = usb_osal_enter_critical_section();
  58. g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i] = false;
  59. usb_osal_leave_critical_section(flags);
  60. qh->urb = NULL;
  61. return;
  62. }
  63. }
  64. }
  65. static inline void ehci_qh_add_head(struct ehci_qh_hw *head, struct ehci_qh_hw *n)
  66. {
  67. n->hw.hlp = head->hw.hlp;
  68. head->hw.hlp = QH_HLP_QH(n);
  69. }
  70. static inline void ehci_qh_remove(struct ehci_qh_hw *head, struct ehci_qh_hw *n)
  71. {
  72. struct ehci_qh_hw *tmp = head;
  73. while (EHCI_ADDR2QH(tmp->hw.hlp) && EHCI_ADDR2QH(tmp->hw.hlp) != n) {
  74. tmp = EHCI_ADDR2QH(tmp->hw.hlp);
  75. }
  76. if (tmp) {
  77. tmp->hw.hlp = n->hw.hlp;
  78. }
  79. }
  80. static int ehci_caculate_smask(int binterval)
  81. {
  82. int order, interval;
  83. interval = 1;
  84. while (binterval > 1) {
  85. interval *= 2;
  86. binterval--;
  87. }
  88. if (interval < 2) /* interval 1 */
  89. return 0xFF;
  90. if (interval < 4) /* interval 2 */
  91. return 0x55;
  92. if (interval < 8) /* interval 4 */
  93. return 0x22;
  94. for (order = 0; (interval > 1); order++) {
  95. interval >>= 1;
  96. }
  97. return (0x1 << (order % 8));
  98. }
  99. static void ehci_qh_fill(struct ehci_qh_hw *qh,
  100. uint8_t dev_addr,
  101. uint8_t ep_addr,
  102. uint8_t ep_type,
  103. uint16_t ep_mps,
  104. uint8_t ep_mult,
  105. uint8_t ep_interval,
  106. uint8_t speed,
  107. uint8_t hubaddr,
  108. uint8_t hubport)
  109. {
  110. uint32_t epchar = 0;
  111. uint32_t epcap = 0;
  112. /* QH endpoint characteristics:
  113. *
  114. * FIELD DESCRIPTION
  115. * -------- -------------------------------
  116. * DEVADDR Device address
  117. * I Inactivate on Next Transaction
  118. * ENDPT Endpoint number
  119. * EPS Endpoint speed
  120. * DTC Data toggle control
  121. * MAXPKT Max packet size
  122. * C Control endpoint
  123. * RL NAK count reloaded
  124. */
  125. /* QH endpoint capabilities
  126. *
  127. * FIELD DESCRIPTION
  128. * -------- -------------------------------
  129. * SSMASK Interrupt Schedule Mask
  130. * SCMASK Split Completion Mask
  131. * HUBADDR Hub Address
  132. * PORT Port number
  133. * MULT High band width multiplier
  134. */
  135. epchar |= ((ep_addr & 0xf) << QH_EPCHAR_ENDPT_SHIFT);
  136. epchar |= (dev_addr << QH_EPCHAR_DEVADDR_SHIFT);
  137. epchar |= (ep_mps << QH_EPCHAR_MAXPKT_SHIFT);
  138. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  139. epchar |= QH_EPCHAR_DTC; /* toggle from qtd */
  140. }
  141. switch (speed) {
  142. case USB_SPEED_LOW:
  143. epchar |= QH_EPCHAR_EPS_LOW;
  144. case USB_SPEED_FULL:
  145. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  146. epchar |= QH_EPCHAR_C; /* for TT */
  147. }
  148. if (ep_type != USB_ENDPOINT_TYPE_INTERRUPT) {
  149. epchar |= (EHCI_TUNE_RL_TT << QH_EPCHAR_RL_SHIFT);
  150. }
  151. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_TT);
  152. epcap |= QH_EPCAPS_HUBADDR(hubaddr);
  153. epcap |= QH_EPCAPS_PORT(hubport);
  154. if (ep_type == USB_ENDPOINT_TYPE_INTERRUPT) {
  155. epcap |= QH_EPCAPS_SSMASK(2);
  156. epcap |= QH_EPCAPS_SCMASK(0x78);
  157. }
  158. break;
  159. case USB_SPEED_HIGH:
  160. epchar |= QH_EPCHAR_EPS_HIGH;
  161. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  162. epchar |= (EHCI_TUNE_RL_HS << QH_EPCHAR_RL_SHIFT);
  163. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS);
  164. } else if (ep_type == USB_ENDPOINT_TYPE_BULK) {
  165. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS);
  166. } else {
  167. /* only for interrupt ep */
  168. epcap |= QH_EPCAPS_MULT(ep_mult);
  169. epcap |= ehci_caculate_smask(ep_interval);
  170. }
  171. break;
  172. default:
  173. break;
  174. }
  175. qh->hw.epchar = epchar;
  176. qh->hw.epcap = epcap;
  177. }
  178. static void ehci_qtd_bpl_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen)
  179. {
  180. uint32_t rest;
  181. qtd->hw.bpl[0] = bufaddr;
  182. rest = 0x1000 - (bufaddr & 0xfff);
  183. if (buflen < rest) {
  184. rest = buflen;
  185. } else {
  186. bufaddr += 0x1000;
  187. bufaddr &= ~0x0fff;
  188. for (int i = 1; rest < buflen && i < 5; i++) {
  189. qtd->hw.bpl[i] = bufaddr;
  190. bufaddr += 0x1000;
  191. if ((rest + 0x1000) < buflen) {
  192. rest += 0x1000;
  193. } else {
  194. rest = buflen;
  195. }
  196. }
  197. }
  198. }
  199. static void ehci_qtd_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen, uint32_t token)
  200. {
  201. /* qTD token
  202. *
  203. * FIELD DESCRIPTION
  204. * -------- -------------------------------
  205. * STATUS Status
  206. * PID PID Code
  207. * CERR Error Counter
  208. * CPAGE Current Page
  209. * IOC Interrupt on complete
  210. * NBYTES Total Bytes to Transfer
  211. * TOGGLE Data Toggle
  212. */
  213. qtd->hw.token = token;
  214. ehci_qtd_bpl_fill(qtd, bufaddr, buflen);
  215. qtd->length = buflen;
  216. }
  217. static struct ehci_qh_hw *ehci_control_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen)
  218. {
  219. struct ehci_qh_hw *qh = NULL;
  220. struct ehci_qtd_hw *qtd_setup = NULL;
  221. struct ehci_qtd_hw *qtd_data = NULL;
  222. struct ehci_qtd_hw *qtd_status = NULL;
  223. uint32_t token;
  224. size_t flags;
  225. qh = ehci_qh_alloc(bus);
  226. if (qh == NULL) {
  227. return NULL;
  228. }
  229. qtd_setup = &qh->qtd_pool[0];
  230. qtd_data = &qh->qtd_pool[1];
  231. qtd_status = &qh->qtd_pool[2];
  232. ehci_qh_fill(qh,
  233. urb->hport->dev_addr,
  234. urb->ep->bEndpointAddress,
  235. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  236. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  237. 0,
  238. 0,
  239. urb->hport->speed,
  240. urb->hport->parent->hub_addr,
  241. urb->hport->port);
  242. /* fill setup qtd */
  243. token = QTD_TOKEN_STATUS_ACTIVE |
  244. QTD_TOKEN_PID_SETUP |
  245. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  246. ((uint32_t)8 << QTD_TOKEN_NBYTES_SHIFT);
  247. ehci_qtd_fill(qtd_setup, (uintptr_t)setup, 8, token);
  248. qtd_setup->urb = urb;
  249. /* fill data qtd */
  250. if (setup->wLength > 0) {
  251. if ((setup->bmRequestType & 0x80) == 0x80) {
  252. token = QTD_TOKEN_PID_IN;
  253. } else {
  254. token = QTD_TOKEN_PID_OUT;
  255. }
  256. token |= QTD_TOKEN_STATUS_ACTIVE |
  257. QTD_TOKEN_PID_OUT |
  258. QTD_TOKEN_TOGGLE |
  259. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  260. ((uint32_t)buflen << QTD_TOKEN_NBYTES_SHIFT);
  261. ehci_qtd_fill(qtd_data, (uintptr_t)buffer, buflen, token);
  262. qtd_data->urb = urb;
  263. qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_data);
  264. qtd_data->hw.next_qtd = EHCI_PTR2ADDR(qtd_status);
  265. } else {
  266. qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_status);
  267. }
  268. /* fill status qtd */
  269. if ((setup->bmRequestType & 0x80) == 0x80) {
  270. token = QTD_TOKEN_PID_OUT;
  271. } else {
  272. token = QTD_TOKEN_PID_IN;
  273. }
  274. token |= QTD_TOKEN_STATUS_ACTIVE |
  275. QTD_TOKEN_TOGGLE |
  276. QTD_TOKEN_IOC |
  277. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  278. ((uint32_t)0 << QTD_TOKEN_NBYTES_SHIFT);
  279. ehci_qtd_fill(qtd_status, 0, 0, token);
  280. qtd_status->urb = urb;
  281. qtd_status->hw.next_qtd = QTD_LIST_END;
  282. /* update qh first qtd */
  283. qh->hw.curr_qtd = EHCI_PTR2ADDR(qtd_setup);
  284. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(qtd_setup);
  285. /* record qh first qtd */
  286. qh->first_qtd = EHCI_PTR2ADDR(qtd_setup);
  287. flags = usb_osal_enter_critical_section();
  288. qh->urb = urb;
  289. urb->hcpriv = qh;
  290. /* add qh into async list */
  291. ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh);
  292. EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN;
  293. usb_osal_leave_critical_section(flags);
  294. return qh;
  295. }
  296. static struct ehci_qh_hw *ehci_bulk_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen)
  297. {
  298. struct ehci_qh_hw *qh = NULL;
  299. struct ehci_qtd_hw *qtd = NULL;
  300. struct ehci_qtd_hw *first_qtd = NULL;
  301. struct ehci_qtd_hw *prev_qtd = NULL;
  302. uint32_t qtd_num = 0;
  303. uint32_t xfer_len = 0;
  304. uint32_t token;
  305. size_t flags;
  306. qh = ehci_qh_alloc(bus);
  307. if (qh == NULL) {
  308. return NULL;
  309. }
  310. ehci_qh_fill(qh,
  311. urb->hport->dev_addr,
  312. urb->ep->bEndpointAddress,
  313. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  314. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  315. 0,
  316. 0,
  317. urb->hport->speed,
  318. urb->hport->parent->hub_addr,
  319. urb->hport->port);
  320. while (buflen >= 0) {
  321. qtd = &qh->qtd_pool[qtd_num];
  322. if (buflen > 0x4000) {
  323. xfer_len = 0x4000;
  324. buflen -= 0x4000;
  325. } else {
  326. xfer_len = buflen;
  327. buflen = 0;
  328. }
  329. if (urb->ep->bEndpointAddress & 0x80) {
  330. token = QTD_TOKEN_PID_IN;
  331. } else {
  332. token = QTD_TOKEN_PID_OUT;
  333. }
  334. token |= QTD_TOKEN_STATUS_ACTIVE |
  335. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  336. ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT);
  337. if (buflen == 0) {
  338. token |= QTD_TOKEN_IOC;
  339. }
  340. ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token);
  341. qtd->urb = urb;
  342. qtd->hw.next_qtd = QTD_LIST_END;
  343. buffer += xfer_len;
  344. if (prev_qtd) {
  345. prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd);
  346. } else {
  347. first_qtd = qtd;
  348. }
  349. prev_qtd = qtd;
  350. if (buflen == 0) {
  351. break;
  352. }
  353. qtd_num++;
  354. if (qtd_num == CONFIG_USB_EHCI_QTD_NUM) {
  355. return NULL;
  356. }
  357. }
  358. /* update qh first qtd */
  359. qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd);
  360. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd);
  361. /* update data toggle */
  362. if (urb->data_toggle) {
  363. qh->hw.overlay.token = QTD_TOKEN_TOGGLE;
  364. } else {
  365. qh->hw.overlay.token = 0;
  366. }
  367. /* record qh first qtd */
  368. qh->first_qtd = EHCI_PTR2ADDR(first_qtd);
  369. flags = usb_osal_enter_critical_section();
  370. qh->urb = urb;
  371. urb->hcpriv = qh;
  372. /* add qh into async list */
  373. ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh);
  374. EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN;
  375. usb_osal_leave_critical_section(flags);
  376. return qh;
  377. }
  378. static struct ehci_qh_hw *ehci_intr_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen)
  379. {
  380. struct ehci_qh_hw *qh = NULL;
  381. struct ehci_qtd_hw *qtd = NULL;
  382. struct ehci_qtd_hw *first_qtd = NULL;
  383. struct ehci_qtd_hw *prev_qtd = NULL;
  384. uint32_t qtd_num = 0;
  385. uint32_t xfer_len = 0;
  386. uint32_t token;
  387. size_t flags;
  388. qh = ehci_qh_alloc(bus);
  389. if (qh == NULL) {
  390. return NULL;
  391. }
  392. ehci_qh_fill(qh,
  393. urb->hport->dev_addr,
  394. urb->ep->bEndpointAddress,
  395. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  396. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  397. USB_GET_MULT(urb->ep->wMaxPacketSize) + 1,
  398. urb->ep->bInterval,
  399. urb->hport->speed,
  400. urb->hport->parent->hub_addr,
  401. urb->hport->port);
  402. while (buflen >= 0) {
  403. qtd = &qh->qtd_pool[qtd_num];
  404. if (buflen > 0x4000) {
  405. xfer_len = 0x4000;
  406. buflen -= 0x4000;
  407. } else {
  408. xfer_len = buflen;
  409. buflen = 0;
  410. }
  411. if (urb->ep->bEndpointAddress & 0x80) {
  412. token = QTD_TOKEN_PID_IN;
  413. } else {
  414. token = QTD_TOKEN_PID_OUT;
  415. }
  416. token |= QTD_TOKEN_STATUS_ACTIVE |
  417. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  418. ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT);
  419. if (buflen == 0) {
  420. token |= QTD_TOKEN_IOC;
  421. }
  422. ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token);
  423. qtd->urb = urb;
  424. qtd->hw.next_qtd = QTD_LIST_END;
  425. buffer += xfer_len;
  426. if (prev_qtd) {
  427. prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd);
  428. } else {
  429. first_qtd = qtd;
  430. }
  431. prev_qtd = qtd;
  432. if (buflen == 0) {
  433. break;
  434. }
  435. qtd_num++;
  436. if (qtd_num == CONFIG_USB_EHCI_QTD_NUM) {
  437. return NULL;
  438. }
  439. }
  440. /* update qh first qtd */
  441. qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd);
  442. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd);
  443. /* update data toggle */
  444. if (urb->data_toggle) {
  445. qh->hw.overlay.token = QTD_TOKEN_TOGGLE;
  446. } else {
  447. qh->hw.overlay.token = 0;
  448. }
  449. /* record qh first qtd */
  450. qh->first_qtd = EHCI_PTR2ADDR(first_qtd);
  451. flags = usb_osal_enter_critical_section();
  452. qh->urb = urb;
  453. urb->hcpriv = qh;
  454. /* add qh into periodic list */
  455. ehci_qh_add_head(&g_periodic_qh_head[bus->hcd.hcd_id], qh);
  456. EHCI_HCOR->usbcmd |= EHCI_USBCMD_PSEN;
  457. usb_osal_leave_critical_section(flags);
  458. return qh;
  459. }
  460. static void ehci_urb_waitup(struct usbh_bus *bus, struct usbh_urb *urb)
  461. {
  462. struct ehci_qh_hw *qh;
  463. qh = (struct ehci_qh_hw *)urb->hcpriv;
  464. qh->urb = NULL;
  465. urb->hcpriv = NULL;
  466. qh->remove_in_iaad = 0;
  467. if (urb->timeout) {
  468. usb_osal_sem_give(qh->waitsem);
  469. } else {
  470. ehci_qh_free(bus, qh);
  471. }
  472. if (urb->complete) {
  473. if (urb->errorcode < 0) {
  474. urb->complete(urb->arg, urb->errorcode);
  475. } else {
  476. urb->complete(urb->arg, urb->actual_length);
  477. }
  478. }
  479. }
  480. static void ehci_qh_scan_qtds(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  481. {
  482. struct ehci_qtd_hw *qtd;
  483. ehci_qh_remove(qhead, qh);
  484. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  485. while (qtd) {
  486. qtd->urb->actual_length += (qtd->length - ((qtd->hw.token & QTD_TOKEN_NBYTES_MASK) >> QTD_TOKEN_NBYTES_SHIFT));
  487. qh->first_qtd = qtd->hw.next_qtd;
  488. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  489. }
  490. }
  491. static void ehci_check_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  492. {
  493. struct usbh_urb *urb;
  494. struct ehci_qtd_hw *qtd;
  495. uint32_t token;
  496. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  497. if (qtd == NULL) {
  498. return;
  499. }
  500. while (qtd) {
  501. token = qtd->hw.token;
  502. if (token & QTD_TOKEN_STATUS_ERRORS) {
  503. break;
  504. } else if (token & QTD_TOKEN_STATUS_ACTIVE) {
  505. return;
  506. }
  507. qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd);
  508. }
  509. urb = qh->urb;
  510. if ((token & QTD_TOKEN_STATUS_ERRORS) == 0) {
  511. if (token & QTD_TOKEN_TOGGLE) {
  512. urb->data_toggle = true;
  513. } else {
  514. urb->data_toggle = false;
  515. }
  516. urb->errorcode = 0;
  517. } else {
  518. if (token & QTD_TOKEN_STATUS_BABBLE) {
  519. urb->errorcode = -USB_ERR_BABBLE;
  520. urb->data_toggle = 0;
  521. } else if (token & QTD_TOKEN_STATUS_HALTED) {
  522. urb->errorcode = -USB_ERR_STALL;
  523. urb->data_toggle = 0;
  524. } else if (token & (QTD_TOKEN_STATUS_DBERR | QTD_TOKEN_STATUS_XACTERR)) {
  525. urb->errorcode = -USB_ERR_IO;
  526. }
  527. }
  528. ehci_qh_scan_qtds(bus, qhead, qh);
  529. if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
  530. ehci_urb_waitup(bus, urb);
  531. } else {
  532. qh->remove_in_iaad = 1;
  533. EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD;
  534. }
  535. }
  536. static void ehci_kill_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  537. {
  538. struct ehci_qtd_hw *qtd;
  539. ehci_qh_remove(qhead, qh);
  540. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  541. while (qtd) {
  542. qh->first_qtd = qtd->hw.next_qtd;
  543. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  544. }
  545. }
  546. static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port)
  547. {
  548. volatile uint32_t timeout = 0;
  549. uint32_t regval;
  550. #if defined(CONFIG_USB_EHCI_HPMICRO) && CONFIG_USB_EHCI_HPMICRO
  551. if ((*(volatile uint32_t *)(bus->hcd.reg_base + 0x224) & 0xc0) == (2 << 6)) { /* Hardcode for hpm */
  552. EHCI_HCOR->portsc[port - 1] |= (1 << 29);
  553. } else {
  554. EHCI_HCOR->portsc[port - 1] &= ~(1 << 29);
  555. }
  556. #endif
  557. regval = EHCI_HCOR->portsc[port - 1];
  558. regval &= ~EHCI_PORTSC_PE;
  559. regval |= EHCI_PORTSC_RESET;
  560. EHCI_HCOR->portsc[port - 1] = regval;
  561. usb_osal_msleep(55);
  562. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESET;
  563. while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESET) != 0) {
  564. usb_osal_msleep(1);
  565. timeout++;
  566. if (timeout > 100) {
  567. return -USB_ERR_TIMEOUT;
  568. }
  569. }
  570. return 0;
  571. }
  572. __WEAK void usb_hc_low_level_init(struct usbh_bus *bus)
  573. {
  574. }
  575. __WEAK void usb_hc_low_level2_init(struct usbh_bus *bus)
  576. {
  577. }
  578. __WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus)
  579. {
  580. }
  581. int usb_hc_init(struct usbh_bus *bus)
  582. {
  583. struct ehci_qh_hw *qh;
  584. volatile uint32_t timeout = 0;
  585. uint32_t regval;
  586. memset(&g_ehci_hcd[bus->hcd.hcd_id], 0, sizeof(struct ehci_hcd));
  587. memset(ehci_qh_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw) * CONFIG_USB_EHCI_QH_NUM);
  588. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  589. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  590. if ((uint32_t)&qh->hw % 32) {
  591. USB_LOG_ERR("struct ehci_qh_hw is not align 32\r\n");
  592. return -USB_ERR_INVAL;
  593. }
  594. for (uint8_t i = 0; i < CONFIG_USB_EHCI_QTD_NUM; i++) {
  595. if ((uint32_t)&qh->qtd_pool[i] % 32) {
  596. USB_LOG_ERR("struct ehci_qtd_hw is not align 32\r\n");
  597. return -USB_ERR_INVAL;
  598. }
  599. }
  600. }
  601. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  602. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  603. qh->waitsem = usb_osal_sem_create(0);
  604. }
  605. memset(&g_async_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw));
  606. g_async_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_QH(&g_async_qh_head[bus->hcd.hcd_id]);
  607. g_async_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCHAR_H;
  608. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END;
  609. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END;
  610. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED;
  611. g_async_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END;
  612. memset(g_framelist[bus->hcd.hcd_id], 0, sizeof(uint32_t) * CONFIG_USB_EHCI_FRAME_LIST_SIZE);
  613. memset(&g_periodic_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw));
  614. g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_END;
  615. g_periodic_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCAPS_SSMASK(1);
  616. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END;
  617. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END;
  618. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED;
  619. g_periodic_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END;
  620. for (uint32_t i = 0; i < CONFIG_USB_EHCI_FRAME_LIST_SIZE; i++) {
  621. g_framelist[bus->hcd.hcd_id][i] = QH_HLP_QH(&g_periodic_qh_head[bus->hcd.hcd_id]);
  622. }
  623. usb_hc_low_level_init(bus);
  624. USB_LOG_INFO("EHCI HCIVERSION:0x%04x\r\n", (unsigned int)EHCI_HCCR->hciversion);
  625. USB_LOG_INFO("EHCI HCSPARAMS:0x%06x\r\n", (unsigned int)EHCI_HCCR->hcsparams);
  626. USB_LOG_INFO("EHCI HCCPARAMS:0x%04x\r\n", (unsigned int)EHCI_HCCR->hccparams);
  627. g_ehci_hcd[bus->hcd.hcd_id].ppc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC) ? true : false;
  628. g_ehci_hcd[bus->hcd.hcd_id].n_ports = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPORTS_MASK) >> EHCI_HCSPARAMS_NPORTS_SHIFT;
  629. g_ehci_hcd[bus->hcd.hcd_id].n_cc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NCC_MASK) >> EHCI_HCSPARAMS_NCC_SHIFT;
  630. g_ehci_hcd[bus->hcd.hcd_id].n_pcc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPCC_MASK) >> EHCI_HCSPARAMS_NPCC_SHIFT;
  631. g_ehci_hcd[bus->hcd.hcd_id].has_tt = g_ehci_hcd[bus->hcd.hcd_id].n_cc ? false : true;
  632. g_ehci_hcd[bus->hcd.hcd_id].hcor_offset = EHCI_HCCR->caplength;
  633. USB_LOG_INFO("EHCI ppc:%u, n_ports:%u, n_cc:%u, n_pcc:%u\r\n",
  634. g_ehci_hcd[bus->hcd.hcd_id].ppc,
  635. g_ehci_hcd[bus->hcd.hcd_id].n_ports,
  636. g_ehci_hcd[bus->hcd.hcd_id].n_cc,
  637. g_ehci_hcd[bus->hcd.hcd_id].n_pcc);
  638. EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET;
  639. while (EHCI_HCOR->usbcmd & EHCI_USBCMD_HCRESET) {
  640. usb_osal_msleep(1);
  641. timeout++;
  642. if (timeout > 100) {
  643. return -USB_ERR_TIMEOUT;
  644. }
  645. }
  646. usb_hc_low_level2_init(bus);
  647. EHCI_HCOR->usbintr = 0;
  648. EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
  649. /* Set the Current Asynchronous List Address. */
  650. EHCI_HCOR->asynclistaddr = EHCI_PTR2ADDR(&g_async_qh_head[bus->hcd.hcd_id]);
  651. /* Set the Periodic Frame List Base Address. */
  652. EHCI_HCOR->periodiclistbase = EHCI_PTR2ADDR(g_framelist[bus->hcd.hcd_id]);
  653. regval = 0;
  654. #if CONFIG_USB_EHCI_FRAME_LIST_SIZE == 1024
  655. regval |= EHCI_USBCMD_FLSIZE_1024;
  656. #elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 512
  657. regval |= EHCI_USBCMD_FLSIZE_512;
  658. #elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 256
  659. regval |= EHCI_USBCMD_FLSIZE_256;
  660. #else
  661. #error Unsupported frame size list size
  662. #endif
  663. regval |= EHCI_USBCMD_ITHRE_1MF;
  664. regval |= EHCI_USBCMD_ASEN;
  665. regval |= EHCI_USBCMD_PSEN;
  666. regval |= EHCI_USBCMD_RUN;
  667. EHCI_HCOR->usbcmd = regval;
  668. #ifdef CONFIG_USB_EHCI_CONFIGFLAG
  669. EHCI_HCOR->configflag = EHCI_CONFIGFLAG;
  670. #endif
  671. /* Wait for the EHCI to run (no longer report halted) */
  672. timeout = 0;
  673. while (EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) {
  674. usb_osal_msleep(1);
  675. timeout++;
  676. if (timeout > 100) {
  677. return -USB_ERR_TIMEOUT;
  678. }
  679. }
  680. if (g_ehci_hcd[bus->hcd.hcd_id].ppc) {
  681. for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  682. regval = EHCI_HCOR->portsc[port];
  683. regval |= EHCI_PORTSC_PP;
  684. EHCI_HCOR->portsc[port] = regval;
  685. }
  686. }
  687. if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) {
  688. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  689. USB_LOG_INFO("EHCI uses tt for ls/fs device, so cannot enable this macro\r\n");
  690. return -USB_ERR_INVAL;
  691. #endif
  692. }
  693. if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) {
  694. USB_LOG_INFO("EHCI uses tt for ls/fs device\r\n");
  695. } else {
  696. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  697. USB_LOG_INFO("EHCI uses companion controller for ls/fs device\r\n");
  698. ohci_init(bus);
  699. #else
  700. USB_LOG_WRN("Do not enable companion controller, you should use a hub to support ls/fs device\r\n");
  701. #endif
  702. }
  703. /* Enable EHCI interrupts. */
  704. EHCI_HCOR->usbintr = EHCI_USBIE_INT | EHCI_USBIE_ERR | EHCI_USBIE_PCD | EHCI_USBIE_FATAL | EHCI_USBIE_IAA;
  705. return 0;
  706. }
  707. int usb_hc_deinit(struct usbh_bus *bus)
  708. {
  709. struct ehci_qh_hw *qh;
  710. volatile uint32_t timeout = 0;
  711. uint32_t regval;
  712. EHCI_HCOR->usbintr = 0;
  713. regval = EHCI_HCOR->usbcmd;
  714. regval &= ~EHCI_USBCMD_ASEN;
  715. regval &= ~EHCI_USBCMD_PSEN;
  716. regval &= ~EHCI_USBCMD_RUN;
  717. EHCI_HCOR->usbcmd = regval;
  718. while ((EHCI_HCOR->usbsts & (EHCI_USBSTS_PSS | EHCI_USBSTS_ASS))) {
  719. usb_osal_msleep(1);
  720. timeout++;
  721. if (timeout > 100) {
  722. return -USB_ERR_TIMEOUT;
  723. }
  724. }
  725. if (g_ehci_hcd[bus->hcd.hcd_id].ppc) {
  726. for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  727. regval = EHCI_HCOR->portsc[port];
  728. regval &= ~EHCI_PORTSC_PP;
  729. EHCI_HCOR->portsc[port] = regval;
  730. }
  731. }
  732. #ifdef CONFIG_USB_EHCI_CONFIGFLAG
  733. EHCI_HCOR->configflag = 0;
  734. #endif
  735. EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
  736. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  737. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  738. usb_osal_sem_delete(qh->waitsem);
  739. }
  740. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  741. ohci_deinit(bus);
  742. #endif
  743. usb_hc_low_level_deinit(bus);
  744. return 0;
  745. }
  746. uint16_t usbh_get_frame_number(struct usbh_bus *bus)
  747. {
  748. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  749. if (EHCI_HCOR->portsc[0] & EHCI_PORTSC_OWNER) {
  750. return ohci_get_frame_number(bus);
  751. }
  752. #endif
  753. return (((EHCI_HCOR->frindex & EHCI_FRINDEX_MASK) >> 3) & 0x3ff);
  754. }
  755. int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf)
  756. {
  757. uint8_t nports;
  758. uint8_t port;
  759. uint32_t temp, status;
  760. nports = g_ehci_hcd[bus->hcd.hcd_id].n_ports;
  761. port = setup->wIndex;
  762. temp = EHCI_HCOR->portsc[port - 1];
  763. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  764. if (temp & EHCI_PORTSC_OWNER) {
  765. return ohci_roothub_control(bus, setup, buf);
  766. }
  767. if ((temp & EHCI_PORTSC_LSTATUS_MASK) == EHCI_PORTSC_LSTATUS_KSTATE) {
  768. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER;
  769. while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) {
  770. }
  771. return ohci_roothub_control(bus, setup, buf);
  772. }
  773. #endif
  774. if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) {
  775. switch (setup->bRequest) {
  776. case HUB_REQUEST_CLEAR_FEATURE:
  777. switch (setup->wValue) {
  778. case HUB_FEATURE_HUB_C_LOCALPOWER:
  779. break;
  780. case HUB_FEATURE_HUB_C_OVERCURRENT:
  781. break;
  782. default:
  783. return -USB_ERR_NOTSUPP;
  784. }
  785. break;
  786. case HUB_REQUEST_SET_FEATURE:
  787. switch (setup->wValue) {
  788. case HUB_FEATURE_HUB_C_LOCALPOWER:
  789. break;
  790. case HUB_FEATURE_HUB_C_OVERCURRENT:
  791. break;
  792. default:
  793. return -USB_ERR_NOTSUPP;
  794. }
  795. break;
  796. case HUB_REQUEST_GET_DESCRIPTOR:
  797. break;
  798. case HUB_REQUEST_GET_STATUS:
  799. memset(buf, 0, 4);
  800. break;
  801. default:
  802. break;
  803. }
  804. } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) {
  805. switch (setup->bRequest) {
  806. case HUB_REQUEST_CLEAR_FEATURE:
  807. if (!port || port > nports) {
  808. return -USB_ERR_INVAL;
  809. }
  810. switch (setup->wValue) {
  811. case HUB_PORT_FEATURE_ENABLE:
  812. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PE;
  813. break;
  814. case HUB_PORT_FEATURE_SUSPEND:
  815. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_RESUME;
  816. usb_osal_msleep(20);
  817. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESUME;
  818. while (EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESUME) {
  819. }
  820. temp = EHCI_HCOR->usbcmd;
  821. temp |= EHCI_USBCMD_ASEN;
  822. temp |= EHCI_USBCMD_PSEN;
  823. temp |= EHCI_USBCMD_RUN;
  824. EHCI_HCOR->usbcmd = temp;
  825. while ((EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) == 0) {
  826. }
  827. case HUB_PORT_FEATURE_C_SUSPEND:
  828. break;
  829. case HUB_PORT_FEATURE_POWER:
  830. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PP;
  831. break;
  832. case HUB_PORT_FEATURE_C_CONNECTION:
  833. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_CSC;
  834. break;
  835. case HUB_PORT_FEATURE_C_ENABLE:
  836. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PEC;
  837. break;
  838. case HUB_PORT_FEATURE_C_OVER_CURREN:
  839. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OCC;
  840. break;
  841. case HUB_PORT_FEATURE_C_RESET:
  842. break;
  843. default:
  844. return -USB_ERR_NOTSUPP;
  845. }
  846. break;
  847. case HUB_REQUEST_SET_FEATURE:
  848. if (!port || port > nports) {
  849. return -USB_ERR_INVAL;
  850. }
  851. switch (setup->wValue) {
  852. case HUB_PORT_FEATURE_SUSPEND:
  853. temp = EHCI_HCOR->usbcmd;
  854. temp &= ~EHCI_USBCMD_ASEN;
  855. temp &= ~EHCI_USBCMD_PSEN;
  856. temp &= ~EHCI_USBCMD_RUN;
  857. EHCI_HCOR->usbcmd = temp;
  858. while (EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) {
  859. }
  860. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_SUSPEND;
  861. while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_SUSPEND) == 0) {
  862. }
  863. break;
  864. case HUB_PORT_FEATURE_POWER:
  865. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PP;
  866. break;
  867. case HUB_PORT_FEATURE_RESET:
  868. usbh_reset_port(bus, port);
  869. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  870. if (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_PE)) {
  871. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER;
  872. while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) {
  873. }
  874. return ohci_roothub_control(bus, setup, buf);
  875. }
  876. #endif
  877. break;
  878. default:
  879. return -USB_ERR_NOTSUPP;
  880. }
  881. break;
  882. case HUB_REQUEST_GET_STATUS:
  883. if (!port || port > nports) {
  884. return -USB_ERR_INVAL;
  885. }
  886. temp = EHCI_HCOR->portsc[port - 1];
  887. status = 0;
  888. if (temp & EHCI_PORTSC_CSC) {
  889. status |= (1 << HUB_PORT_FEATURE_C_CONNECTION);
  890. }
  891. if (temp & EHCI_PORTSC_PEC) {
  892. status |= (1 << HUB_PORT_FEATURE_C_ENABLE);
  893. }
  894. if (temp & EHCI_PORTSC_OCC) {
  895. status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN);
  896. }
  897. if (temp & EHCI_PORTSC_CCS) {
  898. status |= (1 << HUB_PORT_FEATURE_CONNECTION);
  899. }
  900. if (temp & EHCI_PORTSC_PE) {
  901. status |= (1 << HUB_PORT_FEATURE_ENABLE);
  902. if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) {
  903. status |= (1 << HUB_PORT_FEATURE_LOWSPEED);
  904. } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) {
  905. status |= (1 << HUB_PORT_FEATURE_HIGHSPEED);
  906. }
  907. }
  908. if (temp & EHCI_PORTSC_SUSPEND) {
  909. status |= (1 << HUB_PORT_FEATURE_SUSPEND);
  910. }
  911. if (temp & EHCI_PORTSC_OCA) {
  912. status |= (1 << HUB_PORT_FEATURE_OVERCURRENT);
  913. }
  914. if (temp & EHCI_PORTSC_RESET) {
  915. status |= (1 << HUB_PORT_FEATURE_RESET);
  916. }
  917. if (temp & EHCI_PORTSC_PP) {
  918. status |= (1 << HUB_PORT_FEATURE_POWER);
  919. }
  920. memcpy(buf, &status, 4);
  921. break;
  922. default:
  923. break;
  924. }
  925. }
  926. return 0;
  927. }
  928. int usbh_submit_urb(struct usbh_urb *urb)
  929. {
  930. struct ehci_qh_hw *qh = NULL;
  931. size_t flags;
  932. int ret = 0;
  933. struct usbh_hub *hub;
  934. struct usbh_hubport *hport;
  935. struct usbh_bus *bus;
  936. if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) {
  937. return -USB_ERR_INVAL;
  938. }
  939. bus = urb->hport->bus;
  940. /* find active hubport in roothub */
  941. hport = urb->hport;
  942. hub = urb->hport->parent;
  943. while (!hub->is_roothub) {
  944. hport = hub->parent;
  945. hub = hub->parent->parent;
  946. }
  947. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  948. if (EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_OWNER) {
  949. return ohci_submit_urb(urb);
  950. }
  951. #endif
  952. if (!urb->hport->connected || !(EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_CCS)) {
  953. return -USB_ERR_NOTCONN;
  954. }
  955. if (urb->errorcode == -USB_ERR_BUSY) {
  956. return -USB_ERR_BUSY;
  957. }
  958. flags = usb_osal_enter_critical_section();
  959. urb->hcpriv = NULL;
  960. urb->errorcode = -USB_ERR_BUSY;
  961. urb->actual_length = 0;
  962. usb_osal_leave_critical_section(flags);
  963. switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
  964. case USB_ENDPOINT_TYPE_CONTROL:
  965. qh = ehci_control_urb_init(bus, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length);
  966. if (qh == NULL) {
  967. return -USB_ERR_NOMEM;
  968. }
  969. break;
  970. case USB_ENDPOINT_TYPE_BULK:
  971. qh = ehci_bulk_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length);
  972. if (qh == NULL) {
  973. return -USB_ERR_NOMEM;
  974. }
  975. break;
  976. case USB_ENDPOINT_TYPE_INTERRUPT:
  977. qh = ehci_intr_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length);
  978. if (qh == NULL) {
  979. return -USB_ERR_NOMEM;
  980. }
  981. break;
  982. case USB_ENDPOINT_TYPE_ISOCHRONOUS:
  983. #ifdef CONFIG_USB_EHCI_ISO
  984. ret = ehci_iso_urb_init(bus, urb);
  985. #endif
  986. break;
  987. default:
  988. break;
  989. }
  990. if (urb->timeout > 0) {
  991. /* wait until timeout or sem give */
  992. ret = usb_osal_sem_take(qh->waitsem, urb->timeout);
  993. if (ret < 0) {
  994. goto errout_timeout;
  995. }
  996. urb->timeout = 0;
  997. ret = urb->errorcode;
  998. /* we can free qh when waitsem is done */
  999. ehci_qh_free(bus, qh);
  1000. }
  1001. return ret;
  1002. errout_timeout:
  1003. urb->timeout = 0;
  1004. usbh_kill_urb(urb);
  1005. return ret;
  1006. }
  1007. int usbh_kill_urb(struct usbh_urb *urb)
  1008. {
  1009. struct ehci_qh_hw *qh;
  1010. struct usbh_bus *bus;
  1011. size_t flags;
  1012. bool remove_in_iaad = false;
  1013. if (!urb || !urb->hport || !urb->hcpriv || !urb->hport->bus) {
  1014. return -USB_ERR_INVAL;
  1015. }
  1016. bus = urb->hport->bus;
  1017. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  1018. if (EHCI_HCOR->portsc[urb->hport->port - 1] & EHCI_PORTSC_OWNER) {
  1019. return ohci_kill_urb(urb);
  1020. }
  1021. #endif
  1022. flags = usb_osal_enter_critical_section();
  1023. EHCI_HCOR->usbcmd &= ~(EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1024. if ((USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) || (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_BULK)) {
  1025. qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp);
  1026. while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) {
  1027. if (qh->urb == urb) {
  1028. remove_in_iaad = true;
  1029. ehci_kill_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh);
  1030. }
  1031. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1032. }
  1033. } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
  1034. qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp);
  1035. while (qh) {
  1036. if (qh->urb == urb) {
  1037. ehci_kill_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh);
  1038. }
  1039. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1040. }
  1041. } else {
  1042. #ifdef CONFIG_USB_EHCI_ISO
  1043. ehci_kill_iso_urb(bus, urb);
  1044. EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1045. usb_osal_leave_critical_section(flags);
  1046. return 0;
  1047. #endif
  1048. }
  1049. EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1050. qh = (struct ehci_qh_hw *)urb->hcpriv;
  1051. urb->hcpriv = NULL;
  1052. urb->errorcode = -USB_ERR_SHUTDOWN;
  1053. qh->urb = NULL;
  1054. if (urb->timeout) {
  1055. usb_osal_sem_give(qh->waitsem);
  1056. } else {
  1057. ehci_qh_free(bus, qh);
  1058. }
  1059. if (remove_in_iaad) {
  1060. volatile uint32_t timeout = 0;
  1061. EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD;
  1062. while (!(EHCI_HCOR->usbsts & EHCI_USBSTS_IAA)) {
  1063. usb_osal_msleep(1);
  1064. timeout++;
  1065. if (timeout > 100) {
  1066. usb_osal_leave_critical_section(flags);
  1067. return -USB_ERR_TIMEOUT;
  1068. }
  1069. }
  1070. EHCI_HCOR->usbsts = EHCI_USBSTS_IAA;
  1071. }
  1072. usb_osal_leave_critical_section(flags);
  1073. return 0;
  1074. }
  1075. static void ehci_scan_async_list(struct usbh_bus *bus)
  1076. {
  1077. struct ehci_qh_hw *qh;
  1078. qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp);
  1079. while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) {
  1080. if (qh->urb) {
  1081. ehci_check_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh);
  1082. }
  1083. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1084. }
  1085. }
  1086. static void ehci_scan_periodic_list(struct usbh_bus *bus)
  1087. {
  1088. struct ehci_qh_hw *qh;
  1089. qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp);
  1090. while (qh) {
  1091. if (qh->urb) {
  1092. ehci_check_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh);
  1093. }
  1094. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1095. }
  1096. }
  1097. void USBH_IRQHandler(uint8_t busid)
  1098. {
  1099. uint32_t usbsts;
  1100. struct usbh_bus *bus;
  1101. bus = &g_usbhost_bus[busid];
  1102. usbsts = EHCI_HCOR->usbsts & EHCI_HCOR->usbintr;
  1103. EHCI_HCOR->usbsts = usbsts;
  1104. if (usbsts & EHCI_USBSTS_INT) {
  1105. ehci_scan_async_list(bus);
  1106. ehci_scan_periodic_list(bus);
  1107. #ifdef CONFIG_USB_EHCI_ISO
  1108. ehci_scan_isochronous_list(bus);
  1109. #endif
  1110. }
  1111. if (usbsts & EHCI_USBSTS_ERR) {
  1112. ehci_scan_async_list(bus);
  1113. ehci_scan_periodic_list(bus);
  1114. #ifdef CONFIG_USB_EHCI_ISO
  1115. ehci_scan_isochronous_list(bus);
  1116. #endif
  1117. }
  1118. if (usbsts & EHCI_USBSTS_PCD) {
  1119. for (int port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  1120. uint32_t portsc = EHCI_HCOR->portsc[port];
  1121. if (portsc & EHCI_PORTSC_CSC) {
  1122. if ((portsc & EHCI_PORTSC_CCS) == EHCI_PORTSC_CCS) {
  1123. } else {
  1124. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  1125. g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[index] = false;
  1126. }
  1127. for (uint8_t index = 0; index < CONFIG_USB_EHCI_ISO_NUM; index++) {
  1128. g_ehci_hcd[bus->hcd.hcd_id].ehci_iso_used[index] = false;
  1129. }
  1130. }
  1131. bus->hcd.roothub.int_buffer[0] |= (1 << (port + 1));
  1132. usbh_hub_thread_wakeup(&bus->hcd.roothub);
  1133. }
  1134. }
  1135. }
  1136. if (usbsts & EHCI_USBSTS_IAA) {
  1137. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  1138. struct ehci_qh_hw *qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  1139. if (g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[index] && qh->remove_in_iaad) {
  1140. ehci_urb_waitup(bus, qh->urb);
  1141. }
  1142. }
  1143. }
  1144. if (usbsts & EHCI_USBSTS_FATAL) {
  1145. }
  1146. }