usb_dc_fsdev.c 18 KB

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  1. /*
  2. * Copyright (c) 2022, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usbd_core.h"
  7. #ifndef CONFIG_USBDEV_FSDEV_PMA_ACCESS
  8. #error "please define CONFIG_USBDEV_FSDEV_PMA_ACCESS in usb_config.h"
  9. #endif
  10. #define PMA_ACCESS CONFIG_USBDEV_FSDEV_PMA_ACCESS
  11. #include "usb_fsdev_reg.h"
  12. #ifndef CONFIG_USB_FSDEV_RAM_SIZE
  13. #define CONFIG_USB_FSDEV_RAM_SIZE 512
  14. #endif
  15. #ifndef CONFIG_USBDEV_EP_NUM
  16. #define CONFIG_USBDEV_EP_NUM 8
  17. #endif
  18. #define USB ((USB_TypeDef *)g_usbdev_bus[0].reg_base)
  19. #define USB_BTABLE_SIZE (8 * CONFIG_USBDEV_EP_NUM)
  20. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  21. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  22. /* Endpoint state */
  23. struct fsdev_ep_state {
  24. uint16_t ep_mps; /* Endpoint max packet size */
  25. uint8_t ep_type; /* Endpoint type */
  26. uint8_t ep_stalled; /* Endpoint stall flag */
  27. uint8_t ep_enable; /* Endpoint enable */
  28. uint16_t ep_pma_buf_len; /* Previously allocated buffer size */
  29. uint16_t ep_pma_addr; /* ep pmd allocated addr */
  30. uint8_t *xfer_buf;
  31. uint32_t xfer_len;
  32. uint32_t actual_xfer_len;
  33. };
  34. /* Driver state */
  35. struct fsdev_udc {
  36. struct usb_setup_packet setup;
  37. volatile uint8_t dev_addr; /*!< USB Address */
  38. volatile uint32_t pma_offset; /*!< pma offset */
  39. struct fsdev_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
  40. struct fsdev_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
  41. } g_fsdev_udc;
  42. __WEAK void usb_dc_low_level_init(void)
  43. {
  44. }
  45. __WEAK void usb_dc_low_level_deinit(void)
  46. {
  47. }
  48. int usb_dc_init(uint8_t busid)
  49. {
  50. usb_dc_low_level_init();
  51. /* Init Device */
  52. /* CNTR_FRES = 1 */
  53. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  54. /* CNTR_FRES = 0 */
  55. USB->CNTR = 0U;
  56. /* Clear pending interrupts */
  57. USB->ISTR = 0U;
  58. /*Set Btable Address*/
  59. USB->BTABLE = BTABLE_ADDRESS;
  60. uint32_t winterruptmask;
  61. /* Set winterruptmask variable */
  62. winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
  63. USB_CNTR_SUSPM | USB_CNTR_ERRM |
  64. USB_CNTR_SOFM | USB_CNTR_ESOFM |
  65. USB_CNTR_RESETM;
  66. /* Set interrupt mask */
  67. USB->CNTR = (uint16_t)winterruptmask;
  68. /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
  69. USB->BCDR |= (uint16_t)USB_BCDR_DPPU;
  70. return 0;
  71. }
  72. int usb_dc_deinit(uint8_t busid)
  73. {
  74. /* disable all interrupts and force USB reset */
  75. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  76. /* clear interrupt status register */
  77. USB->ISTR = 0U;
  78. /* switch-off device */
  79. USB->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
  80. usb_dc_low_level_deinit();
  81. return 0;
  82. }
  83. int usbd_set_address(uint8_t busid, const uint8_t addr)
  84. {
  85. if (addr == 0U) {
  86. /* set device address and enable function */
  87. USB->DADDR = (uint16_t)USB_DADDR_EF;
  88. }
  89. g_fsdev_udc.dev_addr = addr;
  90. return 0;
  91. }
  92. uint8_t usbd_get_port_speed(uint8_t busid)
  93. {
  94. return USB_SPEED_FULL;
  95. }
  96. int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
  97. {
  98. uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
  99. if (ep_idx > (CONFIG_USBDEV_EP_NUM - 1)) {
  100. USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress);
  101. return -1;
  102. }
  103. uint16_t wEpRegVal;
  104. /* initialize Endpoint */
  105. switch (USB_GET_ENDPOINT_TYPE(ep->bmAttributes)) {
  106. case USB_ENDPOINT_TYPE_CONTROL:
  107. wEpRegVal = USB_EP_CONTROL;
  108. break;
  109. case USB_ENDPOINT_TYPE_BULK:
  110. wEpRegVal = USB_EP_BULK;
  111. break;
  112. case USB_ENDPOINT_TYPE_INTERRUPT:
  113. wEpRegVal = USB_EP_INTERRUPT;
  114. break;
  115. case USB_ENDPOINT_TYPE_ISOCHRONOUS:
  116. wEpRegVal = USB_EP_ISOCHRONOUS;
  117. break;
  118. default:
  119. break;
  120. }
  121. PCD_SET_EPTYPE(USB, ep_idx, wEpRegVal);
  122. PCD_SET_EP_ADDRESS(USB, ep_idx, ep_idx);
  123. if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) {
  124. g_fsdev_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  125. g_fsdev_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  126. g_fsdev_udc.out_ep[ep_idx].ep_enable = true;
  127. if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) {
  128. if (g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps > CONFIG_USB_FSDEV_RAM_SIZE) {
  129. USB_LOG_ERR("Ep pma %02x overflow\r\n", ep->bEndpointAddress);
  130. return -1;
  131. }
  132. g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  133. g_fsdev_udc.out_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  134. /*Set the endpoint Receive buffer address */
  135. PCD_SET_EP_RX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  136. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  137. }
  138. /*Set the endpoint Receive buffer counter*/
  139. PCD_SET_EP_RX_CNT(USB, ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize));
  140. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  141. } else {
  142. g_fsdev_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  143. g_fsdev_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  144. g_fsdev_udc.in_ep[ep_idx].ep_enable = true;
  145. if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) {
  146. if (g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps > CONFIG_USB_FSDEV_RAM_SIZE) {
  147. USB_LOG_ERR("Ep pma %02x overflow\r\n", ep->bEndpointAddress);
  148. return -1;
  149. }
  150. g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  151. g_fsdev_udc.in_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  152. /*Set the endpoint Transmit buffer address */
  153. PCD_SET_EP_TX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  154. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  155. }
  156. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  157. if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  158. /* Configure NAK status for the Endpoint */
  159. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  160. } else {
  161. /* Configure TX Endpoint to disabled state */
  162. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  163. }
  164. }
  165. return 0;
  166. }
  167. int usbd_ep_close(uint8_t busid, const uint8_t ep)
  168. {
  169. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  170. if (USB_EP_DIR_IS_OUT(ep)) {
  171. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  172. /* Configure DISABLE status for the Endpoint*/
  173. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_DIS);
  174. } else {
  175. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  176. /* Configure DISABLE status for the Endpoint*/
  177. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  178. }
  179. return 0;
  180. }
  181. int usbd_ep_set_stall(uint8_t busid, const uint8_t ep)
  182. {
  183. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  184. if (USB_EP_DIR_IS_OUT(ep)) {
  185. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_STALL);
  186. } else {
  187. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_STALL);
  188. }
  189. return 0;
  190. }
  191. int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep)
  192. {
  193. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  194. if (USB_EP_DIR_IS_OUT(ep)) {
  195. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  196. /* Configure VALID status for the Endpoint */
  197. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  198. } else {
  199. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  200. if (g_fsdev_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  201. /* Configure NAK status for the Endpoint */
  202. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  203. }
  204. }
  205. return 0;
  206. }
  207. int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled)
  208. {
  209. if (USB_EP_DIR_IS_OUT(ep)) {
  210. } else {
  211. }
  212. return 0;
  213. }
  214. int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len)
  215. {
  216. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  217. if (!data && data_len) {
  218. return -1;
  219. }
  220. if (!g_fsdev_udc.in_ep[ep_idx].ep_enable) {
  221. return -2;
  222. }
  223. g_fsdev_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
  224. g_fsdev_udc.in_ep[ep_idx].xfer_len = data_len;
  225. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len = 0;
  226. data_len = MIN(data_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  227. fsdev_write_pma(USB, (uint8_t *)data, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len);
  228. PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)data_len);
  229. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  230. return 0;
  231. }
  232. int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len)
  233. {
  234. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  235. if (!data && data_len) {
  236. return -1;
  237. }
  238. if (!g_fsdev_udc.out_ep[ep_idx].ep_enable) {
  239. return -2;
  240. }
  241. g_fsdev_udc.out_ep[ep_idx].xfer_buf = data;
  242. g_fsdev_udc.out_ep[ep_idx].xfer_len = data_len;
  243. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len = 0;
  244. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  245. return 0;
  246. }
  247. void USBD_IRQHandler(uint8_t busid)
  248. {
  249. uint16_t wIstr, wEPVal;
  250. uint8_t ep_idx;
  251. uint8_t read_count;
  252. uint16_t write_count;
  253. uint16_t store_ep[8];
  254. wIstr = USB->ISTR;
  255. if (wIstr & USB_ISTR_CTR) {
  256. while ((USB->ISTR & USB_ISTR_CTR) != 0U) {
  257. wIstr = USB->ISTR;
  258. /* extract highest priority endpoint number */
  259. ep_idx = (uint8_t)(wIstr & USB_ISTR_EP_ID);
  260. if (ep_idx == 0U) {
  261. if ((wIstr & USB_ISTR_DIR) == 0U) {
  262. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  263. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  264. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  265. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  266. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  267. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  268. if (g_fsdev_udc.setup.wLength == 0) {
  269. /* In status, start reading setup */
  270. usbd_ep_start_read(0, 0x00, NULL, 0);
  271. } else if (g_fsdev_udc.setup.wLength && ((g_fsdev_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) {
  272. /* In status, start reading setup */
  273. usbd_ep_start_read(0, 0x00, NULL, 0);
  274. }
  275. if ((g_fsdev_udc.dev_addr > 0U) && (write_count == 0U)) {
  276. USB->DADDR = ((uint16_t)g_fsdev_udc.dev_addr | USB_DADDR_EF);
  277. g_fsdev_udc.dev_addr = 0U;
  278. }
  279. } else {
  280. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  281. if ((wEPVal & USB_EP_SETUP) != 0U) {
  282. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  283. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  284. fsdev_read_pma(USB, (uint8_t *)&g_fsdev_udc.setup, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  285. usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_fsdev_udc.setup);
  286. } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  287. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  288. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  289. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  290. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  291. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  292. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  293. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  294. if (read_count == 0) {
  295. /* Out status, start reading setup */
  296. usbd_ep_start_read(0, 0x00, NULL, 0);
  297. }
  298. }
  299. }
  300. } else {
  301. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  302. if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  303. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  304. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  305. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  306. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  307. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  308. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  309. if ((read_count < g_fsdev_udc.out_ep[ep_idx].ep_mps) ||
  310. (g_fsdev_udc.out_ep[ep_idx].xfer_len == 0)) {
  311. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  312. } else {
  313. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  314. }
  315. }
  316. if ((wEPVal & USB_EP_CTR_TX) != 0U) {
  317. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  318. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  319. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  320. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  321. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  322. if (g_fsdev_udc.in_ep[ep_idx].xfer_len == 0) {
  323. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  324. } else {
  325. write_count = MIN(g_fsdev_udc.in_ep[ep_idx].xfer_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  326. fsdev_write_pma(USB, g_fsdev_udc.in_ep[ep_idx].xfer_buf, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)write_count);
  327. PCD_SET_EP_TX_CNT(USB, ep_idx, write_count);
  328. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  329. }
  330. }
  331. }
  332. }
  333. }
  334. if (wIstr & USB_ISTR_RESET) {
  335. memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc));
  336. g_fsdev_udc.pma_offset = USB_BTABLE_SIZE;
  337. usbd_event_reset_handler(0);
  338. /* start reading setup packet */
  339. PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID);
  340. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  341. }
  342. if (wIstr & USB_ISTR_PMAOVR) {
  343. USB->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR);
  344. }
  345. if (wIstr & USB_ISTR_ERR) {
  346. USB->ISTR &= (uint16_t)(~USB_ISTR_ERR);
  347. }
  348. if (wIstr & USB_ISTR_WKUP) {
  349. USB->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
  350. USB->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
  351. USB->ISTR &= (uint16_t)(~USB_ISTR_WKUP);
  352. }
  353. if (wIstr & USB_ISTR_SUSP) {
  354. /* WA: To Clear Wakeup flag if raised with suspend signal */
  355. /* Store Endpoint register */
  356. for (uint8_t i = 0U; i < 8U; i++) {
  357. store_ep[i] = PCD_GET_ENDPOINT(USB, i);
  358. }
  359. /* FORCE RESET */
  360. USB->CNTR |= (uint16_t)(USB_CNTR_FRES);
  361. /* CLEAR RESET */
  362. USB->CNTR &= (uint16_t)(~USB_CNTR_FRES);
  363. /* wait for reset flag in ISTR */
  364. while ((USB->ISTR & USB_ISTR_RESET) == 0U) {
  365. }
  366. /* Clear Reset Flag */
  367. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  368. /* Restore Registre */
  369. for (uint8_t i = 0U; i < 8U; i++) {
  370. PCD_SET_ENDPOINT(USB, i, store_ep[i]);
  371. }
  372. /* Force low-power mode in the macrocell */
  373. USB->CNTR |= (uint16_t)USB_CNTR_FSUSP;
  374. /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
  375. USB->ISTR &= (uint16_t)(~USB_ISTR_SUSP);
  376. USB->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
  377. }
  378. if (wIstr & USB_ISTR_SOF) {
  379. USB->ISTR &= (uint16_t)(~USB_ISTR_SOF);
  380. }
  381. if (wIstr & USB_ISTR_ESOF) {
  382. USB->ISTR &= (uint16_t)(~USB_ISTR_ESOF);
  383. }
  384. }
  385. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  386. {
  387. uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
  388. uint32_t BaseAddr = (uint32_t)USBx;
  389. uint32_t i, temp1, temp2;
  390. __IO uint16_t *pdwVal;
  391. uint8_t *pBuf = pbUsrBuf;
  392. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  393. for (i = n; i != 0U; i--) {
  394. temp1 = *pBuf;
  395. pBuf++;
  396. temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8));
  397. *pdwVal = (uint16_t)temp2;
  398. pdwVal++;
  399. #if PMA_ACCESS > 1U
  400. pdwVal++;
  401. #endif
  402. pBuf++;
  403. }
  404. }
  405. /**
  406. * @brief Copy data from packet memory area (PMA) to user memory buffer
  407. * @param USBx USB peripheral instance register address.
  408. * @param pbUsrBuf pointer to user memory area.
  409. * @param wPMABufAddr address into PMA.
  410. * @param wNBytes no. of bytes to be copied.
  411. * @retval None
  412. */
  413. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  414. {
  415. uint32_t n = (uint32_t)wNBytes >> 1;
  416. uint32_t BaseAddr = (uint32_t)USBx;
  417. uint32_t i, temp;
  418. __IO uint16_t *pdwVal;
  419. uint8_t *pBuf = pbUsrBuf;
  420. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  421. for (i = n; i != 0U; i--) {
  422. temp = *(__IO uint16_t *)pdwVal;
  423. pdwVal++;
  424. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  425. pBuf++;
  426. *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
  427. pBuf++;
  428. #if PMA_ACCESS > 1U
  429. pdwVal++;
  430. #endif
  431. }
  432. if ((wNBytes % 2U) != 0U) {
  433. temp = *pdwVal;
  434. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  435. }
  436. }