spi_flash_gd.c 11 KB

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  1. /*
  2. * File : spi_flash_gd.c
  3. * This file is part of RT-Thread RTOS
  4. * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
  5. * All rights reserved
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  20. *
  21. * Change Logs:
  22. * Date Author Notes
  23. * 2015-10-11 fullhan copy from winbond flash
  24. */
  25. #include <stdint.h>
  26. #include <rtthread.h>
  27. #include <rtdevice.h>
  28. #include "spi_flash.h"
  29. #include "spi_flash_gd.h"
  30. #define FLASH_DEBUG
  31. #ifdef FLASH_DEBUG
  32. #define FLASH_TRACE rt_kprintf
  33. #else
  34. #define FLASH_TRACE(...)
  35. #endif /* #ifdef FLASH_DEBUG */
  36. #define PAGE_SIZE 4096
  37. /* JEDEC Manufacturer's ID */
  38. #define MF_ID (0xC8)
  39. /* JEDEC Device ID: Memory type and Capacity */
  40. #define MTC_GD25Q128 (0x4018)
  41. /* command list */
  42. #define CMD_WRSR (0x01) /* Write Status Register */
  43. #define CMD_PP (0x02) /* Page Program */
  44. #define CMD_READ (0x03) /* Read Data */
  45. #define CMD_WRDI (0x04) /* Write Disable */
  46. #define CMD_RDSR1 (0x05) /* Read Status Register-1 */
  47. #define CMD_WREN (0x06) /* Write Enable */
  48. #define CMD_FAST_READ (0x0B) /* Fast Read */
  49. #define CMD_ERASE_4K (0x20) /* Sector Erase:4K */
  50. #define CMD_RDSR2 (0x35) /* Read Status Register-2 */
  51. #define CMD_ERASE_32K (0x52) /* 32KB Block Erase */
  52. #define CMD_JEDEC_ID (0x9F) /* Read JEDEC ID */
  53. #define CMD_ERASE_full (0xC7) /* Chip Erase */
  54. #define CMD_ERASE_64K (0xD8) /* 64KB Block Erase */
  55. #define DUMMY (0xFF)
  56. static struct spi_flash_device spi_flash_device;
  57. static void flash_lock(struct spi_flash_device * flash_device)
  58. {
  59. rt_mutex_take(&flash_device->lock, RT_WAITING_FOREVER);
  60. }
  61. static void flash_unlock(struct spi_flash_device * flash_device)
  62. {
  63. rt_mutex_release(&flash_device->lock);
  64. }
  65. static uint8_t w25qxx_read_status(void)
  66. {
  67. return rt_spi_sendrecv8(spi_flash_device.rt_spi_device, CMD_RDSR1);
  68. }
  69. static void w25qxx_wait_busy(void)
  70. {
  71. while( w25qxx_read_status() & (0x01));
  72. }
  73. /** \brief read [size] byte from [offset] to [buffer]
  74. *
  75. * \param offset uint32_t unit : byte
  76. * \param buffer uint8_t*
  77. * \param size uint32_t unit : byte
  78. * \return uint32_t byte for read
  79. *
  80. */
  81. static uint32_t w25qxx_read(uint32_t offset, uint8_t * buffer, uint32_t size)
  82. {
  83. uint8_t send_buffer[4];
  84. send_buffer[0] = CMD_WRDI;
  85. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  86. send_buffer[0] = CMD_READ;
  87. send_buffer[1] = (uint8_t)(offset>>16);
  88. send_buffer[2] = (uint8_t)(offset>>8);
  89. send_buffer[3] = (uint8_t)(offset);
  90. rt_spi_send_then_recv(spi_flash_device.rt_spi_device,
  91. send_buffer, 4,
  92. buffer, size);
  93. return size;
  94. }
  95. /** \brief write N page on [page]
  96. *
  97. * \param page_addr uint32_t unit : byte (4096 * N,1 page = 4096byte)
  98. * \param buffer const uint8_t*
  99. * \return uint32_t
  100. *
  101. */
  102. static uint32_t w25qxx_page_write(uint32_t page_addr, const uint8_t* buffer)
  103. {
  104. uint32_t index;
  105. uint8_t send_buffer[4];
  106. RT_ASSERT((page_addr&0xFF) == 0); /* page addr must align to 256byte. */
  107. send_buffer[0] = CMD_WREN;
  108. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  109. send_buffer[0] = CMD_ERASE_4K;
  110. send_buffer[1] = (page_addr >> 16);
  111. send_buffer[2] = (page_addr >> 8);
  112. send_buffer[3] = (page_addr);
  113. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 4);
  114. w25qxx_wait_busy(); // wait erase done.
  115. for(index=0; index < (PAGE_SIZE / 256); index++)
  116. {
  117. send_buffer[0] = CMD_WREN;
  118. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  119. send_buffer[0] = CMD_PP;
  120. send_buffer[1] = (uint8_t)(page_addr >> 16);
  121. send_buffer[2] = (uint8_t)(page_addr >> 8);
  122. send_buffer[3] = (uint8_t)(page_addr);
  123. rt_spi_send_then_send(spi_flash_device.rt_spi_device,
  124. send_buffer,
  125. 4,
  126. buffer,
  127. 256);
  128. buffer += 256;
  129. page_addr += 256;
  130. w25qxx_wait_busy();
  131. }
  132. send_buffer[0] = CMD_WRDI;
  133. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  134. return PAGE_SIZE;
  135. }
  136. /* RT-Thread device interface */
  137. static rt_err_t w25qxx_flash_init(rt_device_t dev)
  138. {
  139. return RT_EOK;
  140. }
  141. static rt_err_t w25qxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
  142. {
  143. uint8_t send_buffer[3];
  144. flash_lock((struct spi_flash_device *)dev);
  145. send_buffer[0] = CMD_WREN;
  146. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  147. send_buffer[0] = CMD_WRSR;
  148. send_buffer[1] = 0;
  149. send_buffer[2] = 0;
  150. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 3);
  151. w25qxx_wait_busy();
  152. flash_unlock((struct spi_flash_device *)dev);
  153. return RT_EOK;
  154. }
  155. static rt_err_t w25qxx_flash_close(rt_device_t dev)
  156. {
  157. return RT_EOK;
  158. }
  159. static rt_err_t w25qxx_flash_control(rt_device_t dev, int cmd, void *args)
  160. {
  161. RT_ASSERT(dev != RT_NULL);
  162. if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
  163. {
  164. struct rt_device_blk_geometry *geometry;
  165. geometry = (struct rt_device_blk_geometry *)args;
  166. if (geometry == RT_NULL) return -RT_ERROR;
  167. geometry->bytes_per_sector = spi_flash_device.geometry.bytes_per_sector;
  168. geometry->sector_count = spi_flash_device.geometry.sector_count;
  169. geometry->block_size = spi_flash_device.geometry.block_size;
  170. }
  171. return RT_EOK;
  172. }
  173. static rt_size_t w25qxx_flash_read(rt_device_t dev,
  174. rt_off_t pos,
  175. void* buffer,
  176. rt_size_t size)
  177. {
  178. flash_lock((struct spi_flash_device *)dev);
  179. w25qxx_read(pos*spi_flash_device.geometry.bytes_per_sector,
  180. buffer,
  181. size*spi_flash_device.geometry.bytes_per_sector);
  182. flash_unlock((struct spi_flash_device *)dev);
  183. return size;
  184. }
  185. static rt_size_t w25qxx_flash_write(rt_device_t dev,
  186. rt_off_t pos,
  187. const void* buffer,
  188. rt_size_t size)
  189. {
  190. rt_size_t i = 0;
  191. rt_size_t block = size;
  192. const uint8_t * ptr = buffer;
  193. flash_lock((struct spi_flash_device *)dev);
  194. while(block--)
  195. {
  196. w25qxx_page_write((pos + i)*spi_flash_device.geometry.bytes_per_sector,
  197. ptr);
  198. ptr += PAGE_SIZE;
  199. i++;
  200. }
  201. flash_unlock((struct spi_flash_device *)dev);
  202. return size;
  203. }
  204. #ifdef RT_USING_DEVICE_OPS
  205. const static struct rt_device_ops gd_device_ops =
  206. {
  207. w25qxx_flash_init,
  208. w25qxx_flash_open,
  209. w25qxx_flash_close,
  210. w25qxx_flash_read,
  211. w25qxx_flash_write,
  212. w25qxx_flash_control
  213. };
  214. #endif
  215. rt_err_t gd_init(const char * flash_device_name, const char * spi_device_name)
  216. {
  217. struct rt_spi_device * rt_spi_device;
  218. /* initialize mutex */
  219. if (rt_mutex_init(&spi_flash_device.lock, spi_device_name, RT_IPC_FLAG_FIFO) != RT_EOK)
  220. {
  221. rt_kprintf("init sd lock mutex failed\n");
  222. return -RT_ENOSYS;
  223. }
  224. rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
  225. if(rt_spi_device == RT_NULL)
  226. {
  227. FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
  228. return -RT_ENOSYS;
  229. }
  230. spi_flash_device.rt_spi_device = rt_spi_device;
  231. /* config spi */
  232. {
  233. struct rt_spi_configuration cfg;
  234. cfg.data_width = 8;
  235. cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
  236. cfg.max_hz = 50 * 1000 * 1000; /* 50M */
  237. rt_spi_configure(spi_flash_device.rt_spi_device, &cfg);
  238. }
  239. /* init flash */
  240. {
  241. rt_uint8_t cmd;
  242. rt_uint8_t id_recv[3];
  243. uint16_t memory_type_capacity;
  244. flash_lock(&spi_flash_device);
  245. cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
  246. rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
  247. cmd = CMD_WRDI;
  248. rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
  249. /* read flash id */
  250. cmd = CMD_JEDEC_ID;
  251. rt_spi_send_then_recv(spi_flash_device.rt_spi_device, &cmd, 1, id_recv, 3);
  252. flash_unlock(&spi_flash_device);
  253. if(id_recv[0] != MF_ID)
  254. {
  255. FLASH_TRACE("Manufacturers ID error!\r\n");
  256. FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
  257. return -RT_ENOSYS;
  258. }
  259. spi_flash_device.geometry.bytes_per_sector = 4096;
  260. spi_flash_device.geometry.block_size = 4096; /* block erase: 4k */
  261. /* get memory type and capacity */
  262. memory_type_capacity = id_recv[1];
  263. memory_type_capacity = (memory_type_capacity << 8) | id_recv[2];
  264. if(memory_type_capacity == MTC_GD25Q128)
  265. {
  266. FLASH_TRACE("GD128 detection\r\n");
  267. spi_flash_device.geometry.sector_count = 4096;
  268. }
  269. else
  270. {
  271. FLASH_TRACE("Memory Capacity error!\r\n");
  272. return -RT_ENOSYS;
  273. }
  274. }
  275. /* register device */
  276. spi_flash_device.flash_device.type = RT_Device_Class_Block;
  277. #ifdef RT_USING_DEVICE_OPS
  278. spi_flash_device.flash_device.ops = &gd_device_ops;
  279. #else
  280. spi_flash_device.flash_device.init = w25qxx_flash_init;
  281. spi_flash_device.flash_device.open = w25qxx_flash_open;
  282. spi_flash_device.flash_device.close = w25qxx_flash_close;
  283. spi_flash_device.flash_device.read = w25qxx_flash_read;
  284. spi_flash_device.flash_device.write = w25qxx_flash_write;
  285. spi_flash_device.flash_device.control = w25qxx_flash_control;
  286. #endif
  287. /* no private */
  288. spi_flash_device.flash_device.user_data = RT_NULL;
  289. rt_device_register(&spi_flash_device.flash_device, flash_device_name,
  290. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
  291. return RT_EOK;
  292. }