usb_conf.h 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132
  1. /******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
  2. * File Name : usb_conf.h
  3. * Author : MCD Application Team
  4. * Version : V3.1.0
  5. * Date : 10/30/2009
  6. * Description : Mass Storage Demo configuration header
  7. ********************************************************************************
  8. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  9. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  10. * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  11. * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  12. * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  13. * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  14. *******************************************************************************/
  15. /* Define to prevent recursive inclusion -------------------------------------*/
  16. #ifndef __USB_CONF_H
  17. #define __USB_CONF_H
  18. /*-------------------------------------------------------------*/
  19. /* EP_NUM */
  20. /* defines how many endpoints are used by the device */
  21. /*-------------------------------------------------------------*/
  22. #define EP_NUM (3)
  23. #ifndef STM32F10X_CL
  24. /*-------------------------------------------------------------*/
  25. /* -------------- Buffer Description Table -----------------*/
  26. /*-------------------------------------------------------------*/
  27. /* buffer table base address */
  28. #define BTABLE_ADDRESS (0x00)
  29. /* EP0 */
  30. /* rx/tx buffer base address */
  31. #define ENDP0_RXADDR (0x18)
  32. #define ENDP0_TXADDR (0x58)
  33. /* EP1 */
  34. /* tx buffer base address */
  35. #define ENDP1_TXADDR (0x98)
  36. /* EP2 */
  37. /* Rx buffer base address */
  38. #define ENDP2_RXADDR (0xD8)
  39. /* ISTR events */
  40. /* IMR_MSK */
  41. /* mask defining which events has to be handled */
  42. /* by the device application software */
  43. #define IMR_MSK (CNTR_CTRM | CNTR_RESETM)
  44. #endif /* STM32F10X_CL */
  45. /* CTR service routines */
  46. /* associated to defined endpoints */
  47. //#define EP1_IN_Callback NOP_Process
  48. #define EP2_IN_Callback NOP_Process
  49. #define EP3_IN_Callback NOP_Process
  50. #define EP4_IN_Callback NOP_Process
  51. #define EP5_IN_Callback NOP_Process
  52. #define EP6_IN_Callback NOP_Process
  53. #define EP7_IN_Callback NOP_Process
  54. #define EP1_OUT_Callback NOP_Process
  55. //#define EP2_OUT_Callback NOP_Process
  56. #define EP3_OUT_Callback NOP_Process
  57. #define EP4_OUT_Callback NOP_Process
  58. #define EP5_OUT_Callback NOP_Process
  59. #define EP6_OUT_Callback NOP_Process
  60. #define EP7_OUT_Callback NOP_Process
  61. #ifdef STM32F10X_CL
  62. /* OTGD-FS-DEVICE IP interrupts Enable definitions */
  63. /* Uncomment the define to enable the selected interrupt */
  64. //#define INTR_MODEMISMATCH
  65. #define INTR_SOFINTR
  66. #define INTR_RXSTSQLVL /* Mandatory */
  67. //#define INTR_NPTXFEMPTY
  68. //#define INTR_GINNAKEFF
  69. //#define INTR_GOUTNAKEFF
  70. //#define INTR_ERLYSUSPEND
  71. #define INTR_USBSUSPEND /* Mandatory */
  72. #define INTR_USBRESET /* Mandatory */
  73. #define INTR_ENUMDONE /* Mandatory */
  74. //#define INTR_ISOOUTDROP
  75. #define INTR_EOPFRAME
  76. //#define INTR_EPMISMATCH
  77. #define INTR_INEPINTR /* Mandatory */
  78. #define INTR_OUTEPINTR /* Mandatory */
  79. //#define INTR_INCOMPLISOIN
  80. //#define INTR_INCOMPLISOOUT
  81. #define INTR_WKUPINTR /* Mandatory */
  82. /* OTGD-FS-DEVICE IP interrupts subroutines */
  83. /* Comment the define to enable the selected interrupt subroutine and replace it
  84. by user code */
  85. #define INTR_MODEMISMATCH_Callback NOP_Process
  86. #define INTR_SOFINTR_Callback NOP_Process
  87. #define INTR_RXSTSQLVL_Callback NOP_Process
  88. #define INTR_NPTXFEMPTY_Callback NOP_Process
  89. #define INTR_NPTXFEMPTY_Callback NOP_Process
  90. #define INTR_GINNAKEFF_Callback NOP_Process
  91. #define INTR_GOUTNAKEFF_Callback NOP_Process
  92. #define INTR_ERLYSUSPEND_Callback NOP_Process
  93. #define INTR_USBSUSPEND_Callback NOP_Process
  94. #define INTR_USBRESET_Callback NOP_Process
  95. #define INTR_ENUMDONE_Callback NOP_Process
  96. #define INTR_ISOOUTDROP_Callback NOP_Process
  97. #define INTR_EOPFRAME_Callback NOP_Process
  98. #define INTR_EPMISMATCH_Callback NOP_Process
  99. #define INTR_INEPINTR_Callback NOP_Process
  100. #define INTR_OUTEPINTR_Callback NOP_Process
  101. #define INTR_INCOMPLISOIN_Callback NOP_Process
  102. #define INTR_INCOMPLISOOUT_Callback NOP_Process
  103. #define INTR_WKUPINTR_Callback NOP_Process
  104. /* Isochronous data update */
  105. #define INTR_RXSTSQLVL_ISODU_Callback NOP_Process
  106. /* Isochronous transfer parameters */
  107. /* Size of a single Isochronous buffer (size of a single transfer) */
  108. #define ISOC_BUFFER_SZE 1
  109. /* Number of sub-buffers (number of single buffers/transfers), should be even */
  110. #define NUM_SUB_BUFFERS 2
  111. #endif /* STM32F10X_CL */
  112. #endif /* __USB_CONF_H */
  113. /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/