drv_uart.c 16 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-08-23 AisinoChip the first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include "rtconfig.h"
  14. #include "board.h"
  15. #include "uart_config.h"
  16. #ifdef RT_USING_SERIAL
  17. #ifdef RT_SERIAL_USING_DMA
  18. struct dma_config
  19. {
  20. DMA_Channel_TypeDef *Instance;
  21. rt_uint32_t dma_rcc;
  22. IRQn_Type dma_irq;
  23. rt_uint32_t channel;
  24. rt_uint32_t request;
  25. };
  26. #endif
  27. #ifdef RT_SERIAL_USING_DMA
  28. static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag);
  29. #endif /* RT_SERIAL_USING_DMA */
  30. struct acm32_uart_config
  31. {
  32. const char *name;
  33. UART_TypeDef *Instance;
  34. IRQn_Type irq_type;
  35. enum_Enable_ID_t enable_id;
  36. #ifdef RT_SERIAL_USING_DMA
  37. struct dma_config *dma_rx;
  38. struct dma_config *dma_tx;
  39. #endif
  40. enum_GPIOx_t tx_port;
  41. enum_GPIOx_t rx_port;
  42. rt_uint32_t tx_pin;
  43. rt_uint32_t rx_pin;
  44. };
  45. struct acm32_uart
  46. {
  47. UART_HandleTypeDef handle;
  48. struct acm32_uart_config *config;
  49. #ifdef RT_SERIAL_USING_DMA
  50. struct
  51. {
  52. DMA_HandleTypeDef handle;
  53. rt_size_t last_index;
  54. } dma_rx;
  55. struct
  56. {
  57. DMA_HandleTypeDef handle;
  58. } dma_tx;
  59. #endif
  60. rt_uint16_t uart_dma_flag;
  61. struct rt_serial_device serial;
  62. };
  63. static rt_err_t uart_rx_indicate_cb(rt_device_t dev, rt_size_t size)
  64. {
  65. return RT_EOK;
  66. }
  67. static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  68. {
  69. struct acm32_uart *uart;
  70. RT_ASSERT(serial != RT_NULL);
  71. RT_ASSERT(cfg != RT_NULL);
  72. uart = rt_container_of(serial, struct acm32_uart, serial);
  73. uart->handle.Instance = uart->config->Instance;
  74. uart->handle.Init.BaudRate = cfg->baud_rate;
  75. if (cfg->data_bits == DATA_BITS_8)
  76. {
  77. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  78. }
  79. else /* not support */
  80. {
  81. return -RT_EINVAL;
  82. }
  83. if (cfg->stop_bits == STOP_BITS_1)
  84. {
  85. uart->handle.Init.StopBits = UART_STOPBITS_1;
  86. }
  87. else if (cfg->stop_bits == STOP_BITS_2)
  88. {
  89. uart->handle.Init.StopBits = UART_STOPBITS_2;
  90. }
  91. else /* not support */
  92. {
  93. return -RT_EINVAL;
  94. }
  95. if (cfg->parity == PARITY_NONE)
  96. {
  97. uart->handle.Init.Parity = UART_PARITY_NONE;
  98. }
  99. else if (cfg->parity == PARITY_ODD)
  100. {
  101. uart->handle.Init.Parity = UART_PARITY_ODD;
  102. }
  103. else if (cfg->parity == PARITY_EVEN)
  104. {
  105. uart->handle.Init.Parity = UART_PARITY_EVEN;
  106. }
  107. else /* not support */
  108. {
  109. return -RT_EINVAL;
  110. }
  111. uart->handle.Init.Mode = UART_MODE_TX_RX;
  112. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  113. HAL_UART_Init(&uart->handle);
  114. uart->handle.Instance->LCRH &= ~UART_LCRH_FEN;
  115. return RT_EOK;
  116. }
  117. static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  118. {
  119. struct acm32_uart *uart;
  120. #ifdef RT_SERIAL_USING_DMA
  121. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  122. #endif
  123. RT_ASSERT(serial != RT_NULL);
  124. uart = rt_container_of(serial, struct acm32_uart, serial);
  125. switch (cmd)
  126. {
  127. /* disable interrupt */
  128. case RT_DEVICE_CTRL_CLR_INT:
  129. NVIC_DisableIRQ(uart->config->irq_type);
  130. /* Disable RX interrupt */
  131. uart->handle.Instance->IE &= ~UART_IE_RXI;
  132. break;
  133. /* enable interrupt */
  134. case RT_DEVICE_CTRL_SET_INT:
  135. NVIC_EnableIRQ(uart->config->irq_type);
  136. /* Enable RX interrupt */
  137. uart->handle.Instance->IE |= UART_IE_RXI;
  138. break;
  139. #ifdef RT_SERIAL_USING_DMA
  140. /* UART config */
  141. case RT_DEVICE_CTRL_CONFIG :
  142. DMA_Configuration(serial, (rt_uint32_t)ctrl_arg);
  143. rt_device_set_rx_indicate((rt_device_t)serial, uart_rx_indicate_cb);
  144. break;
  145. #endif /* RT_SERIAL_USING_DMA */
  146. }
  147. return RT_EOK;
  148. }
  149. static int _uart_putc(struct rt_serial_device *serial, char c)
  150. {
  151. struct acm32_uart *uart;
  152. RT_ASSERT(serial != RT_NULL);
  153. uart = rt_container_of(serial, struct acm32_uart, serial);
  154. while (uart->handle.Instance->FR & UART_FR_TXFF); /* wait Tx FIFO not full */
  155. uart->handle.Instance->DR = c;
  156. while ((uart->handle.Instance->FR & UART_FR_BUSY)); /* wait TX Complete */
  157. return 1;
  158. }
  159. static int _uart_getc(struct rt_serial_device *serial)
  160. {
  161. struct acm32_uart *uart;
  162. int ch;
  163. RT_ASSERT(serial != RT_NULL);
  164. uart = rt_container_of(serial, struct acm32_uart, serial);
  165. ch = -1;
  166. if (!(uart->handle.Instance->FR & UART_FR_RXFE)) /* Rx FIFO not empty */
  167. {
  168. ch = uart->handle.Instance->DR & 0xff;
  169. }
  170. return ch;
  171. }
  172. #ifdef RT_SERIAL_USING_DMA
  173. /**
  174. * Serial port receive idle process. This need add to uart idle ISR.
  175. *
  176. * @param serial serial device
  177. */
  178. static void dma_uart_rx_idle_isr(struct rt_serial_device *serial)
  179. {
  180. struct acm32_uart *uart;
  181. RT_ASSERT(serial != RT_NULL);
  182. uart = rt_container_of(serial, struct acm32_uart, serial);
  183. rt_size_t recv_total_index, recv_len;
  184. rt_base_t level;
  185. /* disable interrupt */
  186. level = rt_hw_interrupt_disable();
  187. recv_total_index = uart->handle.lu32_RxSize - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
  188. recv_len = recv_total_index - uart->handle.lu32_RxCount;
  189. uart->handle.lu32_RxCount = recv_total_index;
  190. /* enable interrupt */
  191. rt_hw_interrupt_enable(level);
  192. if (recv_len)
  193. {
  194. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  195. }
  196. }
  197. /*
  198. DMA receive done process. This need add to DMA receive done ISR.
  199. @param serial serial device
  200. */
  201. static void dma_rx_done_isr(struct rt_serial_device *serial)
  202. {
  203. struct acm32_uart *uart;
  204. struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  205. RT_ASSERT(serial != RT_NULL);
  206. uart = rt_container_of(serial, struct acm32_uart, serial);
  207. rt_size_t recv_len;
  208. rt_base_t level;
  209. /* disable interrupt */
  210. level = rt_hw_interrupt_disable();
  211. recv_len = serial->config.bufsz - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
  212. uart->dma_rx.last_index = 0;
  213. DMA->INT_TC_CLR |= 1 << (uart->config->dma_rx->channel); /* clear channel0 TC flag */
  214. /* enable interrupt */
  215. rt_hw_interrupt_enable(level);
  216. if (recv_len)
  217. {
  218. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  219. }
  220. HAL_UART_Receive_DMA(&(uart->handle), &rx_fifo->buffer[rx_fifo->put_index], serial->config.bufsz);
  221. }
  222. static rt_size_t _uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  223. {
  224. struct acm32_uart *uart;
  225. RT_ASSERT(serial != RT_NULL);
  226. uart = rt_container_of(serial, struct acm32_uart, serial);
  227. if (size == 0)
  228. {
  229. return 0;
  230. }
  231. if (RT_SERIAL_DMA_TX == direction)
  232. {
  233. if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
  234. {
  235. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  236. return size;
  237. }
  238. else
  239. {
  240. return 0;
  241. }
  242. }
  243. return 0;
  244. }
  245. #endif /* RT_SERIAL_USING_DMA */
  246. static const struct rt_uart_ops acm32_uart_ops =
  247. {
  248. _uart_configure,
  249. _uart_control,
  250. _uart_putc,
  251. _uart_getc,
  252. #ifdef RT_SERIAL_USING_DMA
  253. _uart_dma_transmit,
  254. #endif
  255. };
  256. #ifdef RT_SERIAL_USING_DMA
  257. static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag)
  258. {
  259. struct rt_serial_rx_fifo *rx_fifo;
  260. DMA_HandleTypeDef *DMA_Handle;
  261. struct dma_config *dma_config;
  262. struct acm32_uart *uart;
  263. RT_ASSERT(serial != RT_NULL);
  264. uart = rt_container_of(serial, struct acm32_uart, serial);
  265. if (RT_DEVICE_FLAG_DMA_RX == flag)
  266. {
  267. DMA_Handle = &uart->dma_rx.handle;
  268. dma_config = uart->config->dma_rx;
  269. }
  270. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  271. {
  272. DMA_Handle = &uart->dma_tx.handle;
  273. dma_config = uart->config->dma_tx;
  274. }
  275. else
  276. {
  277. return;
  278. }
  279. DMA_Handle->Instance = dma_config->Instance;
  280. if (RT_DEVICE_FLAG_DMA_RX == flag)
  281. {
  282. DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_P2M;
  283. DMA_Handle->Init.Mode = DMA_NORMAL;
  284. DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_DISABLE;
  285. DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_ENABLE;
  286. }
  287. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  288. {
  289. DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_M2P;
  290. DMA_Handle->Init.Mode = DMA_NORMAL;
  291. DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_ENABLE;
  292. DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_DISABLE;
  293. }
  294. DMA_Handle->Init.Request_ID = dma_config->request;
  295. DMA_Handle->Init.Source_Width = DMA_SRC_WIDTH_BYTE;
  296. DMA_Handle->Init.Desination_Width = DMA_DST_WIDTH_BYTE;
  297. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  298. {
  299. RT_ASSERT(0);
  300. }
  301. if (RT_DEVICE_FLAG_DMA_RX == flag)
  302. {
  303. __HAL_LINK_DMA(uart->handle, HDMA_Rx, uart->dma_rx.handle);
  304. }
  305. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  306. {
  307. __HAL_LINK_DMA(uart->handle, HDMA_Tx, uart->dma_tx.handle);
  308. }
  309. /* enable interrupt */
  310. if (flag == RT_DEVICE_FLAG_DMA_RX)
  311. {
  312. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  313. /* Start DMA transfer */
  314. if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
  315. {
  316. /* Transfer error in reception process */
  317. RT_ASSERT(0);
  318. }
  319. }
  320. }
  321. #endif /* RT_SERIAL_USING_DMA */
  322. enum
  323. {
  324. #ifdef BSP_USING_UART1
  325. UART1_INDEX,
  326. #endif
  327. #ifdef BSP_USING_UART2
  328. UART2_INDEX,
  329. #endif
  330. #ifdef BSP_USING_UART3
  331. UART3_INDEX,
  332. #endif
  333. UART_MAX_INDEX,
  334. };
  335. static struct acm32_uart_config uart_config[] =
  336. {
  337. #ifdef BSP_USING_UART1
  338. UART1_CONFIG,
  339. #endif
  340. #ifdef BSP_USING_UART2
  341. UART2_CONFIG,
  342. #endif
  343. #ifdef BSP_USING_UART3
  344. UART3_CONFIG,
  345. #endif
  346. };
  347. static struct acm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  348. #ifdef RT_SERIAL_USING_DMA
  349. static void uart_get_dma_config(void)
  350. {
  351. #if defined(BSP_USING_UART1)
  352. #if defined(BSP_UART1_RX_USING_DMA)
  353. static struct dma_config uart1_rx_dma_conf = UART1_DMA_RX_CONFIG;
  354. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  355. uart_config[UART1_INDEX].dma_rx = &uart1_rx_dma_conf;
  356. #endif /* BSP_UART1_RX_USING_DMA */
  357. #if defined(BSP_UART1_TX_USING_DMA)
  358. static struct dma_config uart1_tx_dma_conf = UART1_DMA_TX_CONFIG;
  359. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  360. uart_config[UART1_INDEX].dma_tx = &uart1_tx_dma_conf;
  361. #endif /* BSP_UART1_TX_USING_DMA */
  362. #endif /* BSP_USING_UART1 */
  363. #if defined(BSP_USING_UART2)
  364. #if defined(BSP_UART2_RX_USING_DMA)
  365. static struct dma_config uart2_rx_dma_conf = UART2_DMA_RX_CONFIG;
  366. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  367. uart_config[UART2_INDEX].dma_rx = &uart2_rx_dma_conf;
  368. #endif /* BSP_UART2_RX_USING_DMA */
  369. #if defined(BSP_UART2_TX_USING_DMA)
  370. static struct dma_config uart2_tx_dma_conf = UART2_DMA_TX_CONFIG;
  371. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  372. uart_config[UART2_INDEX].dma_tx = &uart2_tx_dma_conf;
  373. #endif /* BSP_UART2_TX_USING_DMA */
  374. #endif /* BSP_USING_UART2 */
  375. #if defined(BSP_USING_UART3)
  376. #if defined(BSP_UART3_RX_USING_DMA)
  377. static struct dma_config uart3_rx_dma_conf = UART3_DMA_RX_CONFIG;
  378. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  379. uart_config[UART3_INDEX].dma_rx = &uart3_rx_dma_conf;
  380. #endif /* BSP_UART3_RX_USING_DMA */
  381. #if defined(BSP_UART3_TX_USING_DMA)
  382. static struct dma_config uart3_tx_dma_conf = UART3_DMA_TX_CONFIG;
  383. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  384. uart_config[UART3_INDEX].dma_tx = &uart3_tx_dma_conf;
  385. #endif /* BSP_UART3_TX_USING_DMA */
  386. #endif /* BSP_USING_UART3 */
  387. }
  388. #endif
  389. rt_err_t rt_hw_uart_init(void)
  390. {
  391. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct acm32_uart);
  392. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  393. rt_err_t rc = RT_EOK;
  394. #ifdef RT_SERIAL_USING_DMA
  395. uart_get_dma_config();
  396. #endif
  397. for (int i = 0; i < obj_num; i++)
  398. {
  399. uart_obj[i].config = &uart_config[i];
  400. uart_obj[i].serial.ops = &acm32_uart_ops;
  401. uart_obj[i].serial.config = config;
  402. /* register UART device */
  403. rc = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
  404. RT_DEVICE_FLAG_RDWR
  405. | RT_DEVICE_FLAG_INT_RX
  406. | RT_DEVICE_FLAG_INT_TX
  407. | uart_obj[i].uart_dma_flag
  408. , NULL);
  409. RT_ASSERT(rc == RT_EOK);
  410. }
  411. return rc;
  412. }
  413. static void uart_isr(struct rt_serial_device *serial)
  414. {
  415. struct acm32_uart *uart = rt_container_of(serial, struct acm32_uart, serial);
  416. RT_ASSERT(serial != RT_NULL);
  417. /* receive interrupt enabled */
  418. if (uart->handle.Instance->IE & UART_IE_RXI)
  419. {
  420. if (uart->handle.Instance->RIS & UART_RIS_RXI)
  421. {
  422. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  423. }
  424. }
  425. #ifdef RT_SERIAL_USING_DMA
  426. if (uart->handle.Instance->IE & UART_IE_RTI) /* Receive TimeOut Interrupt */
  427. {
  428. dma_uart_rx_idle_isr(serial);
  429. /* Clear RTI Status */
  430. uart->handle.Instance->ICR = UART_ICR_RTI;
  431. }
  432. #endif /* RT_SERIAL_USING_DMA */
  433. if (uart->handle.Instance->IE & UART_IE_TXI && \
  434. uart->handle.Instance->RIS & UART_RIS_TXI)
  435. {
  436. /* Clear TXI Status */
  437. uart->handle.Instance->ICR = UART_ICR_TXI;
  438. if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
  439. {
  440. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  441. }
  442. /* Disable TX interrupt */
  443. uart->handle.Instance->IE &= ~UART_IE_TXI;
  444. }
  445. }
  446. #if defined(BSP_USING_UART1)
  447. void UART1_IRQHandler(void)
  448. {
  449. /* enter interrupt */
  450. rt_interrupt_enter();
  451. uart_isr(&uart_obj[UART1_INDEX].serial);
  452. /* leave interrupt */
  453. rt_interrupt_leave();
  454. }
  455. #endif /* BSP_USING_UART1 */
  456. #if defined(BSP_USING_UART2)
  457. void UART2_IRQHandler(void)
  458. {
  459. /* enter interrupt */
  460. rt_interrupt_enter();
  461. uart_isr(&uart_obj[UART2_INDEX].serial);
  462. /* leave interrupt */
  463. rt_interrupt_leave();
  464. }
  465. #endif /* BSP_USING_UART1 */
  466. #if defined(BSP_USING_UART3)
  467. void UART3_IRQHandler(void)
  468. {
  469. /* enter interrupt */
  470. rt_interrupt_enter();
  471. uart_isr(&uart_obj[UART3_INDEX].serial);
  472. /* leave interrupt */
  473. rt_interrupt_leave();
  474. }
  475. #endif /* BSP_USING_UART1 */
  476. #ifdef RT_SERIAL_USING_DMA
  477. void DMA_IRQHandler(void)
  478. {
  479. /* enter interrupt */
  480. rt_interrupt_enter();
  481. for (int i = 0; i < UART_MAX_INDEX; i++)
  482. {
  483. if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_rx->channel))
  484. {
  485. dma_rx_done_isr(&uart_obj[i].serial);
  486. break;
  487. }
  488. if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_tx->channel))
  489. {
  490. DMA->INT_TC_CLR |= 1 << (uart_obj[i].config->dma_tx->channel); /* clear channel0 TC flag */
  491. break;
  492. }
  493. }
  494. /* leave interrupt */
  495. rt_interrupt_leave();
  496. }
  497. #endif /* RT_SERIAL_USING_DMA */
  498. void HAL_UART_MspInit(UART_HandleTypeDef *huart)
  499. {
  500. struct acm32_uart *uart;
  501. GPIO_InitTypeDef GPIO_Uart;
  502. RT_ASSERT(huart != RT_NULL);
  503. /* get uart object */
  504. uart = rt_container_of(huart, struct acm32_uart, handle);
  505. /* Enable Clock */
  506. System_Module_Enable(uart->config->enable_id);
  507. /* Initialization GPIO */
  508. GPIO_Uart.Pin = uart->config->tx_pin;
  509. GPIO_Uart.Mode = GPIO_MODE_AF_PP;
  510. GPIO_Uart.Pull = GPIO_PULLUP;
  511. GPIO_Uart.Alternate = GPIO_FUNCTION_2;
  512. HAL_GPIO_Init(uart->config->tx_port, &GPIO_Uart);
  513. GPIO_Uart.Pin = uart->config->rx_pin;
  514. GPIO_Uart.Mode = GPIO_MODE_AF_PP;
  515. GPIO_Uart.Pull = GPIO_PULLUP;
  516. GPIO_Uart.Alternate = GPIO_FUNCTION_2;
  517. HAL_GPIO_Init(uart->config->rx_port, &GPIO_Uart);
  518. /* NVIC Config */
  519. NVIC_ClearPendingIRQ(uart->config->irq_type);
  520. NVIC_SetPriority(uart->config->irq_type, 5);
  521. NVIC_EnableIRQ(uart->config->irq_type);
  522. }
  523. #endif /* RT_USING_SEARIAL */