am_reg_nvic.h 16 KB

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  1. //*****************************************************************************
  2. //
  3. // am_reg_nvic.h
  4. //! @file
  5. //!
  6. //! @brief Register macros for the NVIC module
  7. //
  8. //*****************************************************************************
  9. //*****************************************************************************
  10. //
  11. // Copyright (c) 2017, Ambiq Micro
  12. // All rights reserved.
  13. //
  14. // Redistribution and use in source and binary forms, with or without
  15. // modification, are permitted provided that the following conditions are met:
  16. //
  17. // 1. Redistributions of source code must retain the above copyright notice,
  18. // this list of conditions and the following disclaimer.
  19. //
  20. // 2. Redistributions in binary form must reproduce the above copyright
  21. // notice, this list of conditions and the following disclaimer in the
  22. // documentation and/or other materials provided with the distribution.
  23. //
  24. // 3. Neither the name of the copyright holder nor the names of its
  25. // contributors may be used to endorse or promote products derived from this
  26. // software without specific prior written permission.
  27. //
  28. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31. // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  32. // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33. // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  34. // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  35. // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  36. // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  37. // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. // POSSIBILITY OF SUCH DAMAGE.
  39. //
  40. // This is part of revision 1.2.11 of the AmbiqSuite Development Package.
  41. //
  42. //*****************************************************************************
  43. #ifndef AM_REG_NVIC_H
  44. #define AM_REG_NVIC_H
  45. //*****************************************************************************
  46. //
  47. // Instance finder. (1 instance(s) available)
  48. //
  49. //*****************************************************************************
  50. #define AM_REG_NVIC_NUM_MODULES 1
  51. #define AM_REG_NVICn(n) \
  52. (REG_NVIC_BASEADDR + 0x00000000 * n)
  53. //*****************************************************************************
  54. //
  55. // Register offsets.
  56. //
  57. //*****************************************************************************
  58. #define AM_REG_NVIC_ISER0_O 0xE000E100
  59. #define AM_REG_NVIC_ICER0_O 0xE000E180
  60. #define AM_REG_NVIC_ISPR0_O 0xE000E200
  61. #define AM_REG_NVIC_ICPR0_O 0xE000E280
  62. #define AM_REG_NVIC_IABR0_O 0xE000E300
  63. #define AM_REG_NVIC_IPR0_O 0xE000E400
  64. #define AM_REG_NVIC_IPR1_O 0xE000E404
  65. #define AM_REG_NVIC_IPR2_O 0xE000E408
  66. #define AM_REG_NVIC_IPR3_O 0xE000E40C
  67. #define AM_REG_NVIC_IPR4_O 0xE000E410
  68. #define AM_REG_NVIC_IPR5_O 0xE000E414
  69. #define AM_REG_NVIC_IPR6_O 0xE000E418
  70. #define AM_REG_NVIC_IPR7_O 0xE000E41C
  71. //*****************************************************************************
  72. //
  73. // NVIC_ISER0 - Interrupt Set-Enable Register 0
  74. //
  75. //*****************************************************************************
  76. // NVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0.
  77. #define AM_REG_NVIC_ISER0_BITS_S 0
  78. #define AM_REG_NVIC_ISER0_BITS_M 0xFFFFFFFF
  79. #define AM_REG_NVIC_ISER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
  80. //*****************************************************************************
  81. //
  82. // NVIC_ICER0 - Interrupt Clear-Enable Register 0
  83. //
  84. //*****************************************************************************
  85. // NVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0.
  86. #define AM_REG_NVIC_ICER0_BITS_S 0
  87. #define AM_REG_NVIC_ICER0_BITS_M 0xFFFFFFFF
  88. #define AM_REG_NVIC_ICER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
  89. //*****************************************************************************
  90. //
  91. // NVIC_ISPR0 - Interrupt Set-Pending Register 0
  92. //
  93. //*****************************************************************************
  94. // NVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0.
  95. #define AM_REG_NVIC_ISPR0_BITS_S 0
  96. #define AM_REG_NVIC_ISPR0_BITS_M 0xFFFFFFFF
  97. #define AM_REG_NVIC_ISPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
  98. //*****************************************************************************
  99. //
  100. // NVIC_ICPR0 - Interrupt Clear-Pending Register 0
  101. //
  102. //*****************************************************************************
  103. // NVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0.
  104. #define AM_REG_NVIC_ICPR0_BITS_S 0
  105. #define AM_REG_NVIC_ICPR0_BITS_M 0xFFFFFFFF
  106. #define AM_REG_NVIC_ICPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
  107. //*****************************************************************************
  108. //
  109. // NVIC_IABR0 - Interrupt Active Bit Register 0
  110. //
  111. //*****************************************************************************
  112. // NVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0.
  113. #define AM_REG_NVIC_IABR0_BITS_S 0
  114. #define AM_REG_NVIC_IABR0_BITS_M 0xFFFFFFFF
  115. #define AM_REG_NVIC_IABR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
  116. //*****************************************************************************
  117. //
  118. // NVIC_IPR0 - Interrupt Priority Register 0
  119. //
  120. //*****************************************************************************
  121. // Priority assignment for interrupt vector 3.
  122. #define AM_REG_NVIC_IPR0_PRI_N3_S 24
  123. #define AM_REG_NVIC_IPR0_PRI_N3_M 0xFF000000
  124. #define AM_REG_NVIC_IPR0_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
  125. // Priority assignment for interrupt vector 2.
  126. #define AM_REG_NVIC_IPR0_PRI_N2_S 16
  127. #define AM_REG_NVIC_IPR0_PRI_N2_M 0x00FF0000
  128. #define AM_REG_NVIC_IPR0_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
  129. // Priority assignment for interrupt vector 1.
  130. #define AM_REG_NVIC_IPR0_PRI_N1_S 8
  131. #define AM_REG_NVIC_IPR0_PRI_N1_M 0x0000FF00
  132. #define AM_REG_NVIC_IPR0_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
  133. // Priority assignment for interrupt vector 0.
  134. #define AM_REG_NVIC_IPR0_PRI_N0_S 0
  135. #define AM_REG_NVIC_IPR0_PRI_N0_M 0x000000FF
  136. #define AM_REG_NVIC_IPR0_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
  137. //*****************************************************************************
  138. //
  139. // NVIC_IPR1 - Interrupt Priority Register 1
  140. //
  141. //*****************************************************************************
  142. // Priority assignment for interrupt vector 7.
  143. #define AM_REG_NVIC_IPR1_PRI_N3_S 24
  144. #define AM_REG_NVIC_IPR1_PRI_N3_M 0xFF000000
  145. #define AM_REG_NVIC_IPR1_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
  146. // Priority assignment for interrupt vector 6.
  147. #define AM_REG_NVIC_IPR1_PRI_N2_S 16
  148. #define AM_REG_NVIC_IPR1_PRI_N2_M 0x00FF0000
  149. #define AM_REG_NVIC_IPR1_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
  150. // Priority assignment for interrupt vector 5.
  151. #define AM_REG_NVIC_IPR1_PRI_N1_S 8
  152. #define AM_REG_NVIC_IPR1_PRI_N1_M 0x0000FF00
  153. #define AM_REG_NVIC_IPR1_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
  154. // Priority assignment for interrupt vector 4.
  155. #define AM_REG_NVIC_IPR1_PRI_N0_S 0
  156. #define AM_REG_NVIC_IPR1_PRI_N0_M 0x000000FF
  157. #define AM_REG_NVIC_IPR1_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
  158. //*****************************************************************************
  159. //
  160. // NVIC_IPR2 - Interrupt Priority Register 2
  161. //
  162. //*****************************************************************************
  163. // Priority assignment for interrupt vector 11.
  164. #define AM_REG_NVIC_IPR2_PRI_N3_S 24
  165. #define AM_REG_NVIC_IPR2_PRI_N3_M 0xFF000000
  166. #define AM_REG_NVIC_IPR2_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
  167. // Priority assignment for interrupt vector 10.
  168. #define AM_REG_NVIC_IPR2_PRI_N2_S 16
  169. #define AM_REG_NVIC_IPR2_PRI_N2_M 0x00FF0000
  170. #define AM_REG_NVIC_IPR2_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
  171. // Priority assignment for interrupt vector 9.
  172. #define AM_REG_NVIC_IPR2_PRI_N1_S 8
  173. #define AM_REG_NVIC_IPR2_PRI_N1_M 0x0000FF00
  174. #define AM_REG_NVIC_IPR2_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
  175. // Priority assignment for interrupt vector 8.
  176. #define AM_REG_NVIC_IPR2_PRI_N0_S 0
  177. #define AM_REG_NVIC_IPR2_PRI_N0_M 0x000000FF
  178. #define AM_REG_NVIC_IPR2_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
  179. //*****************************************************************************
  180. //
  181. // NVIC_IPR3 - Interrupt Priority Register 3
  182. //
  183. //*****************************************************************************
  184. // Priority assignment for interrupt vector 15.
  185. #define AM_REG_NVIC_IPR3_PRI_N3_S 24
  186. #define AM_REG_NVIC_IPR3_PRI_N3_M 0xFF000000
  187. #define AM_REG_NVIC_IPR3_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
  188. // Priority assignment for interrupt vector 14.
  189. #define AM_REG_NVIC_IPR3_PRI_N2_S 16
  190. #define AM_REG_NVIC_IPR3_PRI_N2_M 0x00FF0000
  191. #define AM_REG_NVIC_IPR3_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
  192. // Priority assignment for interrupt vector 13.
  193. #define AM_REG_NVIC_IPR3_PRI_N1_S 8
  194. #define AM_REG_NVIC_IPR3_PRI_N1_M 0x0000FF00
  195. #define AM_REG_NVIC_IPR3_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
  196. // Priority assignment for interrupt vector 12.
  197. #define AM_REG_NVIC_IPR3_PRI_N0_S 0
  198. #define AM_REG_NVIC_IPR3_PRI_N0_M 0x000000FF
  199. #define AM_REG_NVIC_IPR3_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
  200. //*****************************************************************************
  201. //
  202. // NVIC_IPR4 - Interrupt Priority Register 4
  203. //
  204. //*****************************************************************************
  205. // Priority assignment for interrupt vector 19.
  206. #define AM_REG_NVIC_IPR4_PRI_N3_S 24
  207. #define AM_REG_NVIC_IPR4_PRI_N3_M 0xFF000000
  208. #define AM_REG_NVIC_IPR4_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
  209. // Priority assignment for interrupt vector 18.
  210. #define AM_REG_NVIC_IPR4_PRI_N2_S 16
  211. #define AM_REG_NVIC_IPR4_PRI_N2_M 0x00FF0000
  212. #define AM_REG_NVIC_IPR4_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
  213. // Priority assignment for interrupt vector 17.
  214. #define AM_REG_NVIC_IPR4_PRI_N1_S 8
  215. #define AM_REG_NVIC_IPR4_PRI_N1_M 0x0000FF00
  216. #define AM_REG_NVIC_IPR4_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
  217. // Priority assignment for interrupt vector 16.
  218. #define AM_REG_NVIC_IPR4_PRI_N0_S 0
  219. #define AM_REG_NVIC_IPR4_PRI_N0_M 0x000000FF
  220. #define AM_REG_NVIC_IPR4_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
  221. //*****************************************************************************
  222. //
  223. // NVIC_IPR5 - Interrupt Priority Register 5
  224. //
  225. //*****************************************************************************
  226. // Priority assignment for interrupt vector 23.
  227. #define AM_REG_NVIC_IPR5_PRI_N3_S 24
  228. #define AM_REG_NVIC_IPR5_PRI_N3_M 0xFF000000
  229. #define AM_REG_NVIC_IPR5_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
  230. // Priority assignment for interrupt vector 22.
  231. #define AM_REG_NVIC_IPR5_PRI_N2_S 16
  232. #define AM_REG_NVIC_IPR5_PRI_N2_M 0x00FF0000
  233. #define AM_REG_NVIC_IPR5_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
  234. // Priority assignment for interrupt vector 21.
  235. #define AM_REG_NVIC_IPR5_PRI_N1_S 8
  236. #define AM_REG_NVIC_IPR5_PRI_N1_M 0x0000FF00
  237. #define AM_REG_NVIC_IPR5_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
  238. // Priority assignment for interrupt vector 20.
  239. #define AM_REG_NVIC_IPR5_PRI_N0_S 0
  240. #define AM_REG_NVIC_IPR5_PRI_N0_M 0x000000FF
  241. #define AM_REG_NVIC_IPR5_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
  242. //*****************************************************************************
  243. //
  244. // NVIC_IPR6 - Interrupt Priority Register 6
  245. //
  246. //*****************************************************************************
  247. // Priority assignment for interrupt vector 27.
  248. #define AM_REG_NVIC_IPR6_PRI_N3_S 24
  249. #define AM_REG_NVIC_IPR6_PRI_N3_M 0xFF000000
  250. #define AM_REG_NVIC_IPR6_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
  251. // Priority assignment for interrupt vector 26.
  252. #define AM_REG_NVIC_IPR6_PRI_N2_S 16
  253. #define AM_REG_NVIC_IPR6_PRI_N2_M 0x00FF0000
  254. #define AM_REG_NVIC_IPR6_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
  255. // Priority assignment for interrupt vector 25.
  256. #define AM_REG_NVIC_IPR6_PRI_N1_S 8
  257. #define AM_REG_NVIC_IPR6_PRI_N1_M 0x0000FF00
  258. #define AM_REG_NVIC_IPR6_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
  259. // Priority assignment for interrupt vector 24.
  260. #define AM_REG_NVIC_IPR6_PRI_N0_S 0
  261. #define AM_REG_NVIC_IPR6_PRI_N0_M 0x000000FF
  262. #define AM_REG_NVIC_IPR6_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
  263. //*****************************************************************************
  264. //
  265. // NVIC_IPR7 - Interrupt Priority Register 7
  266. //
  267. //*****************************************************************************
  268. // Priority assignment for interrupt vector 31.
  269. #define AM_REG_NVIC_IPR7_PRI_N3_S 24
  270. #define AM_REG_NVIC_IPR7_PRI_N3_M 0xFF000000
  271. #define AM_REG_NVIC_IPR7_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
  272. // Priority assignment for interrupt vector 30.
  273. #define AM_REG_NVIC_IPR7_PRI_N2_S 16
  274. #define AM_REG_NVIC_IPR7_PRI_N2_M 0x00FF0000
  275. #define AM_REG_NVIC_IPR7_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
  276. // Priority assignment for interrupt vector 29.
  277. #define AM_REG_NVIC_IPR7_PRI_N1_S 8
  278. #define AM_REG_NVIC_IPR7_PRI_N1_M 0x0000FF00
  279. #define AM_REG_NVIC_IPR7_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
  280. // Priority assignment for interrupt vector 28.
  281. #define AM_REG_NVIC_IPR7_PRI_N0_S 0
  282. #define AM_REG_NVIC_IPR7_PRI_N0_M 0x000000FF
  283. #define AM_REG_NVIC_IPR7_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
  284. #endif // AM_REG_NVIC_H