am_reg_pdm.h 18 KB

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  1. //*****************************************************************************
  2. //
  3. // am_reg_pdm.h
  4. //! @file
  5. //!
  6. //! @brief Register macros for the PDM module
  7. //
  8. //*****************************************************************************
  9. //*****************************************************************************
  10. //
  11. // Copyright (c) 2017, Ambiq Micro
  12. // All rights reserved.
  13. //
  14. // Redistribution and use in source and binary forms, with or without
  15. // modification, are permitted provided that the following conditions are met:
  16. //
  17. // 1. Redistributions of source code must retain the above copyright notice,
  18. // this list of conditions and the following disclaimer.
  19. //
  20. // 2. Redistributions in binary form must reproduce the above copyright
  21. // notice, this list of conditions and the following disclaimer in the
  22. // documentation and/or other materials provided with the distribution.
  23. //
  24. // 3. Neither the name of the copyright holder nor the names of its
  25. // contributors may be used to endorse or promote products derived from this
  26. // software without specific prior written permission.
  27. //
  28. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29. // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30. // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31. // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  32. // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33. // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  34. // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  35. // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  36. // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  37. // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. // POSSIBILITY OF SUCH DAMAGE.
  39. //
  40. // This is part of revision 1.2.11 of the AmbiqSuite Development Package.
  41. //
  42. //*****************************************************************************
  43. #ifndef AM_REG_PDM_H
  44. #define AM_REG_PDM_H
  45. //*****************************************************************************
  46. //
  47. // Instance finder. (1 instance(s) available)
  48. //
  49. //*****************************************************************************
  50. #define AM_REG_PDM_NUM_MODULES 1
  51. #define AM_REG_PDMn(n) \
  52. (REG_PDM_BASEADDR + 0x00000000 * n)
  53. //*****************************************************************************
  54. //
  55. // Register offsets.
  56. //
  57. //*****************************************************************************
  58. #define AM_REG_PDM_PCFG_O 0x00000000
  59. #define AM_REG_PDM_VCFG_O 0x00000004
  60. #define AM_REG_PDM_FR_O 0x00000008
  61. #define AM_REG_PDM_FRD_O 0x0000000C
  62. #define AM_REG_PDM_FLUSH_O 0x00000010
  63. #define AM_REG_PDM_FTHR_O 0x00000014
  64. #define AM_REG_PDM_INTEN_O 0x00000200
  65. #define AM_REG_PDM_INTSTAT_O 0x00000204
  66. #define AM_REG_PDM_INTCLR_O 0x00000208
  67. #define AM_REG_PDM_INTSET_O 0x0000020C
  68. //*****************************************************************************
  69. //
  70. // PDM_INTEN - IO Master Interrupts: Enable
  71. //
  72. //*****************************************************************************
  73. // This is the FIFO underflow interrupt.
  74. #define AM_REG_PDM_INTEN_UNDFL_S 2
  75. #define AM_REG_PDM_INTEN_UNDFL_M 0x00000004
  76. #define AM_REG_PDM_INTEN_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
  77. // This is the FIFO overflow interrupt.
  78. #define AM_REG_PDM_INTEN_OVF_S 1
  79. #define AM_REG_PDM_INTEN_OVF_M 0x00000002
  80. #define AM_REG_PDM_INTEN_OVF(n) (((uint32_t)(n) << 1) & 0x00000002)
  81. // This is the FIFO threshold interrupt.
  82. #define AM_REG_PDM_INTEN_THR_S 0
  83. #define AM_REG_PDM_INTEN_THR_M 0x00000001
  84. #define AM_REG_PDM_INTEN_THR(n) (((uint32_t)(n) << 0) & 0x00000001)
  85. //*****************************************************************************
  86. //
  87. // PDM_INTSTAT - IO Master Interrupts: Status
  88. //
  89. //*****************************************************************************
  90. // This is the FIFO underflow interrupt.
  91. #define AM_REG_PDM_INTSTAT_UNDFL_S 2
  92. #define AM_REG_PDM_INTSTAT_UNDFL_M 0x00000004
  93. #define AM_REG_PDM_INTSTAT_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
  94. // This is the FIFO overflow interrupt.
  95. #define AM_REG_PDM_INTSTAT_OVF_S 1
  96. #define AM_REG_PDM_INTSTAT_OVF_M 0x00000002
  97. #define AM_REG_PDM_INTSTAT_OVF(n) (((uint32_t)(n) << 1) & 0x00000002)
  98. // This is the FIFO threshold interrupt.
  99. #define AM_REG_PDM_INTSTAT_THR_S 0
  100. #define AM_REG_PDM_INTSTAT_THR_M 0x00000001
  101. #define AM_REG_PDM_INTSTAT_THR(n) (((uint32_t)(n) << 0) & 0x00000001)
  102. //*****************************************************************************
  103. //
  104. // PDM_INTCLR - IO Master Interrupts: Clear
  105. //
  106. //*****************************************************************************
  107. // This is the FIFO underflow interrupt.
  108. #define AM_REG_PDM_INTCLR_UNDFL_S 2
  109. #define AM_REG_PDM_INTCLR_UNDFL_M 0x00000004
  110. #define AM_REG_PDM_INTCLR_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
  111. // This is the FIFO overflow interrupt.
  112. #define AM_REG_PDM_INTCLR_OVF_S 1
  113. #define AM_REG_PDM_INTCLR_OVF_M 0x00000002
  114. #define AM_REG_PDM_INTCLR_OVF(n) (((uint32_t)(n) << 1) & 0x00000002)
  115. // This is the FIFO threshold interrupt.
  116. #define AM_REG_PDM_INTCLR_THR_S 0
  117. #define AM_REG_PDM_INTCLR_THR_M 0x00000001
  118. #define AM_REG_PDM_INTCLR_THR(n) (((uint32_t)(n) << 0) & 0x00000001)
  119. //*****************************************************************************
  120. //
  121. // PDM_INTSET - IO Master Interrupts: Set
  122. //
  123. //*****************************************************************************
  124. // This is the FIFO underflow interrupt.
  125. #define AM_REG_PDM_INTSET_UNDFL_S 2
  126. #define AM_REG_PDM_INTSET_UNDFL_M 0x00000004
  127. #define AM_REG_PDM_INTSET_UNDFL(n) (((uint32_t)(n) << 2) & 0x00000004)
  128. // This is the FIFO overflow interrupt.
  129. #define AM_REG_PDM_INTSET_OVF_S 1
  130. #define AM_REG_PDM_INTSET_OVF_M 0x00000002
  131. #define AM_REG_PDM_INTSET_OVF(n) (((uint32_t)(n) << 1) & 0x00000002)
  132. // This is the FIFO threshold interrupt.
  133. #define AM_REG_PDM_INTSET_THR_S 0
  134. #define AM_REG_PDM_INTSET_THR_M 0x00000001
  135. #define AM_REG_PDM_INTSET_THR(n) (((uint32_t)(n) << 0) & 0x00000001)
  136. //*****************************************************************************
  137. //
  138. // PDM_PCFG - PDM Configuration Register
  139. //
  140. //*****************************************************************************
  141. // Left/right channel swap.
  142. #define AM_REG_PDM_PCFG_LRSWAP_S 31
  143. #define AM_REG_PDM_PCFG_LRSWAP_M 0x80000000
  144. #define AM_REG_PDM_PCFG_LRSWAP(n) (((uint32_t)(n) << 31) & 0x80000000)
  145. #define AM_REG_PDM_PCFG_LRSWAP_EN 0x80000000
  146. #define AM_REG_PDM_PCFG_LRSWAP_NOSWAP 0x00000000
  147. // Right channel PGA gain.
  148. #define AM_REG_PDM_PCFG_PGARIGHT_S 27
  149. #define AM_REG_PDM_PCFG_PGARIGHT_M 0x78000000
  150. #define AM_REG_PDM_PCFG_PGARIGHT(n) (((uint32_t)(n) << 27) & 0x78000000)
  151. #define AM_REG_PDM_PCFG_PGARIGHT_M15DB 0x78000000
  152. #define AM_REG_PDM_PCFG_PGARIGHT_M300DB 0x70000000
  153. #define AM_REG_PDM_PCFG_PGARIGHT_M45DB 0x68000000
  154. #define AM_REG_PDM_PCFG_PGARIGHT_M60DB 0x60000000
  155. #define AM_REG_PDM_PCFG_PGARIGHT_M75DB 0x58000000
  156. #define AM_REG_PDM_PCFG_PGARIGHT_M90DB 0x50000000
  157. #define AM_REG_PDM_PCFG_PGARIGHT_M105DB 0x48000000
  158. #define AM_REG_PDM_PCFG_PGARIGHT_M120DB 0x40000000
  159. #define AM_REG_PDM_PCFG_PGARIGHT_P105DB 0x38000000
  160. #define AM_REG_PDM_PCFG_PGARIGHT_P90DB 0x30000000
  161. #define AM_REG_PDM_PCFG_PGARIGHT_P75DB 0x28000000
  162. #define AM_REG_PDM_PCFG_PGARIGHT_P60DB 0x20000000
  163. #define AM_REG_PDM_PCFG_PGARIGHT_P45DB 0x18000000
  164. #define AM_REG_PDM_PCFG_PGARIGHT_P30DB 0x10000000
  165. #define AM_REG_PDM_PCFG_PGARIGHT_P15DB 0x08000000
  166. #define AM_REG_PDM_PCFG_PGARIGHT_0DB 0x00000000
  167. // Left channel PGA gain.
  168. #define AM_REG_PDM_PCFG_PGALEFT_S 23
  169. #define AM_REG_PDM_PCFG_PGALEFT_M 0x07800000
  170. #define AM_REG_PDM_PCFG_PGALEFT(n) (((uint32_t)(n) << 23) & 0x07800000)
  171. #define AM_REG_PDM_PCFG_PGALEFT_M15DB 0x07800000
  172. #define AM_REG_PDM_PCFG_PGALEFT_M300DB 0x07000000
  173. #define AM_REG_PDM_PCFG_PGALEFT_M45DB 0x06800000
  174. #define AM_REG_PDM_PCFG_PGALEFT_M60DB 0x06000000
  175. #define AM_REG_PDM_PCFG_PGALEFT_M75DB 0x05800000
  176. #define AM_REG_PDM_PCFG_PGALEFT_M90DB 0x05000000
  177. #define AM_REG_PDM_PCFG_PGALEFT_M105DB 0x04800000
  178. #define AM_REG_PDM_PCFG_PGALEFT_M120DB 0x04000000
  179. #define AM_REG_PDM_PCFG_PGALEFT_P105DB 0x03800000
  180. #define AM_REG_PDM_PCFG_PGALEFT_P90DB 0x03000000
  181. #define AM_REG_PDM_PCFG_PGALEFT_P75DB 0x02800000
  182. #define AM_REG_PDM_PCFG_PGALEFT_P60DB 0x02000000
  183. #define AM_REG_PDM_PCFG_PGALEFT_P45DB 0x01800000
  184. #define AM_REG_PDM_PCFG_PGALEFT_P30DB 0x01000000
  185. #define AM_REG_PDM_PCFG_PGALEFT_P15DB 0x00800000
  186. #define AM_REG_PDM_PCFG_PGALEFT_0DB 0x00000000
  187. // PDM_CLK frequency divisor.
  188. #define AM_REG_PDM_PCFG_MCLKDIV_S 17
  189. #define AM_REG_PDM_PCFG_MCLKDIV_M 0x00060000
  190. #define AM_REG_PDM_PCFG_MCLKDIV(n) (((uint32_t)(n) << 17) & 0x00060000)
  191. #define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV4 0x00060000
  192. #define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV3 0x00040000
  193. #define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV2 0x00020000
  194. #define AM_REG_PDM_PCFG_MCLKDIV_MCKDIV1 0x00000000
  195. // SINC decimation rate.
  196. #define AM_REG_PDM_PCFG_SINCRATE_S 10
  197. #define AM_REG_PDM_PCFG_SINCRATE_M 0x0001FC00
  198. #define AM_REG_PDM_PCFG_SINCRATE(n) (((uint32_t)(n) << 10) & 0x0001FC00)
  199. // High pass filter control.
  200. #define AM_REG_PDM_PCFG_ADCHPD_S 9
  201. #define AM_REG_PDM_PCFG_ADCHPD_M 0x00000200
  202. #define AM_REG_PDM_PCFG_ADCHPD(n) (((uint32_t)(n) << 9) & 0x00000200)
  203. #define AM_REG_PDM_PCFG_ADCHPD_EN 0x00000200
  204. #define AM_REG_PDM_PCFG_ADCHPD_DIS 0x00000000
  205. // High pass filter coefficients.
  206. #define AM_REG_PDM_PCFG_HPCUTOFF_S 5
  207. #define AM_REG_PDM_PCFG_HPCUTOFF_M 0x000001E0
  208. #define AM_REG_PDM_PCFG_HPCUTOFF(n) (((uint32_t)(n) << 5) & 0x000001E0)
  209. // Number of clocks during gain-setting changes.
  210. #define AM_REG_PDM_PCFG_CYCLES_S 2
  211. #define AM_REG_PDM_PCFG_CYCLES_M 0x0000001C
  212. #define AM_REG_PDM_PCFG_CYCLES(n) (((uint32_t)(n) << 2) & 0x0000001C)
  213. // Soft mute control.
  214. #define AM_REG_PDM_PCFG_SOFTMUTE_S 1
  215. #define AM_REG_PDM_PCFG_SOFTMUTE_M 0x00000002
  216. #define AM_REG_PDM_PCFG_SOFTMUTE(n) (((uint32_t)(n) << 1) & 0x00000002)
  217. #define AM_REG_PDM_PCFG_SOFTMUTE_EN 0x00000002
  218. #define AM_REG_PDM_PCFG_SOFTMUTE_DIS 0x00000000
  219. // Data Streaming Control.
  220. #define AM_REG_PDM_PCFG_PDMCORE_S 0
  221. #define AM_REG_PDM_PCFG_PDMCORE_M 0x00000001
  222. #define AM_REG_PDM_PCFG_PDMCORE(n) (((uint32_t)(n) << 0) & 0x00000001)
  223. #define AM_REG_PDM_PCFG_PDMCORE_EN 0x00000001
  224. #define AM_REG_PDM_PCFG_PDMCORE_DIS 0x00000000
  225. //*****************************************************************************
  226. //
  227. // PDM_VCFG - Voice Configuration Register
  228. //
  229. //*****************************************************************************
  230. // Enable the IO clock.
  231. #define AM_REG_PDM_VCFG_IOCLKEN_S 31
  232. #define AM_REG_PDM_VCFG_IOCLKEN_M 0x80000000
  233. #define AM_REG_PDM_VCFG_IOCLKEN(n) (((uint32_t)(n) << 31) & 0x80000000)
  234. #define AM_REG_PDM_VCFG_IOCLKEN_DIS 0x00000000
  235. #define AM_REG_PDM_VCFG_IOCLKEN_EN 0x80000000
  236. // Reset the IP core.
  237. #define AM_REG_PDM_VCFG_RSTB_S 30
  238. #define AM_REG_PDM_VCFG_RSTB_M 0x40000000
  239. #define AM_REG_PDM_VCFG_RSTB(n) (((uint32_t)(n) << 30) & 0x40000000)
  240. #define AM_REG_PDM_VCFG_RSTB_RESET 0x00000000
  241. #define AM_REG_PDM_VCFG_RSTB_NORM 0x40000000
  242. // Select the PDM input clock.
  243. #define AM_REG_PDM_VCFG_PDMCLKSEL_S 27
  244. #define AM_REG_PDM_VCFG_PDMCLKSEL_M 0x38000000
  245. #define AM_REG_PDM_VCFG_PDMCLKSEL(n) (((uint32_t)(n) << 27) & 0x38000000)
  246. #define AM_REG_PDM_VCFG_PDMCLKSEL_DISABLE 0x00000000
  247. #define AM_REG_PDM_VCFG_PDMCLKSEL_12MHz 0x08000000
  248. #define AM_REG_PDM_VCFG_PDMCLKSEL_6MHz 0x10000000
  249. #define AM_REG_PDM_VCFG_PDMCLKSEL_3MHz 0x18000000
  250. #define AM_REG_PDM_VCFG_PDMCLKSEL_1_5MHz 0x20000000
  251. #define AM_REG_PDM_VCFG_PDMCLKSEL_750KHz 0x28000000
  252. #define AM_REG_PDM_VCFG_PDMCLKSEL_375KHz 0x30000000
  253. #define AM_REG_PDM_VCFG_PDMCLKSEL_187KHz 0x38000000
  254. // Enable the serial clock.
  255. #define AM_REG_PDM_VCFG_PDMCLK_S 26
  256. #define AM_REG_PDM_VCFG_PDMCLK_M 0x04000000
  257. #define AM_REG_PDM_VCFG_PDMCLK(n) (((uint32_t)(n) << 26) & 0x04000000)
  258. #define AM_REG_PDM_VCFG_PDMCLK_DIS 0x00000000
  259. #define AM_REG_PDM_VCFG_PDMCLK_EN 0x04000000
  260. // I2S interface enable.
  261. #define AM_REG_PDM_VCFG_I2SMODE_S 20
  262. #define AM_REG_PDM_VCFG_I2SMODE_M 0x00100000
  263. #define AM_REG_PDM_VCFG_I2SMODE(n) (((uint32_t)(n) << 20) & 0x00100000)
  264. #define AM_REG_PDM_VCFG_I2SMODE_DIS 0x00000000
  265. #define AM_REG_PDM_VCFG_I2SMODE_EN 0x00100000
  266. // I2S BCLK input inversion.
  267. #define AM_REG_PDM_VCFG_BCLKINV_S 19
  268. #define AM_REG_PDM_VCFG_BCLKINV_M 0x00080000
  269. #define AM_REG_PDM_VCFG_BCLKINV(n) (((uint32_t)(n) << 19) & 0x00080000)
  270. #define AM_REG_PDM_VCFG_BCLKINV_INV 0x00000000
  271. #define AM_REG_PDM_VCFG_BCLKINV_NORM 0x00080000
  272. // PDM clock sampling delay.
  273. #define AM_REG_PDM_VCFG_DMICKDEL_S 17
  274. #define AM_REG_PDM_VCFG_DMICKDEL_M 0x00020000
  275. #define AM_REG_PDM_VCFG_DMICKDEL(n) (((uint32_t)(n) << 17) & 0x00020000)
  276. #define AM_REG_PDM_VCFG_DMICKDEL_0CYC 0x00000000
  277. #define AM_REG_PDM_VCFG_DMICKDEL_1CYC 0x00020000
  278. // Select PDM input clock source.
  279. #define AM_REG_PDM_VCFG_SELAP_S 16
  280. #define AM_REG_PDM_VCFG_SELAP_M 0x00010000
  281. #define AM_REG_PDM_VCFG_SELAP(n) (((uint32_t)(n) << 16) & 0x00010000)
  282. #define AM_REG_PDM_VCFG_SELAP_I2S 0x00010000
  283. #define AM_REG_PDM_VCFG_SELAP_INTERNAL 0x00000000
  284. // PCM data packing enable.
  285. #define AM_REG_PDM_VCFG_PCMPACK_S 8
  286. #define AM_REG_PDM_VCFG_PCMPACK_M 0x00000100
  287. #define AM_REG_PDM_VCFG_PCMPACK(n) (((uint32_t)(n) << 8) & 0x00000100)
  288. #define AM_REG_PDM_VCFG_PCMPACK_DIS 0x00000000
  289. #define AM_REG_PDM_VCFG_PCMPACK_EN 0x00000100
  290. // Set PCM channels.
  291. #define AM_REG_PDM_VCFG_CHSET_S 3
  292. #define AM_REG_PDM_VCFG_CHSET_M 0x00000018
  293. #define AM_REG_PDM_VCFG_CHSET(n) (((uint32_t)(n) << 3) & 0x00000018)
  294. #define AM_REG_PDM_VCFG_CHSET_DIS 0x00000000
  295. #define AM_REG_PDM_VCFG_CHSET_LEFT 0x00000008
  296. #define AM_REG_PDM_VCFG_CHSET_RIGHT 0x00000010
  297. #define AM_REG_PDM_VCFG_CHSET_STEREO 0x00000018
  298. //*****************************************************************************
  299. //
  300. // PDM_FR - Voice Status Register
  301. //
  302. //*****************************************************************************
  303. // Valid 32-bit entries currently in the FIFO.
  304. #define AM_REG_PDM_FR_FIFOCNT_S 0
  305. #define AM_REG_PDM_FR_FIFOCNT_M 0x000001FF
  306. #define AM_REG_PDM_FR_FIFOCNT(n) (((uint32_t)(n) << 0) & 0x000001FF)
  307. //*****************************************************************************
  308. //
  309. // PDM_FRD - FIFO Read
  310. //
  311. //*****************************************************************************
  312. // FIFO read data.
  313. #define AM_REG_PDM_FRD_FIFOREAD_S 0
  314. #define AM_REG_PDM_FRD_FIFOREAD_M 0xFFFFFFFF
  315. #define AM_REG_PDM_FRD_FIFOREAD(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
  316. //*****************************************************************************
  317. //
  318. // PDM_FLUSH - FIFO Flush
  319. //
  320. //*****************************************************************************
  321. // FIFO FLUSH.
  322. #define AM_REG_PDM_FLUSH_FIFOFLUSH_S 0
  323. #define AM_REG_PDM_FLUSH_FIFOFLUSH_M 0x00000001
  324. #define AM_REG_PDM_FLUSH_FIFOFLUSH(n) (((uint32_t)(n) << 0) & 0x00000001)
  325. //*****************************************************************************
  326. //
  327. // PDM_FTHR - FIFO Threshold
  328. //
  329. //*****************************************************************************
  330. // FIFO interrupt threshold.
  331. #define AM_REG_PDM_FTHR_FIFOTHR_S 0
  332. #define AM_REG_PDM_FTHR_FIFOTHR_M 0x000000FF
  333. #define AM_REG_PDM_FTHR_FIFOTHR(n) (((uint32_t)(n) << 0) & 0x000000FF)
  334. #endif // AM_REG_PDM_H