at32f413_dma.h 25 KB

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  1. /**
  2. **************************************************************************
  3. * @file at32f413_dma.h
  4. * @version v2.0.5
  5. * @date 2022-05-20
  6. * @brief at32f413 dma header file
  7. **************************************************************************
  8. * Copyright notice & Disclaimer
  9. *
  10. * The software Board Support Package (BSP) that is made available to
  11. * download from Artery official website is the copyrighted work of Artery.
  12. * Artery authorizes customers to use, copy, and distribute the BSP
  13. * software and its related documentation for the purpose of design and
  14. * development in conjunction with Artery microcontrollers. Use of the
  15. * software is governed by this copyright notice and the following disclaimer.
  16. *
  17. * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18. * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19. * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20. * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21. * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23. *
  24. **************************************************************************
  25. */
  26. /* Define to prevent recursive inclusion -------------------------------------*/
  27. #ifndef __AT32F413_DMA_H
  28. #define __AT32F413_DMA_H
  29. #ifdef __cplusplus
  30. extern "C" {
  31. #endif
  32. /* Includes ------------------------------------------------------------------*/
  33. #include "at32f413.h"
  34. /** @addtogroup AT32F413_periph_driver
  35. * @{
  36. */
  37. /** @addtogroup DMA
  38. * @{
  39. */
  40. /** @defgroup DMA_interrupts_definition
  41. * @brief dma interrupt
  42. * @{
  43. */
  44. #define DMA_FDT_INT ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
  45. #define DMA_HDT_INT ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
  46. #define DMA_DTERR_INT ((uint32_t)0x00000008) /*!< dma errorr interrupt */
  47. /**
  48. * @}
  49. */
  50. /** @defgroup DMA_flexible_channel
  51. * @{
  52. */
  53. #define FLEX_CHANNEL1 ((uint8_t)0x01) /*!< dma flexible channel1 */
  54. #define FLEX_CHANNEL2 ((uint8_t)0x02) /*!< dma flexible channel2 */
  55. #define FLEX_CHANNEL3 ((uint8_t)0x03) /*!< dma flexible channel3 */
  56. #define FLEX_CHANNEL4 ((uint8_t)0x04) /*!< dma flexible channel4 */
  57. #define FLEX_CHANNEL5 ((uint8_t)0x05) /*!< dma flexible channel5 */
  58. #define FLEX_CHANNEL6 ((uint8_t)0x06) /*!< dma flexible channel6 */
  59. #define FLEX_CHANNEL7 ((uint8_t)0x07) /*!< dma flexible channel7 */
  60. /**
  61. * @}
  62. */
  63. /** @defgroup DMA_flags_definition
  64. * @brief dma flag
  65. * @{
  66. */
  67. #define DMA1_GL1_FLAG ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
  68. #define DMA1_FDT1_FLAG ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
  69. #define DMA1_HDT1_FLAG ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
  70. #define DMA1_DTERR1_FLAG ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
  71. #define DMA1_GL2_FLAG ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
  72. #define DMA1_FDT2_FLAG ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
  73. #define DMA1_HDT2_FLAG ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
  74. #define DMA1_DTERR2_FLAG ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
  75. #define DMA1_GL3_FLAG ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
  76. #define DMA1_FDT3_FLAG ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
  77. #define DMA1_HDT3_FLAG ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
  78. #define DMA1_DTERR3_FLAG ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
  79. #define DMA1_GL4_FLAG ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
  80. #define DMA1_FDT4_FLAG ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
  81. #define DMA1_HDT4_FLAG ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
  82. #define DMA1_DTERR4_FLAG ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
  83. #define DMA1_GL5_FLAG ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
  84. #define DMA1_FDT5_FLAG ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
  85. #define DMA1_HDT5_FLAG ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
  86. #define DMA1_DTERR5_FLAG ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
  87. #define DMA1_GL6_FLAG ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
  88. #define DMA1_FDT6_FLAG ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
  89. #define DMA1_HDT6_FLAG ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
  90. #define DMA1_DTERR6_FLAG ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
  91. #define DMA1_GL7_FLAG ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
  92. #define DMA1_FDT7_FLAG ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
  93. #define DMA1_HDT7_FLAG ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
  94. #define DMA1_DTERR7_FLAG ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
  95. #define DMA2_GL1_FLAG ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
  96. #define DMA2_FDT1_FLAG ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
  97. #define DMA2_HDT1_FLAG ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
  98. #define DMA2_DTERR1_FLAG ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
  99. #define DMA2_GL2_FLAG ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
  100. #define DMA2_FDT2_FLAG ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
  101. #define DMA2_HDT2_FLAG ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
  102. #define DMA2_DTERR2_FLAG ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
  103. #define DMA2_GL3_FLAG ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
  104. #define DMA2_FDT3_FLAG ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
  105. #define DMA2_HDT3_FLAG ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
  106. #define DMA2_DTERR3_FLAG ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
  107. #define DMA2_GL4_FLAG ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
  108. #define DMA2_FDT4_FLAG ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
  109. #define DMA2_HDT4_FLAG ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
  110. #define DMA2_DTERR4_FLAG ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
  111. #define DMA2_GL5_FLAG ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
  112. #define DMA2_FDT5_FLAG ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
  113. #define DMA2_HDT5_FLAG ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
  114. #define DMA2_DTERR5_FLAG ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
  115. #define DMA2_GL6_FLAG ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
  116. #define DMA2_FDT6_FLAG ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
  117. #define DMA2_HDT6_FLAG ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
  118. #define DMA2_DTERR6_FLAG ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
  119. #define DMA2_GL7_FLAG ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
  120. #define DMA2_FDT7_FLAG ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
  121. #define DMA2_HDT7_FLAG ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
  122. #define DMA2_DTERR7_FLAG ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
  123. /**
  124. * @}
  125. */
  126. /** @defgroup DMA_exported_types
  127. * @{
  128. */
  129. /**
  130. * @brief dma flexible request type
  131. */
  132. typedef enum
  133. {
  134. DMA_FLEXIBLE_ADC1 = 0x01, /*!< adc1 flexible request id */
  135. DMA_FLEXIBLE_SPI1_RX = 0x09, /*!< spi1_rx flexible request id */
  136. DMA_FLEXIBLE_SPI1_TX = 0x0A, /*!< spi1_tx flexible request id */
  137. DMA_FLEXIBLE_SPI2_RX = 0x0B, /*!< spi2_rx flexible request id */
  138. DMA_FLEXIBLE_SPI2_TX = 0x0C, /*!< spi2_tx flexible request id */
  139. DMA_FLEXIBLE_UART1_RX = 0x19, /*!< uart1_rx flexible request id */
  140. DMA_FLEXIBLE_UART1_TX = 0x1A, /*!< uart1_tx flexible request id */
  141. DMA_FLEXIBLE_UART2_RX = 0x1B, /*!< uart2_rx flexible request id */
  142. DMA_FLEXIBLE_UART2_TX = 0x1C, /*!< uart2_tx flexible request id */
  143. DMA_FLEXIBLE_UART3_RX = 0x1D, /*!< uart3_rx flexible request id */
  144. DMA_FLEXIBLE_UART3_TX = 0x1E, /*!< uart3_tx flexible request id */
  145. DMA_FLEXIBLE_UART4_RX = 0x1F, /*!< uart4_rx flexible request id */
  146. DMA_FLEXIBLE_UART4_TX = 0x20, /*!< uart4_tx flexible request id */
  147. DMA_FLEXIBLE_UART5_RX = 0x21, /*!< uart5_rx flexible request id */
  148. DMA_FLEXIBLE_UART5_TX = 0x22, /*!< uart5_tx flexible request id */
  149. DMA_FLEXIBLE_I2C1_RX = 0x29, /*!< i2c1_rx flexible request id */
  150. DMA_FLEXIBLE_I2C1_TX = 0x2A, /*!< i2c1_tx flexible request id */
  151. DMA_FLEXIBLE_I2C2_RX = 0x2B, /*!< i2c2_rx flexible request id */
  152. DMA_FLEXIBLE_I2C2_TX = 0x2C, /*!< i2c2_tx flexible request id */
  153. DMA_FLEXIBLE_SDIO1 = 0x31, /*!< sdio1 flexible request id */
  154. DMA_FLEXIBLE_TMR1_TRIG = 0x35, /*!< tmr1_trig flexible request id */
  155. DMA_FLEXIBLE_TMR1_HALL = 0x36, /*!< tmr1_hall flexible request id */
  156. DMA_FLEXIBLE_TMR1_OVERFLOW = 0x37, /*!< tmr1_overflow flexible request id */
  157. DMA_FLEXIBLE_TMR1_CH1 = 0x38, /*!< tmr1_ch1 flexible request id */
  158. DMA_FLEXIBLE_TMR1_CH2 = 0x39, /*!< tmr1_ch2 flexible request id */
  159. DMA_FLEXIBLE_TMR1_CH3 = 0x3A, /*!< tmr1_ch3 flexible request id */
  160. DMA_FLEXIBLE_TMR1_CH4 = 0x3B, /*!< tmr1_ch4 flexible request id */
  161. DMA_FLEXIBLE_TMR2_TRIG = 0x3D, /*!< tmr2_trig flexible request id */
  162. DMA_FLEXIBLE_TMR2_OVERFLOW = 0x3F, /*!< tmr2_overflow flexible request id */
  163. DMA_FLEXIBLE_TMR2_CH1 = 0x40, /*!< tmr2_ch1 flexible request id */
  164. DMA_FLEXIBLE_TMR2_CH2 = 0x41, /*!< tmr2_ch2 flexible request id */
  165. DMA_FLEXIBLE_TMR2_CH3 = 0x42, /*!< tmr2_ch3 flexible request id */
  166. DMA_FLEXIBLE_TMR2_CH4 = 0x43, /*!< tmr2_ch4 flexible request id */
  167. DMA_FLEXIBLE_TMR3_TRIG = 0x45, /*!< tmr3_trig flexible request id */
  168. DMA_FLEXIBLE_TMR3_OVERFLOW = 0x47, /*!< tmr3_overflow flexible request id */
  169. DMA_FLEXIBLE_TMR3_CH1 = 0x48, /*!< tmr3_ch1 flexible request id */
  170. DMA_FLEXIBLE_TMR3_CH2 = 0x49, /*!< tmr3_ch2 flexible request id */
  171. DMA_FLEXIBLE_TMR3_CH3 = 0x4A, /*!< tmr3_ch3 flexible request id */
  172. DMA_FLEXIBLE_TMR3_CH4 = 0x4B, /*!< tmr3_ch4 flexible request id */
  173. DMA_FLEXIBLE_TMR4_TRIG = 0x4D, /*!< tmr4_trig flexible request id */
  174. DMA_FLEXIBLE_TMR4_OVERFLOW = 0x4F, /*!< tmr4_overflow flexible request id */
  175. DMA_FLEXIBLE_TMR4_CH1 = 0x50, /*!< tmr4_ch1 flexible request id */
  176. DMA_FLEXIBLE_TMR4_CH2 = 0x51, /*!< tmr4_ch2 flexible request id */
  177. DMA_FLEXIBLE_TMR4_CH3 = 0x52, /*!< tmr4_ch3 flexible request id */
  178. DMA_FLEXIBLE_TMR4_CH4 = 0x53, /*!< tmr4_ch4 flexible request id */
  179. DMA_FLEXIBLE_TMR5_TRIG = 0x55, /*!< tmr5_trig flexible request id */
  180. DMA_FLEXIBLE_TMR5_OVERFLOW = 0x57, /*!< tmr5_overflow flexible request id */
  181. DMA_FLEXIBLE_TMR5_CH1 = 0x58, /*!< tmr5_ch1 flexible request id */
  182. DMA_FLEXIBLE_TMR5_CH2 = 0x59, /*!< tmr5_ch2 flexible request id */
  183. DMA_FLEXIBLE_TMR5_CH3 = 0x5A, /*!< tmr5_ch3 flexible request id */
  184. DMA_FLEXIBLE_TMR5_CH4 = 0x5B, /*!< tmr5_ch4 flexible request id */
  185. DMA_FLEXIBLE_TMR8_TRIG = 0x6D, /*!< tmr8_trig flexible request id */
  186. DMA_FLEXIBLE_TMR8_HALL = 0x6E, /*!< tmr8_hall flexible request id */
  187. DMA_FLEXIBLE_TMR8_OVERFLOW = 0x6F, /*!< tmr8_overflow flexible request id */
  188. DMA_FLEXIBLE_TMR8_CH1 = 0x70, /*!< tmr8_ch1 flexible request id */
  189. DMA_FLEXIBLE_TMR8_CH2 = 0x71, /*!< tmr8_ch2 flexible request id */
  190. DMA_FLEXIBLE_TMR8_CH3 = 0x72, /*!< tmr8_ch3 flexible request id */
  191. DMA_FLEXIBLE_TMR8_CH4 = 0x73, /*!< tmr8_ch4 flexible request id */
  192. } dma_flexible_request_type;
  193. /**
  194. * @brief dma direction type
  195. */
  196. typedef enum
  197. {
  198. DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction:peripheral to memory */
  199. DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction:memory to peripheral */
  200. DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction:memory to memory */
  201. } dma_dir_type;
  202. /**
  203. * @brief dma peripheral incremented type
  204. */
  205. typedef enum
  206. {
  207. DMA_PERIPHERAL_INC_DISABLE = 0x00, /*!< dma peripheral increment mode disable */
  208. DMA_PERIPHERAL_INC_ENABLE = 0x01 /*!< dma peripheral increment mode enable */
  209. } dma_peripheral_inc_type;
  210. /**
  211. * @brief dma memory incremented type
  212. */
  213. typedef enum
  214. {
  215. DMA_MEMORY_INC_DISABLE = 0x00, /*!< dma memory increment mode disable */
  216. DMA_MEMORY_INC_ENABLE = 0x01 /*!< dma memory increment mode enable */
  217. } dma_memory_inc_type;
  218. /**
  219. * @brief dma peripheral data size type
  220. */
  221. typedef enum
  222. {
  223. DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< dma peripheral databus width 8bit */
  224. DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< dma peripheral databus width 16bit */
  225. DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< dma peripheral databus width 32bit */
  226. } dma_peripheral_data_size_type;
  227. /**
  228. * @brief dma memory data size type
  229. */
  230. typedef enum
  231. {
  232. DMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< dma memory databus width 8bit */
  233. DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< dma memory databus width 16bit */
  234. DMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< dma memory databus width 32bit */
  235. } dma_memory_data_size_type;
  236. /**
  237. * @brief dma priority level type
  238. */
  239. typedef enum
  240. {
  241. DMA_PRIORITY_LOW = 0x00, /*!< dma channel priority: low */
  242. DMA_PRIORITY_MEDIUM = 0x01, /*!< dma channel priority: mediue */
  243. DMA_PRIORITY_HIGH = 0x02, /*!< dma channel priority: high */
  244. DMA_PRIORITY_VERY_HIGH = 0x03 /*!< dma channel priority: very high */
  245. } dma_priority_level_type;
  246. /**
  247. * @brief dma init type
  248. */
  249. typedef struct
  250. {
  251. uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
  252. uint32_t memory_base_addr; /*!< base addrress for memory */
  253. dma_dir_type direction; /*!< dma transmit direction, peripheral as source or as destnation */
  254. uint16_t buffer_size; /*!< counter to transfer */
  255. confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
  256. confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
  257. dma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
  258. dma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
  259. confirm_state loop_mode_enable; /*!< when circular mode enable, buffer size will reload if count to 0 */
  260. dma_priority_level_type priority; /*!< dma priority can choose from very high, high, dedium or low */
  261. } dma_init_type;
  262. /**
  263. * @brief type define dma register
  264. */
  265. typedef struct
  266. {
  267. /**
  268. * @brief dma sts register, offset:0x00
  269. */
  270. union
  271. {
  272. __IO uint32_t sts;
  273. struct
  274. {
  275. __IO uint32_t gf1 : 1; /* [0] */
  276. __IO uint32_t fdtf1 : 1; /* [1] */
  277. __IO uint32_t hdtf1 : 1; /* [2] */
  278. __IO uint32_t dterrf1 : 1; /* [3] */
  279. __IO uint32_t gf2 : 1; /* [4] */
  280. __IO uint32_t fdtf2 : 1; /* [5] */
  281. __IO uint32_t hdtf2 : 1; /* [6] */
  282. __IO uint32_t dterrf2 : 1; /* [7] */
  283. __IO uint32_t gf3 : 1; /* [8] */
  284. __IO uint32_t fdtf3 : 1; /* [9] */
  285. __IO uint32_t hdtf3 : 1; /* [10] */
  286. __IO uint32_t dterrf3 : 1; /* [11] */
  287. __IO uint32_t gf4 : 1; /* [12] */
  288. __IO uint32_t fdtf4 : 1; /* [13] */
  289. __IO uint32_t hdtf4 : 1; /* [14] */
  290. __IO uint32_t dterrf4 : 1; /* [15] */
  291. __IO uint32_t gf5 : 1; /* [16] */
  292. __IO uint32_t fdtf5 : 1; /* [17] */
  293. __IO uint32_t hdtf5 : 1; /* [18] */
  294. __IO uint32_t dterrf5 : 1; /* [19] */
  295. __IO uint32_t gf6 : 1; /* [20] */
  296. __IO uint32_t fdtf6 : 1; /* [21] */
  297. __IO uint32_t hdtf6 : 1; /* [22] */
  298. __IO uint32_t dterrf6 : 1; /* [23] */
  299. __IO uint32_t gf7 : 1; /* [24] */
  300. __IO uint32_t fdtf7 : 1; /* [25] */
  301. __IO uint32_t hdtf7 : 1; /* [26] */
  302. __IO uint32_t dterrf7 : 1; /* [27] */
  303. __IO uint32_t reserved1 : 4; /* [31:28] */
  304. } sts_bit;
  305. };
  306. /**
  307. * @brief dma clr register, offset:0x04
  308. */
  309. union
  310. {
  311. __IO uint32_t clr;
  312. struct
  313. {
  314. __IO uint32_t gfc1 : 1; /* [0] */
  315. __IO uint32_t fdtfc1 : 1; /* [1] */
  316. __IO uint32_t hdtfc1 : 1; /* [2] */
  317. __IO uint32_t dterrfc1 : 1; /* [3] */
  318. __IO uint32_t gfc2 : 1; /* [4] */
  319. __IO uint32_t fdtfc2 : 1; /* [5] */
  320. __IO uint32_t hdtfc2 : 1; /* [6] */
  321. __IO uint32_t dterrfc2 : 1; /* [7] */
  322. __IO uint32_t gfc3 : 1; /* [8] */
  323. __IO uint32_t fdtfc3 : 1; /* [9] */
  324. __IO uint32_t hdtfc3 : 1; /* [10] */
  325. __IO uint32_t dterrfc3 : 1; /* [11] */
  326. __IO uint32_t gfc4 : 1; /* [12] */
  327. __IO uint32_t fdtfc4 : 1; /* [13] */
  328. __IO uint32_t hdtfc4 : 1; /* [14] */
  329. __IO uint32_t dterrfc4 : 1; /* [15] */
  330. __IO uint32_t gfc5 : 1; /* [16] */
  331. __IO uint32_t fdtfc5 : 1; /* [17] */
  332. __IO uint32_t hdtfc5 : 1; /* [18] */
  333. __IO uint32_t dterrfc5 : 1; /* [19] */
  334. __IO uint32_t gfc6 : 1; /* [20] */
  335. __IO uint32_t fdtfc6 : 1; /* [21] */
  336. __IO uint32_t hdtfc6 : 1; /* [22] */
  337. __IO uint32_t dterrfc6 : 1; /* [23] */
  338. __IO uint32_t gfc7 : 1; /* [24] */
  339. __IO uint32_t fdtfc7 : 1; /* [25] */
  340. __IO uint32_t hdtfc7 : 1; /* [26] */
  341. __IO uint32_t dterrfc7 : 1; /* [27] */
  342. __IO uint32_t reserved1 : 4; /* [31:28] */
  343. } clr_bit;
  344. };
  345. /**
  346. * @brief reserved, offset:0x08~0x9C
  347. */
  348. __IO uint32_t reserved1[38];
  349. /**
  350. * @brief dma src_sel0 register, offset:0xA0
  351. */
  352. union
  353. {
  354. __IO uint32_t src_sel0;
  355. struct
  356. {
  357. __IO uint32_t ch1_src : 8; /* [7:0] */
  358. __IO uint32_t ch2_src : 8; /* [15:8] */
  359. __IO uint32_t ch3_src : 8; /* [23:16] */
  360. __IO uint32_t ch4_src : 8; /* [31:24] */
  361. } src_sel0_bit;
  362. };
  363. /**
  364. * @brief dma src_sel1 register, offset:0xA4
  365. */
  366. union
  367. {
  368. __IO uint32_t src_sel1;
  369. struct
  370. {
  371. __IO uint32_t ch5_src : 8; /* [7:0] */
  372. __IO uint32_t ch6_src : 8; /* [15:8] */
  373. __IO uint32_t ch7_src : 8; /* [23:16] */
  374. __IO uint32_t dma_flex_en : 1; /* [24] */
  375. __IO uint32_t reserved1 : 7; /* [31:25] */
  376. } src_sel1_bit;
  377. };
  378. } dma_type;
  379. /**
  380. * @brief type define dma channel register all
  381. */
  382. typedef struct
  383. {
  384. /**
  385. * @brief dma ctrl register, offset:0x08+20*(x-1) x=1...7
  386. */
  387. union
  388. {
  389. __IO uint32_t ctrl;
  390. struct
  391. {
  392. __IO uint32_t chen : 1; /* [0] */
  393. __IO uint32_t fdtien : 1; /* [1] */
  394. __IO uint32_t hdtien : 1; /* [2] */
  395. __IO uint32_t dterrien : 1; /* [3] */
  396. __IO uint32_t dtd : 1; /* [4] */
  397. __IO uint32_t lm : 1; /* [5] */
  398. __IO uint32_t pincm : 1; /* [6] */
  399. __IO uint32_t mincm : 1; /* [7] */
  400. __IO uint32_t pwidth : 2; /* [9:8] */
  401. __IO uint32_t mwidth : 2; /* [11:10] */
  402. __IO uint32_t chpl : 2; /* [13:12] */
  403. __IO uint32_t m2m : 1; /* [14] */
  404. __IO uint32_t reserved1 : 17;/* [31:15] */
  405. } ctrl_bit;
  406. };
  407. /**
  408. * @brief dma dtcnt register, offset:0x0C+20*(x-1) x=1...7
  409. */
  410. union
  411. {
  412. __IO uint32_t dtcnt;
  413. struct
  414. {
  415. __IO uint32_t cnt : 16;/* [15:0] */
  416. __IO uint32_t reserved1 : 16;/* [31:16] */
  417. } dtcnt_bit;
  418. };
  419. /**
  420. * @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
  421. */
  422. union
  423. {
  424. __IO uint32_t paddr;
  425. struct
  426. {
  427. __IO uint32_t paddr : 32;/* [31:0] */
  428. } paddr_bit;
  429. };
  430. /**
  431. * @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
  432. */
  433. union
  434. {
  435. __IO uint32_t maddr;
  436. struct
  437. {
  438. __IO uint32_t maddr : 32;/* [31:0] */
  439. } maddr_bit;
  440. };
  441. } dma_channel_type;
  442. /**
  443. * @}
  444. */
  445. #define DMA1 ((dma_type *) DMA1_BASE)
  446. #define DMA1_CHANNEL1 ((dma_channel_type *) DMA1_CHANNEL1_BASE)
  447. #define DMA1_CHANNEL2 ((dma_channel_type *) DMA1_CHANNEL2_BASE)
  448. #define DMA1_CHANNEL3 ((dma_channel_type *) DMA1_CHANNEL3_BASE)
  449. #define DMA1_CHANNEL4 ((dma_channel_type *) DMA1_CHANNEL4_BASE)
  450. #define DMA1_CHANNEL5 ((dma_channel_type *) DMA1_CHANNEL5_BASE)
  451. #define DMA1_CHANNEL6 ((dma_channel_type *) DMA1_CHANNEL6_BASE)
  452. #define DMA1_CHANNEL7 ((dma_channel_type *) DMA1_CHANNEL7_BASE)
  453. #define DMA2 ((dma_type *) DMA2_BASE)
  454. #define DMA2_CHANNEL1 ((dma_channel_type *) DMA2_CHANNEL1_BASE)
  455. #define DMA2_CHANNEL2 ((dma_channel_type *) DMA2_CHANNEL2_BASE)
  456. #define DMA2_CHANNEL3 ((dma_channel_type *) DMA2_CHANNEL3_BASE)
  457. #define DMA2_CHANNEL4 ((dma_channel_type *) DMA2_CHANNEL4_BASE)
  458. #define DMA2_CHANNEL5 ((dma_channel_type *) DMA2_CHANNEL5_BASE)
  459. #define DMA2_CHANNEL6 ((dma_channel_type *) DMA2_CHANNEL6_BASE)
  460. #define DMA2_CHANNEL7 ((dma_channel_type *) DMA2_CHANNEL7_BASE)
  461. /** @defgroup DMA_exported_functions
  462. * @{
  463. */
  464. void dma_reset(dma_channel_type* dmax_channely);
  465. void dma_default_para_init(dma_init_type* dma_init_struct);
  466. void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);
  467. void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
  468. void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request);
  469. void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number);
  470. uint16_t dma_data_number_get(dma_channel_type* dmax_channely);
  471. void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state);
  472. flag_status dma_flag_get(uint32_t dmax_flag);
  473. void dma_flag_clear(uint32_t dmax_flag);
  474. /**
  475. * @}
  476. */
  477. /**
  478. * @}
  479. */
  480. /**
  481. * @}
  482. */
  483. #ifdef __cplusplus
  484. }
  485. #endif
  486. #endif