psc.h 2.7 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2010-11-13 weety first version
  9. */
  10. #ifndef __DM36X_PSC_H
  11. #define __DM36X_PSC_H
  12. #ifdef __cplusplus
  13. extern "C" {
  14. #endif
  15. /* PSC register offsets */
  16. #define EPCPR 0x070
  17. #define PTCMD 0x120
  18. #define PTSTAT 0x128
  19. #define PDSTAT 0x200
  20. #define PDCTL1 0x304
  21. #define MDSTAT(n) (0x800 + (n) * 4)
  22. #define MDCTL(n) (0xA00 + (n) * 4)
  23. /* Power and Sleep Controller (PSC) Domains */
  24. #define DAVINCI_GPSC_ARMDOMAIN 0
  25. #define DAVINCI_GPSC_DSPDOMAIN 1
  26. #define DAVINCI_DM365_LPSC_TPCC 0
  27. #define DAVINCI_DM365_LPSC_TPTC0 1
  28. #define DAVINCI_DM365_LPSC_TPTC1 2
  29. #define DAVINCI_DM365_LPSC_TPTC2 3
  30. #define DAVINCI_DM365_LPSC_TPTC3 4
  31. #define DAVINCI_DM365_LPSC_TIMER3 5
  32. #define DAVINCI_DM365_LPSC_SPI1 6
  33. #define DAVINCI_DM365_LPSC_MMC_SD1 7
  34. #define DAVINCI_DM365_LPSC_McBSP 8
  35. #define DAVINCI_DM365_LPSC_USB 9
  36. #define DAVINCI_DM365_LPSC_PWM3 10
  37. #define DAVINCI_DM365_LPSC_SPI2 11
  38. #define DAVINCI_DM365_LPSC_RTO 12
  39. #define DAVINCI_DM365_LPSC_DDR_EMIF 13
  40. #define DAVINCI_DM365_LPSC_AEMIF 14
  41. #define DAVINCI_DM365_LPSC_MMC_SD 15
  42. #define DAVINCI_DM365_LPSC_MMC_SD0 15
  43. #define DAVINCI_DM365_LPSC_MEMSTICK 16
  44. #define DAVINCI_DM365_LPSC_TIMER4 17
  45. #define DAVINCI_DM365_LPSC_I2C 18
  46. #define DAVINCI_DM365_LPSC_UART0 19
  47. #define DAVINCI_DM365_LPSC_UART1 20
  48. #define DAVINCI_DM365_LPSC_UHPI 21
  49. #define DAVINCI_DM365_LPSC_SPI0 22
  50. #define DAVINCI_DM365_LPSC_PWM0 23
  51. #define DAVINCI_DM365_LPSC_PWM1 24
  52. #define DAVINCI_DM365_LPSC_PWM2 25
  53. #define DAVINCI_DM365_LPSC_GPIO 26
  54. #define DAVINCI_DM365_LPSC_TIMER0 27
  55. #define DAVINCI_DM365_LPSC_TIMER1 28
  56. #define DAVINCI_DM365_LPSC_TIMER2 29
  57. #define DAVINCI_DM365_LPSC_SYSTEM_SUBSYS 30
  58. #define DAVINCI_DM365_LPSC_ARM 31
  59. #define DAVINCI_DM365_LPSC_SCR0 33
  60. #define DAVINCI_DM365_LPSC_SCR1 34
  61. #define DAVINCI_DM365_LPSC_EMU 35
  62. #define DAVINCI_DM365_LPSC_CHIPDFT 36
  63. #define DAVINCI_DM365_LPSC_PBIST 37
  64. #define DAVINCI_DM365_LPSC_SPI3 38
  65. #define DAVINCI_DM365_LPSC_SPI4 39
  66. #define DAVINCI_DM365_LPSC_CPGMAC 40
  67. #define DAVINCI_DM365_LPSC_RTC 41
  68. #define DAVINCI_DM365_LPSC_KEYSCAN 42
  69. #define DAVINCI_DM365_LPSC_ADCIF 43
  70. #define DAVINCI_DM365_LPSC_VOICE_CODEC 44
  71. #define DAVINCI_DM365_LPSC_DAC_CLKRES 45
  72. #define DAVINCI_DM365_LPSC_DAC_CLK 46
  73. #define DAVINCI_DM365_LPSC_VPSSMSTR 47
  74. #define DAVINCI_DM365_LPSC_IMCOP 50
  75. #define DAVINCI_DM365_LPSC_KALEIDO 51
  76. #define PSC_ENABLE 3
  77. #define PSC_DISABLE 2
  78. #define PSC_SYNCRESET 1
  79. #define PSC_RESET 0
  80. void psc_change_state(int id, int state);
  81. #ifdef __cplusplus
  82. }
  83. #endif
  84. #endif