drv_usart.c 9.5 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-08-23 lianzhian first implementation.
  9. */
  10. #include <rtthread.h>
  11. #include <gd32f10x.h>
  12. #include <drv_usart.h>
  13. #include <board.h>
  14. #ifdef RT_USING_SERIAL
  15. #define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n))
  16. #define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n))
  17. #if !defined(RT_USING_USART0) && !defined(RT_USING_USART1) && \
  18. !defined(RT_USING_USART2) && !defined(RT_USING_UART3) && \
  19. !defined(RT_USING_UART4)
  20. #error "Please define at least one UARTx"
  21. #endif
  22. #include <rtdevice.h>
  23. /* GD32 uart driver */
  24. /* Todo: compress uart info */
  25. struct gd32_uart
  26. {
  27. uint32_t uart_periph;
  28. IRQn_Type irqn;
  29. rcu_periph_enum per_clk;
  30. rcu_periph_enum tx_gpio_clk;
  31. rcu_periph_enum rx_gpio_clk;
  32. uint32_t tx_port;
  33. uint16_t tx_pin;
  34. uint32_t rx_port;
  35. uint16_t rx_pin;
  36. struct rt_serial_device * serial;
  37. char *device_name;
  38. };
  39. static void uart_isr(struct rt_serial_device *serial);
  40. #if defined(RT_USING_USART0)
  41. struct rt_serial_device serial0;
  42. void USART0_IRQHandler(void)
  43. {
  44. /* enter interrupt */
  45. rt_interrupt_enter();
  46. uart_isr(&serial0);
  47. /* leave interrupt */
  48. rt_interrupt_leave();
  49. }
  50. #endif /* RT_USING_USART0 */
  51. #if defined(RT_USING_USART1)
  52. struct rt_serial_device serial1;
  53. void USART1_IRQHandler(void)
  54. {
  55. /* enter interrupt */
  56. rt_interrupt_enter();
  57. uart_isr(&serial1);
  58. /* leave interrupt */
  59. rt_interrupt_leave();
  60. }
  61. #endif /* RT_USING_UART1 */
  62. #if defined(RT_USING_USART2)
  63. struct rt_serial_device serial2;
  64. void USART2_IRQHandler(void)
  65. {
  66. /* enter interrupt */
  67. rt_interrupt_enter();
  68. uart_isr(&serial2);
  69. /* leave interrupt */
  70. rt_interrupt_leave();
  71. }
  72. #endif /* RT_USING_UART2 */
  73. #if defined(RT_USING_UART3)
  74. struct rt_serial_device serial3;
  75. void UART3_IRQHandler(void)
  76. {
  77. /* enter interrupt */
  78. rt_interrupt_enter();
  79. uart_isr(&serial3);
  80. /* leave interrupt */
  81. rt_interrupt_leave();
  82. }
  83. #endif /* RT_USING_UART3 */
  84. #if defined(RT_USING_UART4)
  85. struct rt_serial_device serial4;
  86. void UART4_IRQHandler(void)
  87. {
  88. /* enter interrupt */
  89. rt_interrupt_enter();
  90. uart_isr(&serial4);
  91. /* leave interrupt */
  92. rt_interrupt_leave();
  93. }
  94. #endif /* RT_USING_UART4 */
  95. static const struct gd32_uart uarts[] = {
  96. #ifdef RT_USING_USART0
  97. {
  98. USART0, /* uart peripheral index */
  99. USART0_IRQn, /* uart iqrn */
  100. RCU_USART0, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */
  101. GPIOA, GPIO_PIN_9, /* tx port, tx pin */
  102. GPIOA, GPIO_PIN_10, /* rx port, rx pin */
  103. &serial0,
  104. "uart0",
  105. },
  106. #endif
  107. #ifdef RT_USING_USART1
  108. {
  109. USART1, /* uart peripheral index */
  110. USART1_IRQn, /* uart iqrn */
  111. RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */
  112. GPIOA, GPIO_PIN_2, /* tx port, tx pin */
  113. GPIOA, GPIO_PIN_3, /* rx port, rx pin */
  114. &serial1,
  115. "uart1",
  116. },
  117. #endif
  118. #ifdef RT_USING_USART2
  119. {
  120. USART2, /* uart peripheral index */
  121. USART2_IRQn, /* uart iqrn */
  122. RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */
  123. GPIOB, GPIO_PIN_10, /* tx port, tx alternate, tx pin */
  124. GPIOB, GPIO_PIN_11, /* rx port, rx alternate, rx pin */
  125. &serial2,
  126. "uart2",
  127. },
  128. #endif
  129. #ifdef RT_USING_UART3
  130. {
  131. UART3, /* uart peripheral index */
  132. UART3_IRQn, /* uart iqrn */
  133. RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */
  134. GPIOC, GPIO_PIN_10, /* tx port, tx alternate, tx pin */
  135. GPIOC, GPIO_PIN_11, /* rx port, rx alternate, rx pin */
  136. &serial3,
  137. "uart3",
  138. },
  139. #endif
  140. #ifdef RT_USING_UART4
  141. {
  142. UART4, /* uart peripheral index */
  143. UART4_IRQn, /* uart iqrn */
  144. RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */
  145. GPIOC, GPIO_PIN_12, /* tx port, tx alternate, tx pin */
  146. GPIOD, GPIO_PIN_2, /* rx port, rx alternate, rx pin */
  147. &serial4,
  148. "uart4",
  149. },
  150. #endif
  151. };
  152. /**
  153. * @brief UART MSP Initialization
  154. * This function configures the hardware resources used in this example:
  155. * - Peripheral's clock enable
  156. * - Peripheral's GPIO Configuration
  157. * - NVIC configuration for UART interrupt request enable
  158. * @param uart: UART handle pointer
  159. * @retval None
  160. */
  161. void gd32_uart_gpio_init(struct gd32_uart *uart)
  162. {
  163. /* enable USART clock */
  164. rcu_periph_clock_enable(uart->tx_gpio_clk);
  165. rcu_periph_clock_enable(uart->rx_gpio_clk);
  166. rcu_periph_clock_enable(uart->per_clk);
  167. /* connect port to USARTx_Tx */
  168. gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin);
  169. /* connect port to USARTx_Rx */
  170. gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin);
  171. NVIC_SetPriority(uart->irqn, 0);
  172. NVIC_EnableIRQ(uart->irqn);
  173. }
  174. static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  175. {
  176. struct gd32_uart *uart;
  177. RT_ASSERT(serial != RT_NULL);
  178. RT_ASSERT(cfg != RT_NULL);
  179. uart = (struct gd32_uart *)serial->parent.user_data;
  180. gd32_uart_gpio_init(uart);
  181. usart_baudrate_set(uart->uart_periph, cfg->baud_rate);
  182. switch (cfg->data_bits)
  183. {
  184. case DATA_BITS_9:
  185. usart_word_length_set(uart->uart_periph, USART_WL_9BIT);
  186. break;
  187. default:
  188. usart_word_length_set(uart->uart_periph, USART_WL_8BIT);
  189. break;
  190. }
  191. switch (cfg->stop_bits)
  192. {
  193. case STOP_BITS_2:
  194. usart_stop_bit_set(uart->uart_periph, USART_STB_2BIT);
  195. break;
  196. default:
  197. usart_stop_bit_set(uart->uart_periph, USART_STB_1BIT);
  198. break;
  199. }
  200. switch (cfg->parity)
  201. {
  202. case PARITY_ODD:
  203. usart_parity_config(uart->uart_periph, USART_PM_ODD);
  204. break;
  205. case PARITY_EVEN:
  206. usart_parity_config(uart->uart_periph, USART_PM_EVEN);
  207. break;
  208. default:
  209. usart_parity_config(uart->uart_periph, USART_PM_NONE);
  210. break;
  211. }
  212. usart_receive_config(uart->uart_periph, USART_RECEIVE_ENABLE);
  213. usart_transmit_config(uart->uart_periph, USART_TRANSMIT_ENABLE);
  214. usart_enable(uart->uart_periph);
  215. return RT_EOK;
  216. }
  217. static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  218. {
  219. struct gd32_uart *uart;
  220. RT_ASSERT(serial != RT_NULL);
  221. uart = (struct gd32_uart *)serial->parent.user_data;
  222. switch (cmd)
  223. {
  224. case RT_DEVICE_CTRL_CLR_INT:
  225. /* disable rx irq */
  226. NVIC_DisableIRQ(uart->irqn);
  227. /* disable interrupt */
  228. usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE);
  229. break;
  230. case RT_DEVICE_CTRL_SET_INT:
  231. /* enable rx irq */
  232. NVIC_EnableIRQ(uart->irqn);
  233. /* enable interrupt */
  234. usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE);
  235. break;
  236. }
  237. return RT_EOK;
  238. }
  239. static int _uart_putc(struct rt_serial_device *serial, char ch)
  240. {
  241. struct gd32_uart *uart;
  242. RT_ASSERT(serial != RT_NULL);
  243. uart = (struct gd32_uart *)serial->parent.user_data;
  244. usart_data_transmit(uart->uart_periph, ch);
  245. while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
  246. return 1;
  247. }
  248. static int _uart_getc(struct rt_serial_device *serial)
  249. {
  250. int ch;
  251. struct gd32_uart *uart;
  252. RT_ASSERT(serial != RT_NULL);
  253. uart = (struct gd32_uart *)serial->parent.user_data;
  254. ch = -1;
  255. if (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)
  256. ch = usart_data_receive(uart->uart_periph);
  257. return ch;
  258. }
  259. /**
  260. * Uart common interrupt process. This need add to uart ISR.
  261. *
  262. * @param serial serial device
  263. */
  264. static void uart_isr(struct rt_serial_device *serial)
  265. {
  266. struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data;
  267. RT_ASSERT(uart != RT_NULL);
  268. /* UART in mode Receiver */
  269. if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) &&
  270. (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET))
  271. {
  272. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  273. /* Clear RXNE interrupt flag */
  274. usart_flag_clear(uart->uart_periph, USART_FLAG_RBNE);
  275. }
  276. }
  277. static const struct rt_uart_ops gd32_uart_ops =
  278. {
  279. _uart_configure,
  280. _uart_control,
  281. _uart_putc,
  282. _uart_getc
  283. };
  284. int gd32_hw_usart_init(void)
  285. {
  286. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  287. int i;
  288. for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
  289. {
  290. uarts[i].serial->ops = &gd32_uart_ops;
  291. uarts[i].serial->config = config;
  292. /* register UART device */
  293. rt_hw_serial_register(uarts[i].serial,
  294. uarts[i].device_name,
  295. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  296. (void *)&uarts[i]);
  297. }
  298. return 0;
  299. }
  300. INIT_BOARD_EXPORT(gd32_hw_usart_init);
  301. #endif