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GD32F30x_standard_peripheral
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gd32f30x_fmc.h

gd32f30x_fmc.h 21 KB
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  1. /*!
    2. 

  2.     \file  gd32f30x_fmc.h
    3. 

  3.     \brief definitions for the FMC
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2017 GigaDevice
    8. 

  8. 

  9.     2017-02-10, V1.0.1, firmware for GD32F30x
    10. 

  10. */
    11. 

  11. 

  12. #ifndef GD32F30X_FMC_H
    13. 

  13. #define GD32F30X_FMC_H
    14. 

  14. 

  15. #include "gd32f30x.h"
    16. 

  16. 

  17. /* FMC and option byte definition */
    18. 

  18. #define FMC                        FMC_BASE                       /*!< FMC register base address */
    19. 

  19. #define OB                         OB_BASE                        /*!< option bytes base address */
    20. 

  20. 

  21. /* registers definitions */
    22. 

  22. #define FMC_WS                     REG32((FMC) + 0x00U)           /*!< FMC wait state register */
    23. 

  23. #define FMC_KEY0                   REG32((FMC) + 0x04U)           /*!< FMC unlock key register 0 */
    24. 

  24. #define FMC_OBKEY                  REG32((FMC) + 0x08U)           /*!< FMC option bytes unlock key register */
    25. 

  25. #define FMC_STAT0                  REG32((FMC) + 0x0CU)           /*!< FMC status register 0 */
    26. 

  26. #define FMC_CTL0                   REG32((FMC) + 0x10U)           /*!< FMC control register 0 */
    27. 

  27. #define FMC_ADDR0                  REG32((FMC) + 0x14U)           /*!< FMC address register 0 */
    28. 

  28. #define FMC_OBSTAT                 REG32((FMC) + 0x1CU)           /*!< FMC option bytes status register */
    29. 

  29. #define FMC_WP                     REG32((FMC) + 0x20U)           /*!< FMC erase/program protection register */
    30. 

  30. #define FMC_KEY1                   REG32((FMC) + 0x44U)           /*!< FMC unlock key register 1 */
    31. 

  31. #define FMC_STAT1                  REG32((FMC) + 0x4CU)           /*!< FMC status register 1 */
    32. 

  32. #define FMC_CTL1                   REG32((FMC) + 0x50U)           /*!< FMC control register 1 */
    33. 

  33. #define FMC_ADDR1                  REG32((FMC) + 0x54U)           /*!< FMC address register 1 */
    34. 

  34. #define FMC_WSEN                   REG32((FMC) + 0xFCU)           /*!< FMC wait state enable register */
    35. 

  35. #define FMC_PID                    REG32((FMC) + 0x100U)          /*!< FMC product ID register */
    36. 

  36. 

  37. #define OB_SPC                     REG16((OB) + 0x00U)            /*!< option byte security protection value */
    38. 

  38. #define OB_USER                    REG16((OB) + 0x02U)            /*!< option byte user value*/
    39. 

  39. #define OB_WP0                     REG16((OB) + 0x08U)            /*!< option byte write protection 0 */
    40. 

  40. #define OB_WP1                     REG16((OB) + 0x0AU)            /*!< option byte write protection 1 */
    41. 

  41. #define OB_WP2                     REG16((OB) + 0x0CU)            /*!< option byte write protection 2 */
    42. 

  42. #define OB_WP3                     REG16((OB) + 0x0EU)            /*!< option byte write protection 3 */
    43. 

  43. 

  44. /* bits definitions */
    45. 

  45. /* FMC_WS */
    46. 

  46. #define FMC_WS_WSCNT               BITS(0,2)                      /*!< wait state counter */
    47. 

  47. 

  48. /* FMC_KEY0 */
    49. 

  49. #define FMC_KEY0_KEY               BITS(0,31)                     /*!< FMC_CTL0 unlock key bits */
    50. 

  50. 

  51. /* FMC_OBKEY */
    52. 

  52. #define FMC_OBKEY_OBKEY            BITS(0,31)                     /*!< option bytes unlock key bits */
    53. 

  53. 

  54. /* FMC_STAT0 */
    55. 

  55. #define FMC_STAT0_BUSY             BIT(0)                         /*!< flash busy flag bit */
    56. 

  56. #define FMC_STAT0_PGERR            BIT(2)                         /*!< flash program error flag bit */
    57. 

  57. #define FMC_STAT0_WPERR            BIT(4)                         /*!< erase/program protection error flag bit */
    58. 

  58. #define FMC_STAT0_ENDF             BIT(5)                         /*!< end of operation flag bit */
    59. 

  59. 

  60. /* FMC_CTL0 */
    61. 

  61. #define FMC_CTL0_PG                BIT(0)                         /*!< main flash program for bank0 command bit */
    62. 

  62. #define FMC_CTL0_PER               BIT(1)                         /*!< main flash page erase for bank0 command bit */
    63. 

  63. #define FMC_CTL0_MER               BIT(2)                         /*!< main flash mass erase for bank0 command bit */
    64. 

  64. #define FMC_CTL0_OBPG              BIT(4)                         /*!< option bytes program command bit */
    65. 

  65. #define FMC_CTL0_OBER              BIT(5)                         /*!< option bytes erase command bit */
    66. 

  66. #define FMC_CTL0_START             BIT(6)                         /*!< send erase command to FMC bit */
    67. 

  67. #define FMC_CTL0_LK                BIT(7)                         /*!< FMC_CTL0 lock bit */
    68. 

  68. #define FMC_CTL0_OBWEN             BIT(9)                         /*!< option bytes erase/program enable bit */
    69. 

  69. #define FMC_CTL0_ERRIE             BIT(10)                        /*!< error interrupt enable bit */
    70. 

  70. #define FMC_CTL0_ENDIE             BIT(12)                        /*!< end of operation interrupt enable bit */
    71. 

  71. 

  72. /* FMC_ADDR0 */
    73. 

  73. #define FMC_ADDR0_ADDR             BITS(0,31)                     /*!< Flash erase/program command address bits */
    74. 

  74. 

  75. /* FMC_OBSTAT */
    76. 

  76. #define FMC_OBSTAT_OBERR           BIT(0)                         /*!< option bytes read error bit. */
    77. 

  77. #define FMC_OBSTAT_SPC             BIT(1)                         /*!< option bytes security protection code */
    78. 

  78. #define FMC_OBSTAT_USER            BITS(2,9)                      /*!< store USER of option bytes block after system reset */
    79. 

  79. #define FMC_OBSTAT_DATA            BITS(10,25)                    /*!< store DATA of option bytes block after system reset. */
    80. 

  80. 

  81. /* FMC_WP */
    82. 

  82. #define FMC_WP_WP                  BITS(0,31)                     /*!< store WP of option bytes block after system reset */
    83. 

  83. 

  84. /* FMC_KEY1 */
    85. 

  85. #define FMC_KEY1_KEY               BITS(0,31)                     /*!< FMC_CTL1 unlock key bits */
    86. 

  86. 

  87. /* FMC_STAT1 */
    88. 

  88. #define FMC_STAT1_BUSY             BIT(0)                         /*!< flash busy flag bit */
    89. 

  89. #define FMC_STAT1_PGERR            BIT(2)                         /*!< flash program error flag bit */
    90. 

  90. #define FMC_STAT1_WPERR            BIT(4)                         /*!< erase/program protection error flag bit */
    91. 

  91. #define FMC_STAT1_ENDF             BIT(5)                         /*!< end of operation flag bit */
    92. 

  92. 

  93. /* FMC_CTL1 */
    94. 

  94. #define FMC_CTL1_PG                BIT(0)                         /*!< main flash program for bank1 command bit */
    95. 

  95. #define FMC_CTL1_PER               BIT(1)                         /*!< main flash page erase for bank1 command bit */
    96. 

  96. #define FMC_CTL1_MER               BIT(2)                         /*!< main flash mass erase for bank1 command bit */
    97. 

  97. #define FMC_CTL1_START             BIT(6)                         /*!< send erase command to FMC bit */
    98. 

  98. #define FMC_CTL1_LK                BIT(7)                         /*!< FMC_CTL1 lock bit */
    99. 

  99. #define FMC_CTL1_ERRIE             BIT(10)                        /*!< error interrupt enable bit */
    100. 

  100. #define FMC_CTL1_ENDIE             BIT(12)                        /*!< end of operation interrupt enable bit */
    101. 

  101. 

  102. /* FMC_ADDR1 */
    103. 

  103. #define FMC_ADDR1_ADDR             BITS(0,31)                     /*!< Flash erase/program command address bits */
    104. 

  104. 

  105. /* FMC_WSEN */
    106. 

  106. #define FMC_WSEN_WSEN              BIT(0)                         /*!< FMC wait state enable bit */
    107. 

  107. 

  108. /* FMC_PID */
    109. 

  109. #define FMC_PID_PID                BITS(0,31)                     /*!< product ID bits */
    110. 

  110. 

  111. /* constants definitions */
    112. 

  112. /* define the FMC bit position and its register index offset */
    113. 

  113. #define FMC_REGIDX_BIT(regidx, bitpos)              (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
    114. 

  114. #define FMC_REG_VAL(offset)                         (REG32(FMC + ((uint32_t)(offset) >> 6)))
    115. 

  115. #define FMC_BIT_POS(val)                            ((uint32_t)(val) & 0x1FU)
    116. 

  116. #define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1)   (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
    117. 

  117. #define FMC_REG_VALS(offset)                        (REG32(FMC + ((uint32_t)(offset) >> 12)))
    118. 

  118. #define FMC_BIT_POS0(val)                           (((uint32_t)(val) >> 6) & 0x1FU)
    119. 

  119. #define FMC_BIT_POS1(val)                           ((uint32_t)(val) & 0x1FU)
    120. 

  120. #define FMC_REG_OFFSET_GET(flag)                    ((uint32_t)(flag) >> 12)
    121. 

  121. 

  122. /* configuration register */
    123. 

  123. #define FMC_STAT0_REG_OFFSET             0x0CU                    /*!< status register 0 offset */
    124. 

  124. #define FMC_CTL0_REG_OFFSET              0x10U                    /*!< control register 0 offset */
    125. 

  125. #define FMC_STAT1_REG_OFFSET             0x4CU                    /*!< status register 1 offset */
    126. 

  126. #define FMC_CTL1_REG_OFFSET              0x50U                    /*!< control register 1 offset */
    127. 

  127. #define FMC_OBSTAT_REG_OFFSET            0x1CU                    /*!< option byte status register offset */
    128. 

  128. 

  129. /* fmc state */
    130. 

  130. typedef enum
    131. 

  131. {
    132. 

  132.     FMC_READY,                                                    /*!< the operation has been completed */
    133. 

  133.     FMC_BUSY,                                                     /*!< the operation is in progress */
    134. 

  134.     FMC_PGERR,                                                    /*!< program error */
    135. 

  135.     FMC_WPERR,                                                    /*!< erase/program protection error */
    136. 

  136.     FMC_TOERR,                                                    /*!< timeout error */
    137. 

  137. }fmc_state_enum;
    138. 

  138. 

  139. /* FMC interrupt enable */
    140. 

  140. typedef enum
    141. 

  141. {
    142. 

  142.     FMC_INT_BANK0_END     = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U),            /*!< enable FMC end of program interrupt */
    143. 

  143.     FMC_INT_BANK0_ERR     = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U),            /*!< enable FMC error interrupt */
    144. 

  144.     FMC_INT_BANK1_END     = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U),            /*!< enable FMC bank1 end of program interrupt */
    145. 

  145.     FMC_INT_BANK1_ERR     = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U),            /*!< enable FMC bank1 error interrupt */
    146. 

  146. }fmc_int_enum;
    147. 

  147. 

  148. /* FMC flags */
    149. 

  149. typedef enum
    150. 

  150. {
    151. 

  151.     FMC_FLAG_BANK0_BUSY   = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U),            /*!< FMC bank0 busy flag */
    152. 

  152.     FMC_FLAG_BANK0_PGERR  = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U),            /*!< FMC bank0 operation error flag bit */
    153. 

  153.     FMC_FLAG_BANK0_WPERR  = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U),            /*!< FMC bank0 erase/program protection error flag bit */
    154. 

  154.     FMC_FLAG_BANK0_END    = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U),            /*!< FMC bank0 end of operation flag bit */
    155. 

  155.     FMC_FLAG_OBERR        = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U),           /*!< FMC option bytes read error flag */
    156. 

  156.     FMC_FLAG_BANK1_BUSY   = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U),            /*!< FMC bank1 busy flag */
    157. 

  157.     FMC_FLAG_BANK1_PGERR  = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U),            /*!< FMC bank1 operation error flag bit */
    158. 

  158.     FMC_FLAG_BANK1_WPERR  = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U),            /*!< FMC bank1 erase/program protection error flag bit */
    159. 

  159.     FMC_FLAG_BANK1_END    = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U),            /*!< FMC bank1 end of operation flag bit */
    160. 

  160. }fmc_flag_enum;
    161. 

  161. 

  162. /* FMC interrupt flags */
    163. 

  163. typedef enum
    164. 

  164. {
    165. 

  165.     FMC_INT_FLAG_BANK0_PGERR  = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U),  /*!< FMC bank0 operation error interrupt flag bit */
    166. 

  166.     FMC_INT_FLAG_BANK0_WPERR  = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U),  /*!< FMC bank0 erase/program protection error interrupt flag bit */
    167. 

  167.     FMC_INT_FLAG_BANK0_END    = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U),  /*!< FMC bank0 end of operation interrupt flag bit */
    168. 

  168.     FMC_INT_FLAG_BANK1_PGERR  = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U),  /*!< FMC bank1 operation error interrupt flag bit */
    169. 

  169.     FMC_INT_FLAG_BANK1_WPERR  = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U),  /*!< FMC bank1 erase/program protection error interrupt flag bit */
    170. 

  170.     FMC_INT_FLAG_BANK1_END    = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U),  /*!< FMC bank1 end of operation interrupt flag bit */
    171. 

  171. }fmc_interrupt_flag_enum;
    172. 

  172. 

  173. /* unlock key */
    174. 

  174. #define UNLOCK_KEY0                ((uint32_t)0x45670123U)        /*!< unlock key 0 */
    175. 

  175. #define UNLOCK_KEY1                ((uint32_t)0xCDEF89ABU)        /*!< unlock key 1 */
    176. 

  176. 

  177. /* FMC wait state counter */
    178. 

  178. #define WS_WSCNT(regval)           (BITS(0,2) & ((uint32_t)(regval)))
    179. 

  179. #define WS_WSCNT_0                 WS_WSCNT(0)                    /*!< FMC 0 wait */
    180. 

  180. #define WS_WSCNT_1                 WS_WSCNT(1)                    /*!< FMC 1 wait */
    181. 

  181. #define WS_WSCNT_2                 WS_WSCNT(2)                    /*!< FMC 2 wait */
    182. 

  182. 

  183. /* option bytes software/hardware free watch dog timer */  
    184. 

  184. #define OB_FWDGT_SW                ((uint8_t)0x01U)               /*!< software free watchdog */
    185. 

  185. #define OB_FWDGT_HW                ((uint8_t)0x00U)               /*!< hardware free watchdog */
    186. 

  186. 

  187. /* option bytes reset or not entering deep sleep mode */
    188. 

  188. #define OB_DEEPSLEEP_NRST          ((uint8_t)0x02U)               /*!< no reset when entering deepsleep mode */
    189. 

  189. #define OB_DEEPSLEEP_RST           ((uint8_t)0x00U)               /*!< generate a reset instead of entering deepsleep mode */
    190. 

  190. 

  191. /* option bytes reset or not entering standby mode */
    192. 

  192. #define OB_STDBY_NRST              ((uint8_t)0x04U)               /*!< no reset when entering deepsleep mode */
    193. 

  193. #define OB_STDBY_RST               ((uint8_t)0x00U)               /*!< generate a reset instead of entering standby mode */
    194. 

  194. 

  195. /* option bytes boot bank value */
    196. 

  196. #define OB_BOOT_B0                 ((uint8_t)0x08U)               /*!< boot from bank0 */
    197. 

  197. #define OB_BOOT_B1                 ((uint8_t)0x00U)               /*!< boot from bank1 */
    198. 

  198. 

  199. #define OB_USER_MASK               ((uint8_t)0xF0U)               /*!< MASK value */
    200. 

  200. 

  201. /* read protect configure */
    202. 

  202. #define FMC_NSPC                   ((uint8_t)0xA5U)               /*!< no security protection */
    203. 

  203. #define FMC_USPC                   ((uint8_t)0xBBU)               /*!< under security protection */
    204. 

  204. 

  205. /* OB_SPC */
    206. 

  206. #define OB_SPC_SPC                 ((uint32_t)0x000000FFU)        /*!< option byte security protection value */
    207. 

  207. #define OB_SPC_SPC_N               ((uint32_t)0x0000FF00U)        /*!< option byte security protection complement value */
    208. 

  208. 

  209. /* OB_USER */
    210. 

  210. #define OB_USER_USER               ((uint32_t)0x00FF0000U)        /*!< user option value */
    211. 

  211. #define OB_USER_USER_N             ((uint32_t)0xFF000000U)        /*!< user option complement value */
    212. 

  212. 

  213. /* OB_WP0 */
    214. 

  214. #define OB_WP0_WP0                 ((uint32_t)0x000000FFU)        /*!< FMC write protection option value */
    215. 

  215. 

  216. /* OB_WP1 */
    217. 

  217. #define OB_WP1_WP1                 ((uint32_t)0x0000FF00U)        /*!< FMC write protection option complement value */
    218. 

  218. 

  219. /* OB_WP2 */
    220. 

  220. #define OB_WP2_WP2                 ((uint32_t)0x00FF0000U)        /*!< FMC write protection option value */
    221. 

  221. 

  222. /* OB_WP3 */
    223. 

  223. #define OB_WP3_WP3                 ((uint32_t)0xFF000000U)        /*!< FMC write protection option complement value */
    224. 

  224. 

  225. /* option bytes write protection */
    226. 

  226. #define OB_WP_0                    ((uint32_t)0x00000001U)        /*!< erase/program protection of sector 0  */
    227. 

  227. #define OB_WP_1                    ((uint32_t)0x00000002U)        /*!< erase/program protection of sector 1  */
    228. 

  228. #define OB_WP_2                    ((uint32_t)0x00000004U)        /*!< erase/program protection of sector 2  */
    229. 

  229. #define OB_WP_3                    ((uint32_t)0x00000008U)        /*!< erase/program protection of sector 3  */
    230. 

  230. #define OB_WP_4                    ((uint32_t)0x00000010U)        /*!< erase/program protection of sector 4  */
    231. 

  231. #define OB_WP_5                    ((uint32_t)0x00000020U)        /*!< erase/program protection of sector 5  */
    232. 

  232. #define OB_WP_6                    ((uint32_t)0x00000040U)        /*!< erase/program protection of sector 6  */
    233. 

  233. #define OB_WP_7                    ((uint32_t)0x00000080U)        /*!< erase/program protection of sector 7  */
    234. 

  234. #define OB_WP_8                    ((uint32_t)0x00000100U)        /*!< erase/program protection of sector 8  */
    235. 

  235. #define OB_WP_9                    ((uint32_t)0x00000200U)        /*!< erase/program protection of sector 9  */
    236. 

  236. #define OB_WP_10                   ((uint32_t)0x00000400U)        /*!< erase/program protection of sector 10 */
    237. 

  237. #define OB_WP_11                   ((uint32_t)0x00000800U)        /*!< erase/program protection of sector 11 */
    238. 

  238. #define OB_WP_12                   ((uint32_t)0x00001000U)        /*!< erase/program protection of sector 12 */
    239. 

  239. #define OB_WP_13                   ((uint32_t)0x00002000U)        /*!< erase/program protection of sector 13 */
    240. 

  240. #define OB_WP_14                   ((uint32_t)0x00004000U)        /*!< erase/program protection of sector 14 */
    241. 

  241. #define OB_WP_15                   ((uint32_t)0x00008000U)        /*!< erase/program protection of sector 15 */
    242. 

  242. #define OB_WP_16                   ((uint32_t)0x00010000U)        /*!< erase/program protection of sector 16 */
    243. 

  243. #define OB_WP_17                   ((uint32_t)0x00020000U)        /*!< erase/program protection of sector 17 */
    244. 

  244. #define OB_WP_18                   ((uint32_t)0x00040000U)        /*!< erase/program protection of sector 18 */
    245. 

  245. #define OB_WP_19                   ((uint32_t)0x00080000U)        /*!< erase/program protection of sector 19 */
    246. 

  246. #define OB_WP_20                   ((uint32_t)0x00100000U)        /*!< erase/program protection of sector 20 */
    247. 

  247. #define OB_WP_21                   ((uint32_t)0x00200000U)        /*!< erase/program protection of sector 21 */
    248. 

  248. #define OB_WP_22                   ((uint32_t)0x00400000U)        /*!< erase/program protection of sector 22 */
    249. 

  249. #define OB_WP_23                   ((uint32_t)0x00800000U)        /*!< erase/program protection of sector 23 */
    250. 

  250. #define OB_WP_24                   ((uint32_t)0x01000000U)        /*!< erase/program protection of sector 24 */
    251. 

  251. #define OB_WP_25                   ((uint32_t)0x02000000U)        /*!< erase/program protection of sector 25 */
    252. 

  252. #define OB_WP_26                   ((uint32_t)0x04000000U)        /*!< erase/program protection of sector 26 */
    253. 

  253. #define OB_WP_27                   ((uint32_t)0x08000000U)        /*!< erase/program protection of sector 27 */
    254. 

  254. #define OB_WP_28                   ((uint32_t)0x10000000U)        /*!< erase/program protection of sector 28 */
    255. 

  255. #define OB_WP_29                   ((uint32_t)0x20000000U)        /*!< erase/program protection of sector 29 */
    256. 

  256. #define OB_WP_30                   ((uint32_t)0x40000000U)        /*!< erase/program protection of sector 30 */
    257. 

  257. #define OB_WP_31                   ((uint32_t)0x80000000U)        /*!< erase/program protection of sector 31 */
    258. 

  258. #define OB_WP_ALL                  ((uint32_t)0xFFFFFFFFU)        /*!< erase/program protection of all sectors */
    259. 

  259. 

  260. /* FMC timeout */
    261. 

  261. #define FMC_TIMEOUT_COUNT          ((uint32_t)0x000F0000U)        /*!< FMC timeout count value */
    262. 

  262. 

  263. /* FMC BANK address */
    264. 

  264. #define FMC_BANK0_END_ADDRESS      ((uint32_t)0x0807FFFFU)        /*!< FMC bank0 end address */
    265. 

  265. #define FMC_BANK0_SIZE             ((uint32_t)0x00000200U)        /*!< FMC bank0 size */
    266. 

  266. #define FMC_SIZE                   (*(uint16_t *)0x1FFFF7E0U)     /*!< FMC size */
    267. 

  267. 

  268. /* function declarations */
    269. 

  269. /* FMC main memory programming functions */
    270. 

  270. /* set the FMC wait state counter */
    271. 

  271. void fmc_wscnt_set(uint32_t wscnt);
    272. 

  272. /* unlock the main FMC operation */
    273. 

  273. void fmc_unlock(void);
    274. 

  274. /* unlock the FMC bank0 operation */
    275. 

  275. void fmc_bank0_unlock(void);
    276. 

  276. /* unlock the FMC bank1 operation */
    277. 

  277. void fmc_bank1_unlock(void);
    278. 

  278. /* lock the main FMC operation */
    279. 

  279. void fmc_lock(void);
    280. 

  280. /* lock the bank0 FMC operation */
    281. 

  281. void fmc_bank0_lock(void);
    282. 

  282. /* lock the bank1 FMC operation */
    283. 

  283. void fmc_bank1_lock(void);
    284. 

  284. /* FMC erase page */
    285. 

  285. fmc_state_enum fmc_page_erase(uint32_t page_address);
    286. 

  286. /* FMC erase whole chip */
    287. 

  287. fmc_state_enum fmc_mass_erase(void);
    288. 

  288. /* FMC erase whole bank0 */
    289. 

  289. fmc_state_enum fmc_bank0_erase(void);
    290. 

  290. /* FMC erase whole bank1 */
    291. 

  291. fmc_state_enum fmc_bank1_erase(void);
    292. 

  292. /* FMC program a word at the corresponding address */
    293. 

  293. fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
    294. 

  294. /* FMC program a half word at the corresponding address */
    295. 

  295. fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
    296. 

  296. 

  297. /* FMC option bytes programming functions */
    298. 

  298. /* unlock the option byte operation */
    299. 

  299. void ob_unlock(void);
    300. 

  300. /* lock the option byte operation */
    301. 

  301. void ob_lock(void);
    302. 

  302. /* erase the option byte */
    303. 

  303. fmc_state_enum ob_erase(void);
    304. 

  304. /* enable write protect */
    305. 

  305. fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
    306. 

  306. /* configure the option byte security protection */
    307. 

  307. fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
    308. 

  308. /* write the FMC option byte */
    309. 

  309. fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
    310. 

  310. /* program option bytes data */
    311. 

  311. fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
    312. 

  312. /* get the FMC option byte user */
    313. 

  313. uint8_t ob_user_get(void);
    314. 

  314. /* get OB_DATA in register FMC_OBSTAT */
    315. 

  315. uint16_t ob_data_get(void);
    316. 

  316. /* get the FMC option byte write protection */
    317. 

  317. uint32_t ob_write_protection_get(void);
    318. 

  318. /* get option byte security protection code value */
    319. 

  319. FlagStatus ob_spc_get(void);
    320. 

  320. 

  321. /* FMC interrupts and flags management functions */
    322. 

  322. /* enable FMC interrupt */
    323. 

  323. void fmc_interrupt_enable(uint32_t interrupt);
    324. 

  324. /* disable FMC interrupt */
    325. 

  325. void fmc_interrupt_disable(uint32_t interrupt);
    326. 

  326. /* check flag is set or not */
    327. 

  327. FlagStatus fmc_flag_get(uint32_t flag);
    328. 

  328. /* clear the FMC flag */
    329. 

  329. void fmc_flag_clear(uint32_t flag);
    330. 

  330. /* get FMC interrupt flag state */
    331. 

  331. FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
    332. 

  332. /* clear FMC interrupt flag state */
    333. 

  333. void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
    334. 

  334. /* return the  FMC bank0 state */
    335. 

  335. fmc_state_enum fmc_bank0_state_get(void);
    336. 

  336. /* return the  FMC bank1 state */
    337. 

  337. fmc_state_enum fmc_bank1_state_get(void);
    338. 

  338. /* check FMC bank0 ready or not */
    339. 

  339. fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout);
    340. 

  340. /* check FMC bank1 ready or not */
    341. 

  341. fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout);
    342. 

  342. 

  343. #endif /* GD32F30X_FMC_H */
    344.