gd32f3x0_spi.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792
  1. /*!
  2. \file gd32f3x0_spi.c
  3. \brief SPI driver
  4. \version 2017-06-06, V1.0.0, firmware for GD32F3x0
  5. \version 2019-06-01, V2.0.0, firmware for GD32F3x0
  6. */
  7. /*
  8. Copyright (c) 2019, GigaDevice Semiconductor Inc.
  9. Redistribution and use in source and binary forms, with or without modification,
  10. are permitted provided that the following conditions are met:
  11. 1. Redistributions of source code must retain the above copyright notice, this
  12. list of conditions and the following disclaimer.
  13. 2. Redistributions in binary form must reproduce the above copyright notice,
  14. this list of conditions and the following disclaimer in the documentation
  15. and/or other materials provided with the distribution.
  16. 3. Neither the name of the copyright holder nor the names of its contributors
  17. may be used to endorse or promote products derived from this software without
  18. specific prior written permission.
  19. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21. WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  23. INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24. NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25. PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  26. WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  28. OF SUCH DAMAGE.
  29. */
  30. #include "gd32f3x0_spi.h"
  31. #define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */
  32. #define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */
  33. #define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */
  34. /*!
  35. \brief reset SPI and I2S
  36. \param[in] spi_periph: SPIx(x=0,1)
  37. \param[out] none
  38. \retval none
  39. */
  40. void spi_i2s_deinit(uint32_t spi_periph)
  41. {
  42. switch(spi_periph){
  43. case SPI0:
  44. /* reset SPI0 and I2S0 */
  45. rcu_periph_reset_enable(RCU_SPI0RST);
  46. rcu_periph_reset_disable(RCU_SPI0RST);
  47. break;
  48. case SPI1:
  49. /* reset SPI1 */
  50. rcu_periph_reset_enable(RCU_SPI1RST);
  51. rcu_periph_reset_disable(RCU_SPI1RST);
  52. break;
  53. default :
  54. break;
  55. }
  56. }
  57. /*!
  58. \brief initialize the parameters of SPI struct with the default values
  59. \param[in] spi_struct: SPI parameter stuct
  60. \param[out] none
  61. \retval none
  62. */
  63. void spi_struct_para_init(spi_parameter_struct* spi_struct)
  64. {
  65. /* set the SPI struct with the default values */
  66. spi_struct->device_mode = SPI_SLAVE;
  67. spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX;
  68. spi_struct->frame_size = SPI_FRAMESIZE_8BIT;
  69. spi_struct->nss = SPI_NSS_HARD;
  70. spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
  71. spi_struct->prescale = SPI_PSC_2;
  72. }
  73. /*!
  74. \brief initialize SPI parameter
  75. \param[in] spi_periph: SPIx(x=0,1)
  76. \param[in] spi_struct: SPI parameter initialization stuct members of the structure
  77. and the member values are shown as below:
  78. device_mode: SPI_MASTER, SPI_SLAVE
  79. trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY,
  80. SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT
  81. frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT
  82. nss: SPI_NSS_SOFT, SPI_NSS_HARD
  83. endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB
  84. clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE
  85. SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE
  86. prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256)
  87. \param[out] none
  88. \retval none
  89. */
  90. void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct)
  91. {
  92. uint32_t reg = 0U;
  93. reg = SPI_CTL0(spi_periph);
  94. reg &= SPI_INIT_MASK;
  95. /* select SPI as master or slave */
  96. reg |= spi_struct->device_mode;
  97. /* select SPI transfer mode */
  98. reg |= spi_struct->trans_mode;
  99. /* select SPI frame size */
  100. reg |= spi_struct->frame_size;
  101. /* select SPI NSS use hardware or software */
  102. reg |= spi_struct->nss;
  103. /* select SPI LSB or MSB */
  104. reg |= spi_struct->endian;
  105. /* select SPI polarity and phase */
  106. reg |= spi_struct->clock_polarity_phase;
  107. /* select SPI prescale to adjust transmit speed */
  108. reg |= spi_struct->prescale;
  109. /* write to SPI_CTL0 register */
  110. SPI_CTL0(spi_periph) = (uint32_t)reg;
  111. /* select SPI mode */
  112. SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL);
  113. }
  114. /*!
  115. \brief enable SPI
  116. \param[in] spi_periph: SPIx(x=0,1)
  117. \param[out] none
  118. \retval none
  119. */
  120. void spi_enable(uint32_t spi_periph)
  121. {
  122. SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN;
  123. }
  124. /*!
  125. \brief disable SPI
  126. \param[in] spi_periph: SPIx(x=0,1)
  127. \param[out] none
  128. \retval none
  129. */
  130. void spi_disable(uint32_t spi_periph)
  131. {
  132. SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN);
  133. }
  134. #ifdef GD32F350
  135. /*!
  136. \brief initialize I2S parameter
  137. \param[in] spi_periph: SPI0
  138. \param[in] mode: I2S operation mode
  139. only one parameter can be selected which is shown as below:
  140. \arg I2S_MODE_SLAVETX: I2S slave transmit mode
  141. \arg I2S_MODE_SLAVERX: I2S slave receive mode
  142. \arg I2S_MODE_MASTERTX: I2S master transmit mode
  143. \arg I2S_MODE_MASTERRX: I2S master receive mode
  144. \param[in] standard: I2S standard
  145. only one parameter can be selected which is shown as below:
  146. \arg I2S_STD_PHILLIPS: I2S phillips standard
  147. \arg I2S_STD_MSB: I2S MSB standard
  148. \arg I2S_STD_LSB: I2S LSB standard
  149. \arg I2S_STD_PCMSHORT: I2S PCM short standard
  150. \arg I2S_STD_PCMLONG: I2S PCM long standard
  151. \param[in] ckpl: I2S idle state clock polarity
  152. only one parameter can be selected which is shown as below:
  153. \arg I2S_CKPL_LOW: I2S clock polarity low level
  154. \arg I2S_CKPL_HIGH: I2S clock polarity high level
  155. \param[out] none
  156. \retval none
  157. */
  158. void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl)
  159. {
  160. uint32_t reg = 0U;
  161. reg = SPI_I2SCTL(spi_periph);
  162. reg &= I2S_INIT_MASK;
  163. /* enable I2S mode */
  164. reg |= (uint32_t)SPI_I2SCTL_I2SSEL;
  165. /* select I2S mode */
  166. reg |= (uint32_t)mode;
  167. /* select I2S standard */
  168. reg |= (uint32_t)standard;
  169. /* select I2S polarity */
  170. reg |= (uint32_t)ckpl;
  171. /* write to SPI_I2SCTL register */
  172. SPI_I2SCTL(spi_periph) = (uint32_t)reg;
  173. }
  174. /*!
  175. \brief configure I2S prescaler
  176. \param[in] spi_periph: SPI0
  177. \param[in] audiosample: I2S audio sample rate
  178. only one parameter can be selected which is shown as below:
  179. \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz
  180. \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz
  181. \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz
  182. \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz
  183. \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz
  184. \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz
  185. \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz
  186. \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz
  187. \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz
  188. \param[in] frameformat: I2S data length and channel length
  189. only one parameter can be selected which is shown as below:
  190. \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit
  191. \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit
  192. \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit
  193. \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit
  194. \param[in] mckout: I2S master clock output
  195. only one parameter can be selected which is shown as below:
  196. \arg I2S_MCKOUT_ENABLE: I2S master clock output enable
  197. \arg I2S_MCKOUT_DISABLE: I2S master clock output disable
  198. \param[out] none
  199. \retval none
  200. */
  201. void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout)
  202. {
  203. uint32_t i2sdiv = 2U, i2sof = 0U;
  204. uint32_t clks = 0U;
  205. uint32_t i2sclock = 0U;
  206. /* deinit SPI_I2SPSC register */
  207. SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE;
  208. /* get system clock */
  209. i2sclock = rcu_clock_freq_get(CK_SYS);
  210. /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */
  211. if(I2S_MCKOUT_ENABLE == mckout){
  212. clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample);
  213. }else{
  214. if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){
  215. clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample);
  216. }else{
  217. clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample);
  218. }
  219. }
  220. /* remove the floating point */
  221. clks = (clks + 5U) / 10U;
  222. i2sof = (clks & 0x00000001U);
  223. i2sdiv = ((clks - i2sof) / 2U);
  224. i2sof = (i2sof << 8U);
  225. /* set the default values */
  226. if((i2sdiv < 2U) || (i2sdiv > 255U)){
  227. i2sdiv = 2U;
  228. i2sof = 0U;
  229. }
  230. /* configure SPI_I2SPSC */
  231. SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout);
  232. /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */
  233. SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN));
  234. /* configure data frame format */
  235. SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat;
  236. }
  237. /*!
  238. \brief enable I2S
  239. \param[in] spi_periph: SPI0
  240. \param[out] none
  241. \retval none
  242. */
  243. void i2s_enable(uint32_t spi_periph)
  244. {
  245. SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN;
  246. }
  247. /*!
  248. \brief disable I2S
  249. \param[in] spi_periph: SPI0
  250. \param[out] none
  251. \retval none
  252. */
  253. void i2s_disable(uint32_t spi_periph)
  254. {
  255. SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN);
  256. }
  257. #endif /* GD32F350 */
  258. /*!
  259. \brief enable SPI NSS output
  260. \param[in] spi_periph: SPIx(x=0,1)
  261. \param[out] none
  262. \retval none
  263. */
  264. void spi_nss_output_enable(uint32_t spi_periph)
  265. {
  266. SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV;
  267. }
  268. /*!
  269. \brief disable SPI NSS output
  270. \param[in] spi_periph: SPIx(x=0,1)
  271. \param[out] none
  272. \retval none
  273. */
  274. void spi_nss_output_disable(uint32_t spi_periph)
  275. {
  276. SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV);
  277. }
  278. /*!
  279. \brief SPI NSS pin high level in software mode
  280. \param[in] spi_periph: SPIx(x=0,1)
  281. \param[out] none
  282. \retval none
  283. */
  284. void spi_nss_internal_high(uint32_t spi_periph)
  285. {
  286. SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS;
  287. }
  288. /*!
  289. \brief SPI NSS pin low level in software mode
  290. \param[in] spi_periph: SPIx(x=0,1)
  291. \param[out] none
  292. \retval none
  293. */
  294. void spi_nss_internal_low(uint32_t spi_periph)
  295. {
  296. SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS);
  297. }
  298. /*!
  299. \brief enable SPI DMA send or receive
  300. \param[in] spi_periph: SPIx(x=0,1)
  301. \param[in] dma: SPI DMA mode
  302. only one parameter can be selected which is shown as below:
  303. \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA
  304. \arg SPI_DMA_RECEIVE: SPI receive data using DMA
  305. \param[out] none
  306. \retval none
  307. */
  308. void spi_dma_enable(uint32_t spi_periph, uint8_t dma)
  309. {
  310. if(SPI_DMA_TRANSMIT == dma){
  311. SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN;
  312. }else{
  313. SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN;
  314. }
  315. }
  316. /*!
  317. \brief disable SPI DMA send or receive
  318. \param[in] spi_periph: SPIx(x=0,1)
  319. \param[in] dma: SPI DMA mode
  320. only one parameter can be selected which is shown as below:
  321. \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA
  322. \arg SPI_DMA_RECEIVE: SPI receive data using DMA
  323. \param[out] none
  324. \retval none
  325. */
  326. void spi_dma_disable(uint32_t spi_periph, uint8_t dma)
  327. {
  328. if(SPI_DMA_TRANSMIT == dma){
  329. SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN);
  330. }else{
  331. SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN);
  332. }
  333. }
  334. /*!
  335. \brief configure SPI/I2S data frame format
  336. \param[in] spi_periph: SPIx(x=0,1)
  337. \param[in] frame_format: SPI frame size
  338. only one parameter can be selected which is shown as below:
  339. \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits
  340. \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits
  341. \param[out] none
  342. \retval none
  343. */
  344. void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format)
  345. {
  346. /* clear SPI_CTL0_FF16 bit */
  347. SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16);
  348. /* confige SPI_CTL0_FF16 bit */
  349. SPI_CTL0(spi_periph) |= (uint32_t)frame_format;
  350. }
  351. /*!
  352. \brief SPI transmit data
  353. \param[in] spi_periph: SPIx(x=0,1)
  354. \param[in] data: 16-bit data
  355. \param[out] none
  356. \retval none
  357. */
  358. void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data)
  359. {
  360. SPI_DATA(spi_periph) = (uint32_t)data;
  361. }
  362. /*!
  363. \brief SPI receive data
  364. \param[in] spi_periph: SPIx(x=0,1)
  365. \param[out] none
  366. \retval 16-bit data
  367. */
  368. uint16_t spi_i2s_data_receive(uint32_t spi_periph)
  369. {
  370. return ((uint16_t)SPI_DATA(spi_periph));
  371. }
  372. /*!
  373. \brief configure SPI bidirectional transfer direction
  374. \param[in] spi_periph: SPIx(x=0,1)
  375. \param[in] transfer_direction: SPI transfer direction
  376. only one parameter can be selected which is shown as below:
  377. \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
  378. \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
  379. \param[out] none
  380. \retval none
  381. */
  382. void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction)
  383. {
  384. if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){
  385. /* set the transmit only mode */
  386. SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT;
  387. }else{
  388. /* set the receive only mode */
  389. SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE;
  390. }
  391. }
  392. /*!
  393. \brief set CRC polynomial
  394. \param[in] spi_periph: SPIx(x=0,1)
  395. \param[in] crc_poly: CRC polynomial value
  396. \param[out] none
  397. \retval none
  398. */
  399. void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly)
  400. {
  401. /* enable SPI CRC */
  402. SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
  403. /* set SPI CRC polynomial */
  404. SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly;
  405. }
  406. /*!
  407. \brief get SPI CRC polynomial
  408. \param[in] spi_periph: SPIx(x=0,1)
  409. \param[out] none
  410. \retval 16-bit CRC polynomial
  411. */
  412. uint16_t spi_crc_polynomial_get(uint32_t spi_periph)
  413. {
  414. return ((uint16_t)SPI_CRCPOLY(spi_periph));
  415. }
  416. /*!
  417. \brief turn on CRC function
  418. \param[in] spi_periph: SPIx(x=0,1)
  419. \param[out] none
  420. \retval none
  421. */
  422. void spi_crc_on(uint32_t spi_periph)
  423. {
  424. SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN;
  425. }
  426. /*!
  427. \brief turn off CRC function
  428. \param[in] spi_periph: SPIx(x=0,1)
  429. \param[out] none
  430. \retval none
  431. */
  432. void spi_crc_off(uint32_t spi_periph)
  433. {
  434. SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN);
  435. }
  436. /*!
  437. \brief SPI next data is CRC value
  438. \param[in] spi_periph: SPIx(x=0,1)
  439. \param[out] none
  440. \retval none
  441. */
  442. void spi_crc_next(uint32_t spi_periph)
  443. {
  444. SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT;
  445. }
  446. /*!
  447. \brief get SPI CRC send value or receive value
  448. \param[in] spi_periph: SPIx(x=0,1)
  449. \param[in] crc: SPI crc value
  450. \arg SPI_CRC_TX: get transmit crc value
  451. \arg SPI_CRC_RX: get receive crc value
  452. \param[out] none
  453. \retval 16-bit CRC value
  454. */
  455. uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc)
  456. {
  457. if(SPI_CRC_TX == crc){
  458. return ((uint16_t)(SPI_TCRC(spi_periph)));
  459. }else{
  460. return ((uint16_t)(SPI_RCRC(spi_periph)));
  461. }
  462. }
  463. /*!
  464. \brief enable SPI TI mode
  465. \param[in] spi_periph: SPIx(x=0,1)
  466. \param[out] none
  467. \retval none
  468. */
  469. void spi_ti_mode_enable(uint32_t spi_periph)
  470. {
  471. SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD;
  472. }
  473. /*!
  474. \brief disable SPI TI mode
  475. \param[in] spi_periph: SPIx(x=0,1)
  476. \param[out] none
  477. \retval none
  478. */
  479. void spi_ti_mode_disable(uint32_t spi_periph)
  480. {
  481. SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD);
  482. }
  483. /*!
  484. \brief enable SPI NSS pulse mode
  485. \param[in] spi_periph: SPIx(x=0,1)
  486. \param[out] none
  487. \retval none
  488. */
  489. void spi_nssp_mode_enable(uint32_t spi_periph)
  490. {
  491. SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP;
  492. }
  493. /*!
  494. \brief disable SPI NSS pulse mode
  495. \param[in] spi_periph: SPIx(x=0,1)
  496. \param[out] none
  497. \retval none
  498. */
  499. void spi_nssp_mode_disable(uint32_t spi_periph)
  500. {
  501. SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP);
  502. }
  503. /*!
  504. \brief enable quad wire SPI
  505. \param[in] spi_periph: SPI1
  506. \param[out] none
  507. \retval none
  508. */
  509. void qspi_enable(uint32_t spi_periph)
  510. {
  511. SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD;
  512. }
  513. /*!
  514. \brief disable quad wire SPI
  515. \param[in] spi_periph: SPI1
  516. \param[out] none
  517. \retval none
  518. */
  519. void qspi_disable(uint32_t spi_periph)
  520. {
  521. SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD);
  522. }
  523. /*!
  524. \brief enable quad wire SPI write
  525. \param[in] spi_periph: SPI1
  526. \param[out] none
  527. \retval none
  528. */
  529. void qspi_write_enable(uint32_t spi_periph)
  530. {
  531. SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD);
  532. }
  533. /*!
  534. \brief enable quad wire SPI read
  535. \param[in] spi_periph: SPI1
  536. \param[out] none
  537. \retval none
  538. */
  539. void qspi_read_enable(uint32_t spi_periph)
  540. {
  541. SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD;
  542. }
  543. /*!
  544. \brief enable SPI_IO2 and SPI_IO3 pin output
  545. \param[in] spi_periph: SPI1
  546. \param[out] none
  547. \retval none
  548. */
  549. void qspi_io23_output_enable(uint32_t spi_periph)
  550. {
  551. SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV;
  552. }
  553. /*!
  554. \brief disable SPI_IO2 and SPI_IO3 pin output
  555. \param[in] spi_periph: SPI1
  556. \param[out] none
  557. \retval none
  558. */
  559. void qspi_io23_output_disable(uint32_t spi_periph)
  560. {
  561. SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV);
  562. }
  563. /*!
  564. \brief enable SPI and I2S interrupt
  565. \param[in] spi_periph: SPIx(x=0,1)
  566. \param[in] interrupt: SPI/I2S interrupt
  567. only one parameter can be selected which is shown as below:
  568. \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt
  569. \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  570. \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
  571. transmission underrun error and format error interrupt
  572. \param[out] none
  573. \retval none
  574. */
  575. void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt)
  576. {
  577. switch(interrupt){
  578. /* SPI/I2S transmit buffer empty interrupt */
  579. case SPI_I2S_INT_TBE:
  580. SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE;
  581. break;
  582. /* SPI/I2S receive buffer not empty interrupt */
  583. case SPI_I2S_INT_RBNE:
  584. SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE;
  585. break;
  586. /* SPI/I2S error */
  587. case SPI_I2S_INT_ERR:
  588. SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE;
  589. break;
  590. default:
  591. break;
  592. }
  593. }
  594. /*!
  595. \brief disable SPI and I2S interrupt
  596. \param[in] spi_periph: SPIx(x=0,1)
  597. \param[in] interrupt: SPI/I2S interrupt
  598. only one parameter can be selected which is shown as below:
  599. \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt
  600. \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt
  601. \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error,
  602. transmission underrun error and format error interrupt
  603. \param[out] none
  604. \retval none
  605. */
  606. void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt)
  607. {
  608. switch(interrupt){
  609. /* SPI/I2S transmit buffer empty interrupt */
  610. case SPI_I2S_INT_TBE:
  611. SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE);
  612. break;
  613. /* SPI/I2S receive buffer not empty interrupt */
  614. case SPI_I2S_INT_RBNE:
  615. SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE);
  616. break;
  617. /* SPI/I2S error */
  618. case SPI_I2S_INT_ERR:
  619. SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE);
  620. break;
  621. default :
  622. break;
  623. }
  624. }
  625. /*!
  626. \brief get SPI and I2S interrupt flag status
  627. \param[in] spi_periph: SPIx(x=0,1)
  628. \param[in] interrupt: SPI/I2S interrupt flag status
  629. only one parameter can be selected which is shown as below:
  630. \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag
  631. \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag
  632. \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag
  633. \arg SPI_INT_FLAG_CONFERR: config error interrupt flag
  634. \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag
  635. \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag
  636. \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag
  637. \param[out] none
  638. \retval FlagStatus: SET or RESET
  639. */
  640. FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt)
  641. {
  642. uint32_t reg1 = SPI_STAT(spi_periph);
  643. uint32_t reg2 = SPI_CTL1(spi_periph);
  644. switch(interrupt){
  645. /* SPI/I2S transmit buffer empty interrupt */
  646. case SPI_I2S_INT_FLAG_TBE:
  647. reg1 = reg1 & SPI_STAT_TBE;
  648. reg2 = reg2 & SPI_CTL1_TBEIE;
  649. break;
  650. /* SPI/I2S receive buffer not empty interrupt */
  651. case SPI_I2S_INT_FLAG_RBNE:
  652. reg1 = reg1 & SPI_STAT_RBNE;
  653. reg2 = reg2 & SPI_CTL1_RBNEIE;
  654. break;
  655. /* SPI/I2S overrun interrupt */
  656. case SPI_I2S_INT_FLAG_RXORERR:
  657. reg1 = reg1 & SPI_STAT_RXORERR;
  658. reg2 = reg2 & SPI_CTL1_ERRIE;
  659. break;
  660. /* SPI config error interrupt */
  661. case SPI_INT_FLAG_CONFERR:
  662. reg1 = reg1 & SPI_STAT_CONFERR;
  663. reg2 = reg2 & SPI_CTL1_ERRIE;
  664. break;
  665. /* SPI CRC error interrupt */
  666. case SPI_INT_FLAG_CRCERR:
  667. reg1 = reg1 & SPI_STAT_CRCERR;
  668. reg2 = reg2 & SPI_CTL1_ERRIE;
  669. break;
  670. /* I2S underrun error interrupt */
  671. case I2S_INT_FLAG_TXURERR:
  672. reg1 = reg1 & SPI_STAT_TXURERR;
  673. reg2 = reg2 & SPI_CTL1_ERRIE;
  674. break;
  675. /* SPI/I2S format error interrupt */
  676. case SPI_I2S_INT_FLAG_FERR:
  677. reg1 = reg1 & SPI_STAT_FERR;
  678. reg2 = reg2 & SPI_CTL1_ERRIE;
  679. break;
  680. default :
  681. break;
  682. }
  683. /*get SPI/I2S interrupt flag status */
  684. if((0U != reg1) && (0U != reg2)){
  685. return SET;
  686. }else{
  687. return RESET;
  688. }
  689. }
  690. /*!
  691. \brief get SPI and I2S flag status
  692. \param[in] spi_periph: SPIx(x=0,1)
  693. \param[in] flag: SPI/I2S flag status
  694. one or more parameters can be selected which are shown as below:
  695. \arg SPI_FLAG_TBE: transmit buffer empty flag
  696. \arg SPI_FLAG_RBNE: receive buffer not empty flag
  697. \arg SPI_FLAG_TRANS: transmit on-going flag
  698. \arg SPI_FLAG_RXORERR: receive overrun error flag
  699. \arg SPI_FLAG_CONFERR: mode config error flag
  700. \arg SPI_FLAG_CRCERR: CRC error flag
  701. \arg SPI_FLAG_FERR: format error interrupt flag
  702. \arg I2S_FLAG_TBE: transmit buffer empty flag
  703. \arg I2S_FLAG_RBNE: receive buffer not empty flag
  704. \arg I2S_FLAG_TRANS: transmit on-going flag
  705. \arg I2S_FLAG_RXORERR: overrun error flag
  706. \arg I2S_FLAG_TXURERR: underrun error flag
  707. \arg I2S_FLAG_CH: channel side flag
  708. \arg I2S_FLAG_FERR: format error interrupt flag
  709. \param[out] none
  710. \retval FlagStatus: SET or RESET
  711. */
  712. FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag)
  713. {
  714. if(RESET != (SPI_STAT(spi_periph) & flag)){
  715. return SET;
  716. }else{
  717. return RESET;
  718. }
  719. }
  720. /*!
  721. \brief clear SPI CRC error flag status
  722. \param[in] spi_periph: SPIx(x=0,1)
  723. \param[out] none
  724. \retval none
  725. */
  726. void spi_crc_error_clear(uint32_t spi_periph)
  727. {
  728. SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR);
  729. }