hc32l196_dmac.h 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356
  1. /*****************************************************************************
  2. * Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved.
  3. *
  4. * This software is owned and published by:
  5. * Huada Semiconductor Co.,Ltd ("HDSC").
  6. *
  7. * BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND
  8. * BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
  9. *
  10. * This software contains source code for use with HDSC
  11. * components. This software is licensed by HDSC to be adapted only
  12. * for use in systems utilizing HDSC components. HDSC shall not be
  13. * responsible for misuse or illegal use of this software for devices not
  14. * supported herein. HDSC is providing this software "AS IS" and will
  15. * not be responsible for issues arising from incorrect user implementation
  16. * of the software.
  17. *
  18. * Disclaimer:
  19. * HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
  20. * REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS),
  21. * ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING,
  22. * WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED
  23. * WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED
  24. * WARRANTY OF NONINFRINGEMENT.
  25. * HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT,
  26. * NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT
  27. * LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION,
  28. * LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR
  29. * INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT,
  30. * INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA,
  31. * SAVINGS OR PROFITS,
  32. * EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
  33. * YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
  34. * INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED
  35. * FROM, THE SOFTWARE.
  36. *
  37. * This software may be replicated in part or whole for the licensed use,
  38. * with the restriction that this Disclaimer and Copyright notice must be
  39. * included with each copy of this software, whether used in part or whole,
  40. * at all times.
  41. */
  42. /******************************************************************************/
  43. /** \file dma.h
  44. **
  45. ** A detailed description is available at
  46. ** @link DmacGroup Dmac description @endlink
  47. **
  48. ** - 2018-03-09 1.0 Hongjh First version for Device Driver Library of Dmac.
  49. **
  50. ******************************************************************************/
  51. #ifndef __DMAC_H__
  52. #define __DMAC_H__
  53. /*******************************************************************************
  54. * Include files
  55. ******************************************************************************/
  56. #include "ddl.h"
  57. /* C binding of definitions if building with C++ compiler */
  58. #ifdef __cplusplus
  59. extern "C"
  60. {
  61. #endif
  62. /**
  63. *******************************************************************************
  64. ** \defgroup DmacGroup Direct Memory Access Control(DMAC)
  65. **
  66. ******************************************************************************/
  67. //@{
  68. /*******************************************************************************
  69. * Global type definitions ('typedef')
  70. ******************************************************************************/
  71. /**
  72. *******************************************************************************
  73. ** \brief DMA 通道
  74. **
  75. ******************************************************************************/
  76. typedef enum en_dma_channel
  77. {
  78. DmaCh0 = 0x00, ///< DMA 通道0
  79. DmaCh1 = 0x04, ///< DMA 通道1
  80. } en_dma_channel_t;
  81. /**
  82. *******************************************************************************
  83. ** \brief DMA 优先级
  84. **
  85. ******************************************************************************/
  86. typedef enum en_dma_priority
  87. {
  88. DmaMskPriorityFix = 0x00000000, ///< DMA 各通道优先级固定 (CH0>CH1)
  89. DmaMskPriorityLoop = 0x10000000, ///< DMA 各通道优先级采用轮询方式
  90. } en_dma_priority_t;
  91. /**
  92. *******************************************************************************
  93. ** \brief DMA 传输数据宽度
  94. **
  95. ******************************************************************************/
  96. typedef enum en_dma_transfer_width
  97. {
  98. DmaMsk8Bit = 0x00000000, ///< 8 bit 字节传输
  99. DmaMsk16Bit = 0x04000000, ///< 16 bit 半字传输
  100. DmaMsk32Bit = 0x08000000 ///< 32 bit 字传输
  101. } en_dma_transfer_width_t;
  102. /**
  103. *******************************************************************************
  104. ** \brief DMA 传输模式:块(Block)传输或者突发(Burst)传输
  105. **
  106. ******************************************************************************/
  107. typedef enum en_dma_transfer_mode
  108. {
  109. DmaMskBlock = 0x00000000, ///< 块(Block)传输
  110. DmaMskBurst = 0x10000000, ///< 突发(Burst)传输
  111. } en_dma_transfer_mode_t;
  112. /**
  113. *******************************************************************************
  114. ** \brief DMA传输当前状态
  115. **
  116. ******************************************************************************/
  117. typedef enum en_dma_stat
  118. {
  119. DmaDefault = 0U, ///< 初始值
  120. DmaAddOverflow = 1U, ///< 传输错误引起中止(地址溢出)
  121. DmaHALT = 2U, ///< 传输停止请求引起中止(外设停止请求引起的停止或者EB/DE位引起的禁止传输)
  122. DmaAccSCRErr = 3U, ///< 传输错误引起中止(传输源地址访问错误)
  123. DmaAccDestErr = 4U, ///< 传输错误引起中止(传输目的地址访问错误)
  124. DmaTransferComplete = 5U, ///< 成功传输完成
  125. DmaTransferPause = 7U, ///< 传输暂停
  126. } en_dma_stat_t;
  127. /**
  128. *******************************************************************************
  129. ** \brief DMA源地址控制模式:自增或固定
  130. **
  131. ******************************************************************************/
  132. typedef enum en_src_address_mode
  133. {
  134. DmaMskSrcAddrInc = 0x00000000, ///< 地址自增
  135. DmaMskSrcAddrFix = 0x02000000, ///< 地址固定
  136. } en_src_address_mode_t;
  137. /**
  138. *******************************************************************************
  139. ** \brief DMA目的地址控制模式:自增或固定
  140. **
  141. ******************************************************************************/
  142. typedef enum en_dst_address_mode
  143. {
  144. DmaMskDstAddrInc = 0x00000000, ///< 地址自增
  145. DmaMskDstAddrFix = 0x01000000, ///< 地址固定
  146. } en_dst_address_mode_t;
  147. /**
  148. *******************************************************************************
  149. ** \brief DMA CONFA:BC[3:0]和CONFA:TC[15:0]的重载功能
  150. **
  151. ******************************************************************************/
  152. typedef enum en_bc_tc_reload_mode
  153. {
  154. DmaMskBcTcReloadDisable = 0x00000000, ///< 禁止重载
  155. DmaMskBcTcReloadEnable = 0x00800000, ///< 使能重载
  156. } en_bc_tc_reload_mode_t;
  157. /**
  158. *******************************************************************************
  159. ** \brief DMA源地址重载功能:使能或禁止
  160. **
  161. ******************************************************************************/
  162. typedef enum en_src_address_reload_mode
  163. {
  164. DmaMskSrcAddrReloadDisable = 0x00000000, ///< 禁止DMA源地址重载
  165. DmaMskSrcAddrReloadEnable = 0x00400000, ///< 使能DMA源地址重载
  166. } en_src_address_reload_mode_t;
  167. /**
  168. *******************************************************************************
  169. ** \brief DMA目的地址重载功能:使能或禁止
  170. **
  171. ******************************************************************************/
  172. typedef enum en_dst_address_reload_mode
  173. {
  174. DmaMskDstAddrReloadDisable = 0x00000000, ///< 禁止DMA目的地址重载
  175. DmaMskDstAddrReloadEnable = 0x00200000, ///< 使能DMA目的地址重载
  176. } en_dst_address_reload_mode_t;
  177. /**
  178. *******************************************************************************
  179. ** \brief DMA 连续传输设置
  180. **
  181. ******************************************************************************/
  182. typedef enum en_dma_msk
  183. {
  184. DmaMskOneTransfer = 0x00000000, ///< 传输一次,DMAC传输完成时清除CONFA:ENS位
  185. DmaMskContinuousTransfer = 0x00000001, ///< 连续传输,DMAC传输完成时不清除CONFA:ENS位
  186. } en_dma_msk_t;
  187. /**
  188. *******************************************************************************
  189. ** \brief DMA 触发源选择
  190. **
  191. ******************************************************************************/
  192. typedef enum stc_dma_trig_sel
  193. {
  194. DmaSWTrig = 0U, ///< Select DMA software trig
  195. DmaSPI0RXTrig = 64U, ///< Select DMA hardware trig 0
  196. DmaSPI0TXTrig = 65U, ///< Select DMA hardware trig 1
  197. DmaSPI1RXTrig = 66U, ///< Select DMA hardware trig 2
  198. DmaSPI1TXTrig = 67U, ///< Select DMA hardware trig 3
  199. DmaADCJQRTrig = 68U, ///< Select DMA hardware trig 4
  200. DmaADCSQRTrig = 69U, ///< Select DMA hardware trig 5
  201. DmaLCDTxTrig = 70U, ///< Select DMA hardware trig 6
  202. DmaUart0RxTrig = 72U, ///< Select DMA hardware trig 8
  203. DmaUart0TxTrig = 73U, ///< Select DMA hardware trig 9
  204. DmaUart1RxTrig = 74U, ///< Select DMA hardware trig 10
  205. DmaUart1TxTrig = 75U, ///< Select DMA hardware trig 11
  206. DmaLpUart0RxTrig = 76U, ///< Select DMA hardware trig 12
  207. DmaLpUart0TxTrig = 77U, ///< Select DMA hardware trig 13
  208. DmaLpUart1RxTrig = 78U, ///< Select DMA hardware trig 14
  209. DmaLpUart1TxTrig = 79U, ///< Select DMA hardware trig 15
  210. DmaDAC0Trig = 80U, ///< Select DMA hardware trig 16
  211. DmaDAC1Trig = 81U, ///< Select DMA hardware trig 17
  212. DmaTIM0ATrig = 82U, ///< Select DMA hardware trig 18
  213. DmaTIM0BTrig = 83U, ///< Select DMA hardware trig 19
  214. DmaTIM1ATrig = 84U, ///< Select DMA hardware trig 20
  215. DmaTIM1BTrig = 85U, ///< Select DMA hardware trig 21
  216. DmaTIM2ATrig = 86U, ///< Select DMA hardware trig 22
  217. DmaTIM2BTrig = 87U, ///< Select DMA hardware trig 23
  218. DmaTIM3ATrig = 88U, ///< Select DMA hardware trig 24
  219. DmaTIM3BTrig = 89U, ///< Select DMA hardware trig 25
  220. DmaTIM4ATrig = 90U, ///< Select DMA hardware trig 26
  221. DmaTIM4BTrig = 91U, ///< Select DMA hardware trig 27
  222. DmaTIM5ATrig = 92U, ///< Select DMA hardware trig 28
  223. DmaTIM5BTrig = 93U, ///< Select DMA hardware trig 29
  224. DmaTIM6ATrig = 94U, ///< Select DMA hardware trig 30
  225. DmaTIM6BTrig = 95U, ///< Select DMA hardware trig 31
  226. DmaUart2RxTrig = 96U, ///< Select DMA hardware trig 32
  227. DmaUart2TxTrig = 97U, ///< Select DMA hardware trig 33
  228. DmaUart3RxTrig = 98U, ///< Select DMA hardware trig 34
  229. DmaUart3TxTrig = 99U, ///< Select DMA hardware trig 35
  230. }en_dma_trig_sel_t;
  231. /**
  232. *******************************************************************************
  233. ** \brief DMA通道初始化配置结构体
  234. **
  235. ******************************************************************************/
  236. typedef struct stc_dma_cfg
  237. {
  238. en_dma_transfer_mode_t enMode;
  239. uint16_t u16BlockSize; ///< 块传输个数
  240. uint16_t u16TransferCnt; ///< 传输块次数
  241. en_dma_transfer_width_t enTransferWidth; ///< 传输数据字节宽度 具体参考枚举定义:en_dma_transfer_width_t
  242. en_src_address_mode_t enSrcAddrMode; ///< DMA源地址控制模式:自增或固定
  243. en_dst_address_mode_t enDstAddrMode; ///< DMA目的地址控制模式:自增或固定
  244. en_src_address_reload_mode_t enSrcAddrReloadCtl; ///< 源地址重载 具体参考枚举定义:en_src_address_reload_mode_t
  245. en_dst_address_reload_mode_t enDestAddrReloadCtl;///< 目的地址重载 具体参考枚举定义:en_dst_address_reload_mode_t
  246. en_bc_tc_reload_mode_t enSrcBcTcReloadCtl; ///< Bc/Tc值重载功能 具体参考枚举定义:en_bc_tc_reload_mode_t
  247. uint32_t u32SrcAddress; ///< 源地址>
  248. uint32_t u32DstAddress; ///< 目的地址>
  249. en_dma_msk_t enTransferMode; ///DMA 连续传输设置 具体参考枚举定义:en_dma_msk_t
  250. en_dma_priority_t enPriority; ///DMA 优先级设定 具体参考枚举定义:en_dma_priority_t
  251. en_dma_trig_sel_t enRequestNum; ///<DMA 触发源选择 具体参考枚举定义:en_dma_trig_sel_t
  252. } stc_dma_cfg_t;
  253. /*******************************************************************************
  254. * Global pre-processor symbols/macros ('#define')
  255. ******************************************************************************/
  256. /*******************************************************************************
  257. * Global variable definitions ('extern')
  258. ******************************************************************************/
  259. /*******************************************************************************
  260. * Global function prototypes (definition in C source)
  261. ******************************************************************************/
  262. ///< 初始化DMAC通道
  263. en_result_t Dma_InitChannel(en_dma_channel_t enCh, stc_dma_cfg_t* pstcCfg);
  264. ///< DMA模块使能函数,使能所有通道的操作,每个通道按照各自设置工作
  265. void Dma_Enable(void);
  266. ///< DMA模块功能禁止函数,所有通道禁止工作.
  267. void Dma_Disable(void);
  268. ///< 触发指定DMA通道软件传输功能.
  269. void Dma_SwStart(en_dma_channel_t enCh);
  270. ///< 停止指定DMA通道软件传输功能.
  271. void Dma_SwStop(en_dma_channel_t enCh);
  272. ///< 使能指定dma通道的(传输完成)中断.
  273. void Dma_EnableChannelIrq(en_dma_channel_t enCh);
  274. ///< 禁用指定dma通道的(传输完成)中断.
  275. void Dma_DisableChannelIrq(en_dma_channel_t enCh);
  276. ///< 使能指定dma通道的(传输错误)中断..
  277. void Dma_EnableChannelErrIrq(en_dma_channel_t enCh);
  278. ///< 禁用指定dma通道的(传输错误)中断..
  279. void Dma_DisableChannelErrIrq(en_dma_channel_t enCh);
  280. ///< 使能指定dma通道
  281. void Dma_EnableChannel(en_dma_channel_t enCh);
  282. ///< 禁用指定dma通道
  283. void Dma_DisableChannel(en_dma_channel_t enCh);
  284. ///< 设定指定通道的块(Block)尺寸
  285. void Dma_SetBlockSize(en_dma_channel_t enCh, uint16_t u16BlkSize);
  286. ///< 设定指定通道块(Block)传输次数
  287. void Dma_SetTransferCnt(en_dma_channel_t enCh, uint16_t u16TrnCnt);
  288. ///< 允许指定通道可连续传输,即DMAC在传输完成时不清除CONFA:ENS位.
  289. void Dma_EnableContinusTranfer(en_dma_channel_t enCh);
  290. ///< 禁止指定通道连续传输,即DMAC在传输完成时清除.
  291. void Dma_DisableContinusTranfer(en_dma_channel_t enCh);
  292. ///< 暂停所有dma通道.
  293. void Dma_HaltTranfer(void);
  294. ///< 恢复(之前暂停的)所有dma通道.
  295. void Dma_RecoverTranfer(void);
  296. ///< 暂停指定dma通道.
  297. void Dma_PauseChannelTranfer(en_dma_channel_t enCh);
  298. ///< 恢复(之前暂定的)指定dma通道.
  299. void Dma_RecoverChannelTranfer(en_dma_channel_t enCh);
  300. ///< 设定指定通道传输数据宽度.
  301. void Dma_SetTransferWidth(en_dma_channel_t enCh, en_dma_transfer_width_t enWidth);
  302. ///< 设定dma通道优先级.
  303. void Dma_SetChPriority(en_dma_priority_t enPrio);
  304. ///< 获取指定DMA通道的状态.
  305. en_dma_stat_t Dma_GetStat(en_dma_channel_t enCh);
  306. ///< 清除指定DMA通道的状态值.
  307. void Dma_ClrStat(en_dma_channel_t enCh);
  308. ///<设定指定通道源地址
  309. void Dma_SetSourceAddress(en_dma_channel_t enCh, uint32_t u32Address);
  310. ///<设定指定通道目标地址.
  311. void Dma_SetDestinationAddress(en_dma_channel_t enCh, uint32_t u32Address);
  312. //@} // DmacGroup
  313. #ifdef __cplusplus
  314. }
  315. #endif
  316. #endif /* __DMAC_H__ */
  317. /*******************************************************************************
  318. * EOF (not truncated)
  319. ******************************************************************************/