hdmi_regs.h 31 KB

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  1. /*
  2. * Copyright (C) 2010-2012, Freescale Semiconductor, Inc. All Rights Reserved
  3. * THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
  4. * BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
  5. * Freescale Semiconductor, Inc.
  6. */
  7. /*!
  8. * @file hdmi_regs.h
  9. * @brief registers defination of hdmi tx module.
  10. * @ingroup diag_hdmi
  11. */
  12. #ifndef __HDMI_REGS_H__
  13. #define __HDMI_REGS_H__
  14. #include "soc_memory_map.h"
  15. // ANALOG registers
  16. #define HW_ANADIG_PLL_VIDEO ANATOP_BASE_ADDR + 0x0a0
  17. #define HW_ANADIG_PLL_VIDEO_NUM ANATOP_BASE_ADDR + 0x0b0
  18. #define HW_ANADIG_PLL_VIDEO_DENUM ANATOP_BASE_ADDR + 0x0c0
  19. // HDMI PHY REGISTERS
  20. #define CREGS_PLL_DIV_ADDR 0x06
  21. #define CREGS_PLL_GMP_CNTRL_ADDR 0x15
  22. #define CREGS_PLL_PROP_INT_CNTRL_ADDR 0x10
  23. #define CREGS_PATTERNGEN 0x1B
  24. #define CREGS_PGMODE 0x1C
  25. #define CREGS_DIGTXMODE 0x1E
  26. //
  27. // Hdmi controller registers
  28. //
  29. // Identification Registers
  30. #define HDMI_DESIGN_ID HDMI_ARB_BASE_ADDR+0x0000
  31. #define HDMI_REVISION_ID HDMI_ARB_BASE_ADDR+0x0001
  32. #define HDMI_PRODUCT_ID0 HDMI_ARB_BASE_ADDR+0x0002
  33. #define HDMI_PRODUCT_ID1 HDMI_ARB_BASE_ADDR+0x0003
  34. #define HDMI_CONFIG0_ID HDMI_ARB_BASE_ADDR+0x0004
  35. #define HDMI_CONFIG1_ID HDMI_ARB_BASE_ADDR+0x0005
  36. #define HDMI_CONFIG2_ID HDMI_ARB_BASE_ADDR+0x0006
  37. #define HDMI_CONFIG3_ID HDMI_ARB_BASE_ADDR+0x0007
  38. // Interrupt Registers
  39. #define HDMI_IH_FC_STAT0 HDMI_ARB_BASE_ADDR+0x0100
  40. #define HDMI_IH_FC_STAT1 HDMI_ARB_BASE_ADDR+0x0101
  41. #define HDMI_IH_FC_STAT2 HDMI_ARB_BASE_ADDR+0x0102
  42. #define HDMI_IH_AS_STAT0 HDMI_ARB_BASE_ADDR+0x0103
  43. #define HDMI_IH_PHY_STAT0 HDMI_ARB_BASE_ADDR+0x0104
  44. #define HDMI_IH_I2CM_STAT0 HDMI_ARB_BASE_ADDR+0x0105
  45. #define HDMI_IH_CEC_STAT0 HDMI_ARB_BASE_ADDR+0x0106
  46. #define HDMI_IH_VP_STAT0 HDMI_ARB_BASE_ADDR+0x0107
  47. #define HDMI_IH_I2CMPHY_STAT0 HDMI_ARB_BASE_ADDR+0x0108
  48. #define HDMI_IH_AHBDMAAUD_STAT0 HDMI_ARB_BASE_ADDR+0x0180
  49. #define HDMI_IH_MUTE_FC_STAT1 HDMI_ARB_BASE_ADDR+0x0181
  50. #define HDMI_IH_MUTE_FC_STAT2 HDMI_ARB_BASE_ADDR+0x0182
  51. #define HDMI_IH_MUTE_AS_STAT0 HDMI_ARB_BASE_ADDR+0x0183
  52. #define HDMI_IH_MUTE_PHY_STAT0 HDMI_ARB_BASE_ADDR+0x0184
  53. #define HDMI_IH_MUTE_I2CM_STAT0 HDMI_ARB_BASE_ADDR+0x0185
  54. #define HDMI_IH_MUTE_CEC_STAT0 HDMI_ARB_BASE_ADDR+0x0186
  55. #define HDMI_IH_MUTE_VP_STAT0 HDMI_ARB_BASE_ADDR+0x0187
  56. #define HDMI_IH_MUTE_I2CMPHY_STAT0 HDMI_ARB_BASE_ADDR+0x0188
  57. #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 HDMI_ARB_BASE_ADDR+0x0189
  58. #define HDMI_IH_MUTE HDMI_ARB_BASE_ADDR+0x01FF
  59. // Video Sample Registers
  60. #define HDMI_TX_INVID0 HDMI_ARB_BASE_ADDR+0x0200
  61. #define HDMI_TX_INSTUFFING HDMI_ARB_BASE_ADDR+0x0201
  62. #define HDMI_TX_GYDATA0 HDMI_ARB_BASE_ADDR+0x0202
  63. #define HDMI_TX_GYDATA1 HDMI_ARB_BASE_ADDR+0x0203
  64. #define HDMI_TX_RCRDATA0 HDMI_ARB_BASE_ADDR+0x0204
  65. #define HDMI_TX_RCRDATA1 HDMI_ARB_BASE_ADDR+0x0205
  66. #define HDMI_TX_BCBDATA0 HDMI_ARB_BASE_ADDR+0x0206
  67. #define HDMI_TX_BCBDATA1 HDMI_ARB_BASE_ADDR+0x0207
  68. // Video Packetizer Registers
  69. #define HDMI_VP_STATUS HDMI_ARB_BASE_ADDR+0x0800
  70. #define HDMI_VP_PR_CD HDMI_ARB_BASE_ADDR+0x0801
  71. #define HDMI_VP_STUFF HDMI_ARB_BASE_ADDR+0x0802
  72. #define HDMI_VP_REMAP HDMI_ARB_BASE_ADDR+0x0803
  73. #define HDMI_VP_CONF HDMI_ARB_BASE_ADDR+0x0804
  74. #define HDMI_VP_STAT HDMI_ARB_BASE_ADDR+0x0805
  75. #define HDMI_VP_INT HDMI_ARB_BASE_ADDR+0x0806
  76. #define HDMI_VP_MASK HDMI_ARB_BASE_ADDR+0x0807
  77. #define HDMI_VP_POL HDMI_ARB_BASE_ADDR+0x0808
  78. // Frame Composer Registers
  79. #define HDMI_FC_INVIDCONF HDMI_ARB_BASE_ADDR+0x1000
  80. #define HDMI_FC_INHACTV0 HDMI_ARB_BASE_ADDR+0x1001
  81. #define HDMI_FC_INHACTV1 HDMI_ARB_BASE_ADDR+0x1002
  82. #define HDMI_FC_INHBLANK0 HDMI_ARB_BASE_ADDR+0x1003
  83. #define HDMI_FC_INHBLANK1 HDMI_ARB_BASE_ADDR+0x1004
  84. #define HDMI_FC_INVACTV0 HDMI_ARB_BASE_ADDR+0x1005
  85. #define HDMI_FC_INVACTV1 HDMI_ARB_BASE_ADDR+0x1006
  86. #define HDMI_FC_INVBLANK HDMI_ARB_BASE_ADDR+0x1007
  87. #define HDMI_FC_HSYNCINDELAY0 HDMI_ARB_BASE_ADDR+0x1008
  88. #define HDMI_FC_HSYNCINDELAY1 HDMI_ARB_BASE_ADDR+0x1009
  89. #define HDMI_FC_HSYNCINWIDTH0 HDMI_ARB_BASE_ADDR+0x100A
  90. #define HDMI_FC_HSYNCINWIDTH1 HDMI_ARB_BASE_ADDR+0x100B
  91. #define HDMI_FC_VSYNCINDELAY HDMI_ARB_BASE_ADDR+0x100C
  92. #define HDMI_FC_VSYNCINWIDTH HDMI_ARB_BASE_ADDR+0x100D
  93. #define HDMI_FC_INFREQ0 HDMI_ARB_BASE_ADDR+0x100E
  94. #define HDMI_FC_INFREQ1 HDMI_ARB_BASE_ADDR+0x100F
  95. #define HDMI_FC_INFREQ2 HDMI_ARB_BASE_ADDR+0x1010
  96. #define HDMI_FC_CTRLDUR HDMI_ARB_BASE_ADDR+0x1011
  97. #define HDMI_FC_EXCTRLDUR HDMI_ARB_BASE_ADDR+0x1012
  98. #define HDMI_FC_EXCTRLSPAC HDMI_ARB_BASE_ADDR+0x1013
  99. #define HDMI_FC_CH0PREAM HDMI_ARB_BASE_ADDR+0x1014
  100. #define HDMI_FC_CH1PREAM HDMI_ARB_BASE_ADDR+0x1015
  101. #define HDMI_FC_CH2PREAM HDMI_ARB_BASE_ADDR+0x1016
  102. #define HDMI_FC_AVICONF3 HDMI_ARB_BASE_ADDR+0x1017
  103. #define HDMI_FC_GCP HDMI_ARB_BASE_ADDR+0x1018
  104. #define HDMI_FC_AVICONF0 HDMI_ARB_BASE_ADDR+0x1019
  105. #define HDMI_FC_AVICONF1 HDMI_ARB_BASE_ADDR+0x101A
  106. #define HDMI_FC_AVICONF2 HDMI_ARB_BASE_ADDR+0x101B
  107. #define HDMI_FC_AVIVID HDMI_ARB_BASE_ADDR+0x101C
  108. #define HDMI_FC_AVIETB0 HDMI_ARB_BASE_ADDR+0x101D
  109. #define HDMI_FC_AVIETB1 HDMI_ARB_BASE_ADDR+0x101E
  110. #define HDMI_FC_AVISBB0 HDMI_ARB_BASE_ADDR+0x101F
  111. #define HDMI_FC_AVISBB1 HDMI_ARB_BASE_ADDR+0x1020
  112. #define HDMI_FC_AVIELB0 HDMI_ARB_BASE_ADDR+0x1021
  113. #define HDMI_FC_AVIELB1 HDMI_ARB_BASE_ADDR+0x1022
  114. #define HDMI_FC_AVISRB0 HDMI_ARB_BASE_ADDR+0x1023
  115. #define HDMI_FC_AVISRB1 HDMI_ARB_BASE_ADDR+0x1024
  116. #define HDMI_FC_AUDICONF0 HDMI_ARB_BASE_ADDR+0x1025
  117. #define HDMI_FC_AUDICONF1 HDMI_ARB_BASE_ADDR+0x1026
  118. #define HDMI_FC_AUDICONF2 HDMI_ARB_BASE_ADDR+0x1027
  119. #define HDMI_FC_AUDICONF3 HDMI_ARB_BASE_ADDR+0x1028
  120. #define HDMI_FC_VSDIEEEID0 HDMI_ARB_BASE_ADDR+0x1029
  121. #define HDMI_FC_VSDSIZE HDMI_ARB_BASE_ADDR+0x102A
  122. #define HDMI_FC_VSDIEEEID1 HDMI_ARB_BASE_ADDR+0x1030
  123. #define HDMI_FC_VSDIEEEID2 HDMI_ARB_BASE_ADDR+0x1031
  124. #define HDMI_FC_VSDPAYLOAD0 HDMI_ARB_BASE_ADDR+0x1032
  125. #define HDMI_FC_VSDPAYLOAD1 HDMI_ARB_BASE_ADDR+0x1033
  126. #define HDMI_FC_VSDPAYLOAD2 HDMI_ARB_BASE_ADDR+0x1034
  127. #define HDMI_FC_VSDPAYLOAD3 HDMI_ARB_BASE_ADDR+0x1035
  128. #define HDMI_FC_VSDPAYLOAD4 HDMI_ARB_BASE_ADDR+0x1036
  129. #define HDMI_FC_VSDPAYLOAD5 HDMI_ARB_BASE_ADDR+0x1037
  130. #define HDMI_FC_VSDPAYLOAD6 HDMI_ARB_BASE_ADDR+0x1038
  131. #define HDMI_FC_VSDPAYLOAD7 HDMI_ARB_BASE_ADDR+0x1039
  132. #define HDMI_FC_VSDPAYLOAD8 HDMI_ARB_BASE_ADDR+0x103A
  133. #define HDMI_FC_VSDPAYLOAD9 HDMI_ARB_BASE_ADDR+0x103B
  134. #define HDMI_FC_VSDPAYLOAD10 HDMI_ARB_BASE_ADDR+0x103C
  135. #define HDMI_FC_VSDPAYLOAD11 HDMI_ARB_BASE_ADDR+0x103D
  136. #define HDMI_FC_VSDPAYLOAD12 HDMI_ARB_BASE_ADDR+0x103E
  137. #define HDMI_FC_VSDPAYLOAD13 HDMI_ARB_BASE_ADDR+0x103F
  138. #define HDMI_FC_VSDPAYLOAD14 HDMI_ARB_BASE_ADDR+0x1040
  139. #define HDMI_FC_VSDPAYLOAD15 HDMI_ARB_BASE_ADDR+0x1041
  140. #define HDMI_FC_VSDPAYLOAD16 HDMI_ARB_BASE_ADDR+0x1042
  141. #define HDMI_FC_VSDPAYLOAD17 HDMI_ARB_BASE_ADDR+0x1043
  142. #define HDMI_FC_VSDPAYLOAD18 HDMI_ARB_BASE_ADDR+0x1044
  143. #define HDMI_FC_VSDPAYLOAD19 HDMI_ARB_BASE_ADDR+0x1045
  144. #define HDMI_FC_VSDPAYLOAD20 HDMI_ARB_BASE_ADDR+0x1046
  145. #define HDMI_FC_VSDPAYLOAD21 HDMI_ARB_BASE_ADDR+0x1047
  146. #define HDMI_FC_VSDPAYLOAD22 HDMI_ARB_BASE_ADDR+0x1048
  147. #define HDMI_FC_VSDPAYLOAD23 HDMI_ARB_BASE_ADDR+0x1049
  148. #define HDMI_FC_SPDVENDORNAME0 HDMI_ARB_BASE_ADDR+0x104A
  149. #define HDMI_FC_SPDVENDORNAME1 HDMI_ARB_BASE_ADDR+0x104B
  150. #define HDMI_FC_SPDVENDORNAME2 HDMI_ARB_BASE_ADDR+0x104C
  151. #define HDMI_FC_SPDVENDORNAME3 HDMI_ARB_BASE_ADDR+0x104D
  152. #define HDMI_FC_SPDVENDORNAME4 HDMI_ARB_BASE_ADDR+0x104E
  153. #define HDMI_FC_SPDVENDORNAME5 HDMI_ARB_BASE_ADDR+0x104F
  154. #define HDMI_FC_SPDVENDORNAME6 HDMI_ARB_BASE_ADDR+0x1050
  155. #define HDMI_FC_SPDVENDORNAME7 HDMI_ARB_BASE_ADDR+0x1051
  156. #define HDMI_FC_SDPPRODUCTNAME0 HDMI_ARB_BASE_ADDR+0x1052
  157. #define HDMI_FC_SDPPRODUCTNAME1 HDMI_ARB_BASE_ADDR+0x1053
  158. #define HDMI_FC_SDPPRODUCTNAME2 HDMI_ARB_BASE_ADDR+0x1054
  159. #define HDMI_FC_SDPPRODUCTNAME3 HDMI_ARB_BASE_ADDR+0x1055
  160. #define HDMI_FC_SDPPRODUCTNAME4 HDMI_ARB_BASE_ADDR+0x1056
  161. #define HDMI_FC_SDPPRODUCTNAME5 HDMI_ARB_BASE_ADDR+0x1057
  162. #define HDMI_FC_SDPPRODUCTNAME6 HDMI_ARB_BASE_ADDR+0x1058
  163. #define HDMI_FC_SDPPRODUCTNAME7 HDMI_ARB_BASE_ADDR+0x1059
  164. #define HDMI_FC_SDPPRODUCTNAME8 HDMI_ARB_BASE_ADDR+0x105A
  165. #define HDMI_FC_SDPPRODUCTNAME9 HDMI_ARB_BASE_ADDR+0x105B
  166. #define HDMI_FC_SDPPRODUCTNAME10 HDMI_ARB_BASE_ADDR+0x105C
  167. #define HDMI_FC_SDPPRODUCTNAME11 HDMI_ARB_BASE_ADDR+0x105D
  168. #define HDMI_FC_SDPPRODUCTNAME12 HDMI_ARB_BASE_ADDR+0x105E
  169. #define HDMI_FC_SDPPRODUCTNAME13 HDMI_ARB_BASE_ADDR+0x105F
  170. #define HDMI_FC_SDPPRODUCTNAME14 HDMI_ARB_BASE_ADDR+0x1060
  171. #define HDMI_FC_SPDPRODUCTNAME15 HDMI_ARB_BASE_ADDR+0x1061
  172. #define HDMI_FC_SPDDEVICEINF HDMI_ARB_BASE_ADDR+0x1062
  173. #define HDMI_FC_AUDSCONF HDMI_ARB_BASE_ADDR+0x1063
  174. #define HDMI_FC_AUDSSTAT HDMI_ARB_BASE_ADDR+0x1064
  175. #define HDMI_FC_AUDSV HDMI_ARB_BASE_ADDR+0x1065
  176. #define HDMI_FC_AUDSU HDMI_ARB_BASE_ADDR+0x1066
  177. #define HDMI_FC_AUDSCHNLS0 HDMI_ARB_BASE_ADDR+0x1067
  178. #define HDMI_FC_AUDSCHNLS1 HDMI_ARB_BASE_ADDR+0x1068
  179. #define HDMI_FC_AUDSCHNLS2 HDMI_ARB_BASE_ADDR+0x1069
  180. #define HDMI_FC_AUDSCHNLS3 HDMI_ARB_BASE_ADDR+0x106A
  181. #define HDMI_FC_AUDSCHNLS4 HDMI_ARB_BASE_ADDR+0x106B
  182. #define HDMI_FC_AUDSCHNLS5 HDMI_ARB_BASE_ADDR+0x106C
  183. #define HDMI_FC_AUDSCHNLS6 HDMI_ARB_BASE_ADDR+0x106D
  184. #define HDMI_FC_AUDSCHNLS7 HDMI_ARB_BASE_ADDR+0x106E
  185. #define HDMI_FC_AUDSCHNLS8 HDMI_ARB_BASE_ADDR+0x106F
  186. #define HDMI_FC_DATACH0FILL HDMI_ARB_BASE_ADDR+0x1070
  187. #define HDMI_FC_DATACH1FILL HDMI_ARB_BASE_ADDR+0x1071
  188. #define HDMI_FC_DATACH2FILL HDMI_ARB_BASE_ADDR+0x1072
  189. #define HDMI_FC_CTRLQHIGH HDMI_ARB_BASE_ADDR+0x1073
  190. #define HDMI_FC_CTRLQLOW HDMI_ARB_BASE_ADDR+0x1074
  191. #define HDMI_FC_ACP0 HDMI_ARB_BASE_ADDR+0x1075
  192. #define HDMI_FC_ACP28 HDMI_ARB_BASE_ADDR+0x1076
  193. #define HDMI_FC_ACP27 HDMI_ARB_BASE_ADDR+0x1077
  194. #define HDMI_FC_ACP26 HDMI_ARB_BASE_ADDR+0x1078
  195. #define HDMI_FC_ACP25 HDMI_ARB_BASE_ADDR+0x1079
  196. #define HDMI_FC_ACP24 HDMI_ARB_BASE_ADDR+0x107A
  197. #define HDMI_FC_ACP23 HDMI_ARB_BASE_ADDR+0x107B
  198. #define HDMI_FC_ACP22 HDMI_ARB_BASE_ADDR+0x107C
  199. #define HDMI_FC_ACP21 HDMI_ARB_BASE_ADDR+0x107D
  200. #define HDMI_FC_ACP20 HDMI_ARB_BASE_ADDR+0x107E
  201. #define HDMI_FC_ACP19 HDMI_ARB_BASE_ADDR+0x107F
  202. #define HDMI_FC_ACP18 HDMI_ARB_BASE_ADDR+0x1080
  203. #define HDMI_FC_ACP17 HDMI_ARB_BASE_ADDR+0x1081
  204. #define HDMI_FC_ACP16 HDMI_ARB_BASE_ADDR+0x1082
  205. #define HDMI_FC_ACP15 HDMI_ARB_BASE_ADDR+0x1083
  206. #define HDMI_FC_ACP14 HDMI_ARB_BASE_ADDR+0x1084
  207. #define HDMI_FC_ACP13 HDMI_ARB_BASE_ADDR+0x1085
  208. #define HDMI_FC_ACP12 HDMI_ARB_BASE_ADDR+0x1086
  209. #define HDMI_FC_ACP11 HDMI_ARB_BASE_ADDR+0x1087
  210. #define HDMI_FC_ACP10 HDMI_ARB_BASE_ADDR+0x1088
  211. #define HDMI_FC_ACP9 HDMI_ARB_BASE_ADDR+0x1089
  212. #define HDMI_FC_ACP8 HDMI_ARB_BASE_ADDR+0x108A
  213. #define HDMI_FC_ACP7 HDMI_ARB_BASE_ADDR+0x108B
  214. #define HDMI_FC_ACP6 HDMI_ARB_BASE_ADDR+0x108C
  215. #define HDMI_FC_ACP5 HDMI_ARB_BASE_ADDR+0x108D
  216. #define HDMI_FC_ACP4 HDMI_ARB_BASE_ADDR+0x108E
  217. #define HDMI_FC_ACP3 HDMI_ARB_BASE_ADDR+0x108F
  218. #define HDMI_FC_ACP2 HDMI_ARB_BASE_ADDR+0x1090
  219. #define HDMI_FC_ACP1 HDMI_ARB_BASE_ADDR+0x1091
  220. #define HDMI_FC_ISCR1_0 HDMI_ARB_BASE_ADDR+0x1092
  221. #define HDMI_FC_ISCR1_16 HDMI_ARB_BASE_ADDR+0x1093
  222. #define HDMI_FC_ISCR1_15 HDMI_ARB_BASE_ADDR+0x1094
  223. #define HDMI_FC_ISCR1_14 HDMI_ARB_BASE_ADDR+0x1095
  224. #define HDMI_FC_ISCR1_13 HDMI_ARB_BASE_ADDR+0x1096
  225. #define HDMI_FC_ISCR1_12 HDMI_ARB_BASE_ADDR+0x1097
  226. #define HDMI_FC_ISCR1_11 HDMI_ARB_BASE_ADDR+0x1098
  227. #define HDMI_FC_ISCR1_10 HDMI_ARB_BASE_ADDR+0x1099
  228. #define HDMI_FC_ISCR1_9 HDMI_ARB_BASE_ADDR+0x109A
  229. #define HDMI_FC_ISCR1_8 HDMI_ARB_BASE_ADDR+0x109B
  230. #define HDMI_FC_ISCR1_7 HDMI_ARB_BASE_ADDR+0x109C
  231. #define HDMI_FC_ISCR1_6 HDMI_ARB_BASE_ADDR+0x109D
  232. #define HDMI_FC_ISCR1_5 HDMI_ARB_BASE_ADDR+0x109E
  233. #define HDMI_FC_ISCR1_4 HDMI_ARB_BASE_ADDR+0x109F
  234. #define HDMI_FC_ISCR1_3 HDMI_ARB_BASE_ADDR+0x10A0
  235. #define HDMI_FC_ISCR1_2 HDMI_ARB_BASE_ADDR+0x10A1
  236. #define HDMI_FC_ISCR1_1 HDMI_ARB_BASE_ADDR+0x10A2
  237. #define HDMI_FC_ISCR2_15 HDMI_ARB_BASE_ADDR+0x10A3
  238. #define HDMI_FC_ISCR2_14 HDMI_ARB_BASE_ADDR+0x10A4
  239. #define HDMI_FC_ISCR2_13 HDMI_ARB_BASE_ADDR+0x10A5
  240. #define HDMI_FC_ISCR2_12 HDMI_ARB_BASE_ADDR+0x10A6
  241. #define HDMI_FC_ISCR2_11 HDMI_ARB_BASE_ADDR+0x10A7
  242. #define HDMI_FC_ISCR2_10 HDMI_ARB_BASE_ADDR+0x10A8
  243. #define HDMI_FC_ISCR2_9 HDMI_ARB_BASE_ADDR+0x10A9
  244. #define HDMI_FC_ISCR2_8 HDMI_ARB_BASE_ADDR+0x10AA
  245. #define HDMI_FC_ISCR2_7 HDMI_ARB_BASE_ADDR+0x10AB
  246. #define HDMI_FC_ISCR2_6 HDMI_ARB_BASE_ADDR+0x10AC
  247. #define HDMI_FC_ISCR2_5 HDMI_ARB_BASE_ADDR+0x10AD
  248. #define HDMI_FC_ISCR2_4 HDMI_ARB_BASE_ADDR+0x10AE
  249. #define HDMI_FC_ISCR2_3 HDMI_ARB_BASE_ADDR+0x10AF
  250. #define HDMI_FC_ISCR2_2 HDMI_ARB_BASE_ADDR+0x10B0
  251. #define HDMI_FC_ISCR2_1 HDMI_ARB_BASE_ADDR+0x10B1
  252. #define HDMI_FC_ISCR2_0 HDMI_ARB_BASE_ADDR+0x10B2
  253. #define HDMI_FC_DATAUTO0 HDMI_ARB_BASE_ADDR+0x10B3
  254. #define HDMI_FC_DATAUTO1 HDMI_ARB_BASE_ADDR+0x10B4
  255. #define HDMI_FC_DATAUTO2 HDMI_ARB_BASE_ADDR+0x10B5
  256. #define HDMI_FC_DATMAN HDMI_ARB_BASE_ADDR+0x10B6
  257. #define HDMI_FC_DATAUTO3 HDMI_ARB_BASE_ADDR+0x10B7
  258. #define HDMI_FC_RDRB0 HDMI_ARB_BASE_ADDR+0x10B8
  259. #define HDMI_FC_RDRB1 HDMI_ARB_BASE_ADDR+0x10B9
  260. #define HDMI_FC_RDRB2 HDMI_ARB_BASE_ADDR+0x10BA
  261. #define HDMI_FC_RDRB3 HDMI_ARB_BASE_ADDR+0x10BB
  262. #define HDMI_FC_RDRB4 HDMI_ARB_BASE_ADDR+0x10BC
  263. #define HDMI_FC_RDRB5 HDMI_ARB_BASE_ADDR+0x10BD
  264. #define HDMI_FC_RDRB6 HDMI_ARB_BASE_ADDR+0x10BE
  265. #define HDMI_FC_RDRB7 HDMI_ARB_BASE_ADDR+0x10BF
  266. #define HDMI_FC_STAT0 HDMI_ARB_BASE_ADDR+0x10D0
  267. #define HDMI_FC_INT0 HDMI_ARB_BASE_ADDR+0x10D1
  268. #define HDMI_FC_MASK0 HDMI_ARB_BASE_ADDR+0x10D2
  269. #define HDMI_FC_POL0 HDMI_ARB_BASE_ADDR+0x10D3
  270. #define HDMI_FC_STAT1 HDMI_ARB_BASE_ADDR+0x10D4
  271. #define HDMI_FC_INT1 HDMI_ARB_BASE_ADDR+0x10D5
  272. #define HDMI_FC_MASK1 HDMI_ARB_BASE_ADDR+0x10D6
  273. #define HDMI_FC_POL1 HDMI_ARB_BASE_ADDR+0x10D7
  274. #define HDMI_FC_STAT2 HDMI_ARB_BASE_ADDR+0x10D8
  275. #define HDMI_FC_INT2 HDMI_ARB_BASE_ADDR+0x10D9
  276. #define HDMI_FC_MASK2 HDMI_ARB_BASE_ADDR+0x10DA
  277. #define HDMI_FC_POL2 HDMI_ARB_BASE_ADDR+0x10DB
  278. #define HDMI_FC_PRCONF HDMI_ARB_BASE_ADDR+0x10E0
  279. #define HDMI_FC_GMD_STAT HDMI_ARB_BASE_ADDR+0x1100
  280. #define HDMI_FC_GMD_EN HDMI_ARB_BASE_ADDR+0x1101
  281. #define HDMI_FC_GMD_UP HDMI_ARB_BASE_ADDR+0x1102
  282. #define HDMI_FC_GMD_CONF HDMI_ARB_BASE_ADDR+0x1103
  283. #define HDMI_FC_GMD_HB HDMI_ARB_BASE_ADDR+0x1104
  284. #define HDMI_FC_GMD_PB0 HDMI_ARB_BASE_ADDR+0x1105
  285. #define HDMI_FC_GMD_PB1 HDMI_ARB_BASE_ADDR+0x1106
  286. #define HDMI_FC_GMD_PB2 HDMI_ARB_BASE_ADDR+0x1107
  287. #define HDMI_FC_GMD_PB3 HDMI_ARB_BASE_ADDR+0x1108
  288. #define HDMI_FC_GMD_PB4 HDMI_ARB_BASE_ADDR+0x1109
  289. #define HDMI_FC_GMD_PB5 HDMI_ARB_BASE_ADDR+0x110A
  290. #define HDMI_FC_GMD_PB6 HDMI_ARB_BASE_ADDR+0x110B
  291. #define HDMI_FC_GMD_PB7 HDMI_ARB_BASE_ADDR+0x110C
  292. #define HDMI_FC_GMD_PB8 HDMI_ARB_BASE_ADDR+0x110D
  293. #define HDMI_FC_GMD_PB9 HDMI_ARB_BASE_ADDR+0x110E
  294. #define HDMI_FC_GMD_PB10 HDMI_ARB_BASE_ADDR+0x110F
  295. #define HDMI_FC_GMD_PB11 HDMI_ARB_BASE_ADDR+0x1110
  296. #define HDMI_FC_GMD_PB12 HDMI_ARB_BASE_ADDR+0x1111
  297. #define HDMI_FC_GMD_PB13 HDMI_ARB_BASE_ADDR+0x1112
  298. #define HDMI_FC_GMD_PB14 HDMI_ARB_BASE_ADDR+0x1113
  299. #define HDMI_FC_GMD_PB15 HDMI_ARB_BASE_ADDR+0x1114
  300. #define HDMI_FC_GMD_PB16 HDMI_ARB_BASE_ADDR+0x1115
  301. #define HDMI_FC_GMD_PB17 HDMI_ARB_BASE_ADDR+0x1116
  302. #define HDMI_FC_GMD_PB18 HDMI_ARB_BASE_ADDR+0x1117
  303. #define HDMI_FC_GMD_PB19 HDMI_ARB_BASE_ADDR+0x1118
  304. #define HDMI_FC_GMD_PB20 HDMI_ARB_BASE_ADDR+0x1119
  305. #define HDMI_FC_GMD_PB21 HDMI_ARB_BASE_ADDR+0x111A
  306. #define HDMI_FC_GMD_PB22 HDMI_ARB_BASE_ADDR+0x111B
  307. #define HDMI_FC_GMD_PB23 HDMI_ARB_BASE_ADDR+0x111C
  308. #define HDMI_FC_GMD_PB24 HDMI_ARB_BASE_ADDR+0x111D
  309. #define HDMI_FC_GMD_PB25 HDMI_ARB_BASE_ADDR+0x111E
  310. #define HDMI_FC_GMD_PB26 HDMI_ARB_BASE_ADDR+0x111F
  311. #define HDMI_FC_GMD_PB27 HDMI_ARB_BASE_ADDR+0x1120
  312. #define HDMI_FC_DBGFORCE HDMI_ARB_BASE_ADDR+0x1200
  313. #define HDMI_FC_DBGAUD0CH0 HDMI_ARB_BASE_ADDR+0x1201
  314. #define HDMI_FC_DBGAUD1CH0 HDMI_ARB_BASE_ADDR+0x1202
  315. #define HDMI_FC_DBGAUD2CH0 HDMI_ARB_BASE_ADDR+0x1203
  316. #define HDMI_FC_DBGAUD0CH1 HDMI_ARB_BASE_ADDR+0x1204
  317. #define HDMI_FC_DBGAUD1CH1 HDMI_ARB_BASE_ADDR+0x1205
  318. #define HDMI_FC_DBGAUD2CH1 HDMI_ARB_BASE_ADDR+0x1206
  319. #define HDMI_FC_DBGAUD0CH2 HDMI_ARB_BASE_ADDR+0x1207
  320. #define HDMI_FC_DBGAUD1CH2 HDMI_ARB_BASE_ADDR+0x1208
  321. #define HDMI_FC_DBGAUD2CH2 HDMI_ARB_BASE_ADDR+0x1209
  322. #define HDMI_FC_DBGAUD0CH3 HDMI_ARB_BASE_ADDR+0x120A
  323. #define HDMI_FC_DBGAUD1CH3 HDMI_ARB_BASE_ADDR+0x120B
  324. #define HDMI_FC_DBGAUD2CH3 HDMI_ARB_BASE_ADDR+0x120C
  325. #define HDMI_FC_DBGAUD0CH4 HDMI_ARB_BASE_ADDR+0x120D
  326. #define HDMI_FC_DBGAUD1CH4 HDMI_ARB_BASE_ADDR+0x120E
  327. #define HDMI_FC_DBGAUD2CH4 HDMI_ARB_BASE_ADDR+0x120F
  328. #define HDMI_FC_DBGAUD0CH5 HDMI_ARB_BASE_ADDR+0x1210
  329. #define HDMI_FC_DBGAUD1CH5 HDMI_ARB_BASE_ADDR+0x1211
  330. #define HDMI_FC_DBGAUD2CH5 HDMI_ARB_BASE_ADDR+0x1212
  331. #define HDMI_FC_DBGAUD0CH6 HDMI_ARB_BASE_ADDR+0x1213
  332. #define HDMI_FC_DBGAUD1CH6 HDMI_ARB_BASE_ADDR+0x1214
  333. #define HDMI_FC_DBGAUD2CH6 HDMI_ARB_BASE_ADDR+0x1215
  334. #define HDMI_FC_DBGAUD0CH7 HDMI_ARB_BASE_ADDR+0x1216
  335. #define HDMI_FC_DBGAUD1CH7 HDMI_ARB_BASE_ADDR+0x1217
  336. #define HDMI_FC_DBGAUD2CH7 HDMI_ARB_BASE_ADDR+0x1218
  337. #define HDMI_FC_DBGTMDS0 HDMI_ARB_BASE_ADDR+0x1219
  338. #define HDMI_FC_DBGTMDS1 HDMI_ARB_BASE_ADDR+0x121A
  339. #define HDMI_FC_DBGTMDS2 HDMI_ARB_BASE_ADDR+0x121B
  340. // HDMI Source PHY Registers
  341. #define HDMI_PHY_CONF0 HDMI_ARB_BASE_ADDR+0x3000
  342. #define HDMI_PHY_TST0 HDMI_ARB_BASE_ADDR+0x3001
  343. #define HDMI_PHY_TST1 HDMI_ARB_BASE_ADDR+0x3002
  344. #define HDMI_PHY_TST2 HDMI_ARB_BASE_ADDR+0x3003
  345. #define HDMI_PHY_STAT0 HDMI_ARB_BASE_ADDR+0x3004
  346. #define HDMI_PHY_INT0 HDMI_ARB_BASE_ADDR+0x3005
  347. #define HDMI_PHY_MASK0 HDMI_ARB_BASE_ADDR+0x3006
  348. #define HDMI_PHY_POL0 HDMI_ARB_BASE_ADDR+0x3007
  349. // HDMI Master PHY Registers
  350. #define HDMI_PHY_I2CM_SLAVE_ADDR HDMI_ARB_BASE_ADDR+0x3020
  351. #define HDMI_PHY_I2CM_ADDRESS_ADDR HDMI_ARB_BASE_ADDR+0x3021
  352. #define HDMI_PHY_I2CM_DATAO_1_ADDR HDMI_ARB_BASE_ADDR+0x3022
  353. #define HDMI_PHY_I2CM_DATAO_0_ADDR HDMI_ARB_BASE_ADDR+0x3023
  354. #define HDMI_PHY_I2CM_DATAI_1_ADDR HDMI_ARB_BASE_ADDR+0x3024
  355. #define HDMI_PHY_I2CM_DATAI_0_ADDR HDMI_ARB_BASE_ADDR+0x3025
  356. #define HDMI_PHY_I2CM_OPERATION_ADDR HDMI_ARB_BASE_ADDR+0x3026
  357. #define HDMI_PHY_I2CM_INT_ADDR HDMI_ARB_BASE_ADDR+0x3027
  358. #define HDMI_PHY_I2CM_CTLINT_ADDR HDMI_ARB_BASE_ADDR+0x3028
  359. #define HDMI_PHY_I2CM_DIV_ADDR HDMI_ARB_BASE_ADDR+0x3029
  360. #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR HDMI_ARB_BASE_ADDR+0x302a
  361. #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x302b
  362. #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x302c
  363. #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x302d
  364. #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x302e
  365. #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x302f
  366. #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x3030
  367. #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x3031
  368. #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x3032
  369. // Generic Parallel Audio Interface Registers
  370. #define HDMI_GP_CONF0 HDMI_ARB_BASE_ADDR+0x3500
  371. #define HDMI_GP_CONF1 HDMI_ARB_BASE_ADDR+0x3501
  372. #define HDMI_GP_CONF2 HDMI_ARB_BASE_ADDR+0x3502
  373. #define HDMI_GP_STAT HDMI_ARB_BASE_ADDR+0x3503
  374. #define HDMI_GP_INT HDMI_ARB_BASE_ADDR+0x3504
  375. #define HDMI_GP_MASK HDMI_ARB_BASE_ADDR+0x3505
  376. #define HDMI_GP_POL HDMI_ARB_BASE_ADDR+0x3506
  377. // Audio DMA Registers (TBD)
  378. #define HDMI_AHB_DMA_CONF0 HDMI_ARB_BASE_ADDR+0x3600
  379. #define HDMI_AHB_DMA_START HDMI_ARB_BASE_ADDR+0x3601
  380. #define HDMI_AHB_DMA_STOP HDMI_ARB_BASE_ADDR+0x3602
  381. #define HDMI_AHB_DMA_THRSLD HDMI_ARB_BASE_ADDR+0x3603
  382. #define HDMI_AHB_DMA_STRADDR0 HDMI_ARB_BASE_ADDR+0x3604
  383. #define HDMI_AHB_DMA_STRADDR1 HDMI_ARB_BASE_ADDR+0x3605
  384. #define HDMI_AHB_DMA_STRADDR2 HDMI_ARB_BASE_ADDR+0x3606
  385. #define HDMI_AHB_DMA_STRADDR3 HDMI_ARB_BASE_ADDR+0x3607
  386. #define HDMI_AHB_DMA_STPADDR0 HDMI_ARB_BASE_ADDR+0x3608
  387. #define HDMI_AHB_DMA_STPADDR1 HDMI_ARB_BASE_ADDR+0x3609
  388. #define HDMI_AHB_DMA_STPADDR2 HDMI_ARB_BASE_ADDR+0x360a
  389. #define HDMI_AHB_DMA_STPADDR3 HDMI_ARB_BASE_ADDR+0x360b
  390. #define HDMI_AHB_DMA_BSTADDR0 HDMI_ARB_BASE_ADDR+0x360c
  391. #define HDMI_AHB_DMA_BSTADDR1 HDMI_ARB_BASE_ADDR+0x360d
  392. #define HDMI_AHB_DMA_BSTADDR2 HDMI_ARB_BASE_ADDR+0x360e
  393. #define HDMI_AHB_DMA_BSTADDR3 HDMI_ARB_BASE_ADDR+0x360f
  394. #define HDMI_AHB_DMA_MBLENGTH0 HDMI_ARB_BASE_ADDR+0x3610
  395. #define HDMI_AHB_DMA_MBLENGTH1 HDMI_ARB_BASE_ADDR+0x3611
  396. #define HDMI_AHB_DMA_STAT HDMI_ARB_BASE_ADDR+0x3612
  397. #define HDMI_AHB_DMA_INT HDMI_ARB_BASE_ADDR+0x3613
  398. #define HDMI_AHB_DMA_MASK HDMI_ARB_BASE_ADDR+0x3614
  399. #define HDMI_AHB_DMA_POL HDMI_ARB_BASE_ADDR+0x3615
  400. // Main Controller Registers
  401. #define HDMI_MC_SFRDIV HDMI_ARB_BASE_ADDR+0x4000
  402. #define HDMI_MC_CLKDIS HDMI_ARB_BASE_ADDR+0x4001
  403. #define HDMI_MC_SWRSTZ HDMI_ARB_BASE_ADDR+0x4002
  404. #define HDMI_MC_OPCTRL HDMI_ARB_BASE_ADDR+0x4003
  405. #define HDMI_MC_FLOWCTRL HDMI_ARB_BASE_ADDR+0x4004
  406. #define HDMI_MC_PHYRSTZ HDMI_ARB_BASE_ADDR+0x4005
  407. #define HDMI_MC_LOCKONCLOCK HDMI_ARB_BASE_ADDR+0x4006
  408. #define HDMI_MC_HEACPHY_RST HDMI_ARB_BASE_ADDR+0x4007
  409. // Color Space Converter Registers
  410. #define HDMI_CSC_CFG HDMI_ARB_BASE_ADDR+0x4100
  411. #define HDMI_CSC_SCALE HDMI_ARB_BASE_ADDR+0x4101
  412. #define HDMI_CSC_COEF_A1_MSB HDMI_ARB_BASE_ADDR+0x4102
  413. #define HDMI_CSC_COEF_A1_LSB HDMI_ARB_BASE_ADDR+0x4103
  414. #define HDMI_CSC_COEF_A2_MSB HDMI_ARB_BASE_ADDR+0x4104
  415. #define HDMI_CSC_COEF_A2_LSB HDMI_ARB_BASE_ADDR+0x4105
  416. #define HDMI_CSC_COEF_A3_MSB HDMI_ARB_BASE_ADDR+0x4106
  417. #define HDMI_CSC_COEF_A3_LSB HDMI_ARB_BASE_ADDR+0x4107
  418. #define HDMI_CSC_COEF_A4_MSB HDMI_ARB_BASE_ADDR+0x4108
  419. #define HDMI_CSC_COEF_A4_LSB HDMI_ARB_BASE_ADDR+0x4109
  420. #define HDMI_CSC_COEF_B1_MSB HDMI_ARB_BASE_ADDR+0x410A
  421. #define HDMI_CSC_COEF_B1_LSB HDMI_ARB_BASE_ADDR+0x410B
  422. #define HDMI_CSC_COEF_B2_MSB HDMI_ARB_BASE_ADDR+0x410C
  423. #define HDMI_CSC_COEF_B2_LSB HDMI_ARB_BASE_ADDR+0x410D
  424. #define HDMI_CSC_COEF_B3_MSB HDMI_ARB_BASE_ADDR+0x410E
  425. #define HDMI_CSC_COEF_B3_LSB HDMI_ARB_BASE_ADDR+0x410F
  426. #define HDMI_CSC_COEF_B4_MSB HDMI_ARB_BASE_ADDR+0x4110
  427. #define HDMI_CSC_COEF_B4_LSB HDMI_ARB_BASE_ADDR+0x4111
  428. #define HDMI_CSC_COEF_C1_MSB HDMI_ARB_BASE_ADDR+0x4112
  429. #define HDMI_CSC_COEF_C1_LSB HDMI_ARB_BASE_ADDR+0x4113
  430. #define HDMI_CSC_COEF_C2_MSB HDMI_ARB_BASE_ADDR+0x4114
  431. #define HDMI_CSC_COEF_C2_LSB HDMI_ARB_BASE_ADDR+0x4115
  432. #define HDMI_CSC_COEF_C3_MSB HDMI_ARB_BASE_ADDR+0x4116
  433. #define HDMI_CSC_COEF_C3_LSB HDMI_ARB_BASE_ADDR+0x4117
  434. #define HDMI_CSC_COEF_C4_MSB HDMI_ARB_BASE_ADDR+0x4118
  435. #define HDMI_CSC_COEF_C4_LSB HDMI_ARB_BASE_ADDR+0x4119
  436. // HDCP Encryption Engine Registers
  437. #define HDMI_A_HDCPCFG0 HDMI_ARB_BASE_ADDR+0x5000
  438. #define HDMI_A_HDCPCFG1 HDMI_ARB_BASE_ADDR+0x5001
  439. #define HDMI_A_HDCPOBS0 HDMI_ARB_BASE_ADDR+0x5002
  440. #define HDMI_A_HDCPOBS1 HDMI_ARB_BASE_ADDR+0x5003
  441. #define HDMI_A_HDCPOBS2 HDMI_ARB_BASE_ADDR+0x5004
  442. #define HDMI_A_HDCPOBS3 HDMI_ARB_BASE_ADDR+0x5005
  443. #define HDMI_A_APIINTCLR HDMI_ARB_BASE_ADDR+0x5006
  444. #define HDMI_A_APIINTSTAT HDMI_ARB_BASE_ADDR+0x5007
  445. #define HDMI_A_APIINTMSK HDMI_ARB_BASE_ADDR+0x5008
  446. #define HDMI_A_VIDPOLCFG HDMI_ARB_BASE_ADDR+0x5009
  447. #define HDMI_A_OESSWCFG HDMI_ARB_BASE_ADDR+0x500A
  448. #define HDMI_A_TIMER1SETUP0 HDMI_ARB_BASE_ADDR+0x500B
  449. #define HDMI_A_TIMER1SETUP1 HDMI_ARB_BASE_ADDR+0x500C
  450. #define HDMI_A_TIMER2SETUP0 HDMI_ARB_BASE_ADDR+0x500D
  451. #define HDMI_A_TIMER2SETUP1 HDMI_ARB_BASE_ADDR+0x500E
  452. #define HDMI_A_100MSCFG HDMI_ARB_BASE_ADDR+0x500F
  453. #define HDMI_A_2SCFG0 HDMI_ARB_BASE_ADDR+0x5010
  454. #define HDMI_A_2SCFG1 HDMI_ARB_BASE_ADDR+0x5011
  455. #define HDMI_A_5SCFG0 HDMI_ARB_BASE_ADDR+0x5012
  456. #define HDMI_A_5SCFG1 HDMI_ARB_BASE_ADDR+0x5013
  457. #define HDMI_A_SRMVERLSB HDMI_ARB_BASE_ADDR+0x5014
  458. #define HDMI_A_SRMVERMSB HDMI_ARB_BASE_ADDR+0x5015
  459. #define HDMI_A_SRMCTRL HDMI_ARB_BASE_ADDR+0x5016
  460. #define HDMI_A_SFRSETUP HDMI_ARB_BASE_ADDR+0x5017
  461. #define HDMI_A_I2CHSETUP HDMI_ARB_BASE_ADDR+0x5018
  462. #define HDMI_A_INTSETUP HDMI_ARB_BASE_ADDR+0x5019
  463. #define HDMI_A_PRESETUP HDMI_ARB_BASE_ADDR+0x501A
  464. #define HDMI_A_SRM_BASE HDMI_ARB_BASE_ADDR+0x5020
  465. // CEC Engine Registers
  466. #define HDMI_CEC_CTRL HDMI_ARB_BASE_ADDR+0x7D00
  467. #define HDMI_CEC_STAT HDMI_ARB_BASE_ADDR+0x7D01
  468. #define HDMI_CEC_MASK HDMI_ARB_BASE_ADDR+0x7D02
  469. #define HDMI_CEC_POLARITY HDMI_ARB_BASE_ADDR+0x7D03
  470. #define HDMI_CEC_INT HDMI_ARB_BASE_ADDR+0x7D04
  471. #define HDMI_CEC_ADDR_L HDMI_ARB_BASE_ADDR+0x7D05
  472. #define HDMI_CEC_ADDR_H HDMI_ARB_BASE_ADDR+0x7D06
  473. #define HDMI_CEC_TX_CNT HDMI_ARB_BASE_ADDR+0x7D07
  474. #define HDMI_CEC_RX_CNT HDMI_ARB_BASE_ADDR+0x7D08
  475. #define HDMI_CEC_TX_DATA0 HDMI_ARB_BASE_ADDR+0x7D10
  476. #define HDMI_CEC_TX_DATA1 HDMI_ARB_BASE_ADDR+0x7D11
  477. #define HDMI_CEC_TX_DATA2 HDMI_ARB_BASE_ADDR+0x7D12
  478. #define HDMI_CEC_TX_DATA3 HDMI_ARB_BASE_ADDR+0x7D13
  479. #define HDMI_CEC_TX_DATA4 HDMI_ARB_BASE_ADDR+0x7D14
  480. #define HDMI_CEC_TX_DATA5 HDMI_ARB_BASE_ADDR+0x7D15
  481. #define HDMI_CEC_TX_DATA6 HDMI_ARB_BASE_ADDR+0x7D16
  482. #define HDMI_CEC_TX_DATA7 HDMI_ARB_BASE_ADDR+0x7D17
  483. #define HDMI_CEC_TX_DATA8 HDMI_ARB_BASE_ADDR+0x7D18
  484. #define HDMI_CEC_TX_DATA9 HDMI_ARB_BASE_ADDR+0x7D19
  485. #define HDMI_CEC_TX_DATA10 HDMI_ARB_BASE_ADDR+0x7D1a
  486. #define HDMI_CEC_TX_DATA11 HDMI_ARB_BASE_ADDR+0x7D1b
  487. #define HDMI_CEC_TX_DATA12 HDMI_ARB_BASE_ADDR+0x7D1c
  488. #define HDMI_CEC_TX_DATA13 HDMI_ARB_BASE_ADDR+0x7D1d
  489. #define HDMI_CEC_TX_DATA14 HDMI_ARB_BASE_ADDR+0x7D1e
  490. #define HDMI_CEC_TX_DATA15 HDMI_ARB_BASE_ADDR+0x7D1f
  491. #define HDMI_CEC_RX_DATA0 HDMI_ARB_BASE_ADDR+0x7D20
  492. #define HDMI_CEC_RX_DATA1 HDMI_ARB_BASE_ADDR+0x7D21
  493. #define HDMI_CEC_RX_DATA2 HDMI_ARB_BASE_ADDR+0x7D22
  494. #define HDMI_CEC_RX_DATA3 HDMI_ARB_BASE_ADDR+0x7D23
  495. #define HDMI_CEC_RX_DATA4 HDMI_ARB_BASE_ADDR+0x7D24
  496. #define HDMI_CEC_RX_DATA5 HDMI_ARB_BASE_ADDR+0x7D25
  497. #define HDMI_CEC_RX_DATA6 HDMI_ARB_BASE_ADDR+0x7D26
  498. #define HDMI_CEC_RX_DATA7 HDMI_ARB_BASE_ADDR+0x7D27
  499. #define HDMI_CEC_RX_DATA8 HDMI_ARB_BASE_ADDR+0x7D28
  500. #define HDMI_CEC_RX_DATA9 HDMI_ARB_BASE_ADDR+0x7D29
  501. #define HDMI_CEC_RX_DATA10 HDMI_ARB_BASE_ADDR+0x7D2a
  502. #define HDMI_CEC_RX_DATA11 HDMI_ARB_BASE_ADDR+0x7D2b
  503. #define HDMI_CEC_RX_DATA12 HDMI_ARB_BASE_ADDR+0x7D2c
  504. #define HDMI_CEC_RX_DATA13 HDMI_ARB_BASE_ADDR+0x7D2d
  505. #define HDMI_CEC_RX_DATA14 HDMI_ARB_BASE_ADDR+0x7D2e
  506. #define HDMI_CEC_RX_DATA15 HDMI_ARB_BASE_ADDR+0x7D2f
  507. #define HDMI_CEC_LOCK HDMI_ARB_BASE_ADDR+0x7D30
  508. #define HDMI_CEC_WKUPCTRL HDMI_ARB_BASE_ADDR+0x7D31
  509. // I2C Master Registers (E-DDC)
  510. #define HDMI_I2CM_SLAVE HDMI_ARB_BASE_ADDR+0x7E00
  511. #define HDMI_I2CMESS HDMI_ARB_BASE_ADDR+0x7E01
  512. #define HDMI_I2CM_DATAO HDMI_ARB_BASE_ADDR+0x7E02
  513. #define HDMI_I2CM_DATAI HDMI_ARB_BASE_ADDR+0x7E03
  514. #define HDMI_I2CM_OPERATION HDMI_ARB_BASE_ADDR+0x7E04
  515. #define HDMI_I2CM_INT HDMI_ARB_BASE_ADDR+0x7E05
  516. #define HDMI_I2CM_CTLINT HDMI_ARB_BASE_ADDR+0x7E06
  517. #define HDMI_I2CM_DIV HDMI_ARB_BASE_ADDR+0x7E07
  518. #define HDMI_I2CM_SEGADDR HDMI_ARB_BASE_ADDR+0x7E08
  519. #define HDMI_I2CM_SOFTRSTZ HDMI_ARB_BASE_ADDR+0x7E09
  520. #define HDMI_I2CM_SEGPTR HDMI_ARB_BASE_ADDR+0x7E0A
  521. #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x7E0B
  522. #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x7E0C
  523. #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x7E0D
  524. #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x7E0E
  525. #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x7E0F
  526. #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x7E10
  527. #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR HDMI_ARB_BASE_ADDR+0x7E11
  528. #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR HDMI_ARB_BASE_ADDR+0x7E12
  529. // Random Number Generator Registers (RNG)
  530. #define HDMI_RNG_BASE HDMI_ARB_BASE_ADDR+0x8000
  531. #endif //HDMI_COMMON_H