link.icf 5.6 KB

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  1. /*
  2. ** ###################################################################
  3. ** Processors: MIMXRT1052CVL5A
  4. ** MIMXRT1052DVL6A
  5. **
  6. ** Compiler: IAR ANSI C/C++ Compiler for ARM
  7. ** Reference manual: IMXRT1050RM Rev.C, 08/2017
  8. ** Version: rev. 0.1, 2017-01-10
  9. ** Build: b170927
  10. **
  11. ** Abstract:
  12. ** Linker file for the IAR ANSI C/C++ Compiler for ARM
  13. **
  14. ** Copyright 2016 Freescale Semiconductor, Inc.
  15. ** Copyright 2016-2017 NXP
  16. ** Redistribution and use in source and binary forms, with or without modification,
  17. ** are permitted provided that the following conditions are met:
  18. **
  19. ** 1. Redistributions of source code must retain the above copyright notice, this list
  20. ** of conditions and the following disclaimer.
  21. **
  22. ** 2. Redistributions in binary form must reproduce the above copyright notice, this
  23. ** list of conditions and the following disclaimer in the documentation and/or
  24. ** other materials provided with the distribution.
  25. **
  26. ** 3. Neither the name of the copyright holder nor the names of its
  27. ** contributors may be used to endorse or promote products derived from this
  28. ** software without specific prior written permission.
  29. **
  30. ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31. ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32. ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33. ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  34. ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35. ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36. ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  37. ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38. ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39. ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40. **
  41. ** http: www.nxp.com
  42. ** mail: support@nxp.com
  43. **
  44. ** ###################################################################
  45. */
  46. define symbol m_interrupts_start = 0x60002000;
  47. define symbol m_interrupts_end = 0x600023FF;
  48. define symbol m_itcm_start = 0x00000000;
  49. define symbol m_itcm_end = 0x0001FFFF;
  50. define symbol m_spiflash_start = 0x60002400;
  51. define symbol m_spiflash_end = 0x7F7FFFFF;
  52. define symbol m_dtcm_start = 0x20000000;
  53. define symbol m_dtcm_end = 0x2001FFFF;/* DTCM 128KB */
  54. define symbol m_ocram_start = 0x20200000;
  55. define symbol m_ocram_end = 0x2020FFFF;/* OCRAM 64KB */
  56. define symbol m_sdram_start = 0x80000000;
  57. define symbol m_sdram_end = 0x81DFFFFF;
  58. define symbol m_ncache_start = 0x81E00000;
  59. define symbol m_ncache_end = 0x81FFFFFF;
  60. define exported symbol m_boot_hdr_conf_start = 0x60000000;
  61. define symbol m_boot_hdr_ivt_start = 0x60001000;
  62. define symbol m_boot_hdr_boot_data_start = 0x60001020;
  63. define symbol m_boot_hdr_dcd_data_start = 0x60001030;
  64. /* Sizes */
  65. if (isdefinedsymbol(__stack_size__)) {
  66. define symbol __size_cstack__ = __stack_size__;
  67. } else {
  68. define symbol __size_cstack__ = 0x0400;
  69. }
  70. if (isdefinedsymbol(__heap_size__)) {
  71. define symbol __size_heap__ = __heap_size__;
  72. } else {
  73. define symbol __size_heap__ = 0x0400;
  74. }
  75. define exported symbol __VECTOR_TABLE = m_interrupts_start;
  76. define exported symbol __VECTOR_RAM = m_interrupts_start;
  77. define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
  78. define exported symbol __RTT_HEAP_END = m_dtcm_end;
  79. define memory mem with size = 4G;
  80. define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
  81. | mem:[from m_spiflash_start to m_spiflash_end];
  82. define region ITCM_region = mem:[from m_itcm_start to m_itcm_end];
  83. define region DTCM_region = mem:[from m_dtcm_start to m_dtcm_end];
  84. define region OCRAM_region = mem:[from m_ocram_start to m_ocram_end];
  85. define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
  86. define region SDRAM_region = mem:[from m_sdram_start to m_sdram_end];
  87. define block CSTACK with alignment = 8, size = __size_cstack__ { };
  88. define block HEAP with alignment = 8, size = __size_heap__ { };
  89. define block RW { readwrite };
  90. define block ZI { zi };
  91. define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
  92. initialize by copy { readwrite, section .textrw};
  93. do not initialize { section .noinit };
  94. place at address mem: m_interrupts_start { readonly section .intvec };
  95. place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
  96. place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
  97. place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
  98. place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
  99. keep { section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
  100. keep { section FSymTab };
  101. keep { section VSymTab };
  102. keep { section .rti_fn* };
  103. place in TEXT_region { readonly };
  104. place in DTCM_region { block RW };
  105. place in DTCM_region { block ZI };
  106. place in DTCM_region { last block HEAP };
  107. place in DTCM_region { block CSTACK };
  108. place in NCACHE_region { block NCACHE_VAR };