board.c 60 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2009-01-05 Bernard first implementation
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "board.h"
  13. #include "pin_mux.h"
  14. #include "fsl_iomuxc.h"
  15. #include "fsl_gpio.h"
  16. #ifdef BSP_USING_DMA
  17. #include "fsl_dmamux.h"
  18. #include "fsl_edma.h"
  19. #endif
  20. #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
  21. 4 bits for subpriority */
  22. #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
  23. 3 bits for subpriority */
  24. #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
  25. 2 bits for subpriority */
  26. #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
  27. 1 bits for subpriority */
  28. #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
  29. 0 bits for subpriority */
  30. void BOARD_ConfigMPU(void)
  31. {
  32. #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
  33. extern uint32_t Image$$RW_m_ncache$$Base[];
  34. /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
  35. extern uint32_t Image$$RW_m_ncache_unused$$Base[];
  36. extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
  37. uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
  38. uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
  39. 0 :
  40. ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
  41. #elif defined(__MCUXPRESSO)
  42. extern uint32_t __base_NCACHE_REGION;
  43. extern uint32_t __top_NCACHE_REGION;
  44. uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
  45. uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
  46. #elif defined(__ICCARM__) || defined(__GNUC__)
  47. extern uint32_t __noncachedata_start__[];
  48. extern uint32_t __noncachedata_end__[];
  49. uint32_t nonCacheStart = (uint32_t)__noncachedata_start__;
  50. uint32_t size = (uint32_t)((uint32_t)__noncachedata_end__ - (uint32_t)__noncachedata_start__);
  51. #endif
  52. volatile uint32_t i = 0;
  53. /* Disable I cache and D cache */
  54. if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
  55. {
  56. SCB_DisableICache();
  57. }
  58. if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
  59. {
  60. SCB_DisableDCache();
  61. }
  62. /* Disable MPU */
  63. ARM_MPU_Disable();
  64. /* MPU configure:
  65. * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
  66. * SubRegionDisable, Size)
  67. * API in mpu_armv7.h.
  68. * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
  69. * disabled.
  70. * param AccessPermission Data access permissions, allows you to configure read/write access for User and
  71. * Privileged mode.
  72. * Use MACROS defined in mpu_armv7.h:
  73. * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
  74. * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
  75. * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
  76. * 0 x 0 0 Strongly Ordered shareable
  77. * 0 x 0 1 Device shareable
  78. * 0 0 1 0 Normal not shareable Outer and inner write
  79. * through no write allocate
  80. * 0 0 1 1 Normal not shareable Outer and inner write
  81. * back no write allocate
  82. * 0 1 1 0 Normal shareable Outer and inner write
  83. * through no write allocate
  84. * 0 1 1 1 Normal shareable Outer and inner write
  85. * back no write allocate
  86. * 1 0 0 0 Normal not shareable outer and inner
  87. * noncache
  88. * 1 1 0 0 Normal shareable outer and inner
  89. * noncache
  90. * 1 0 1 1 Normal not shareable outer and inner write
  91. * back write/read acllocate
  92. * 1 1 1 1 Normal shareable outer and inner write
  93. * back write/read acllocate
  94. * 2 x 0 0 Device not shareable
  95. * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
  96. * policy.
  97. * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
  98. * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
  99. * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
  100. * mpu_armv7.h.
  101. */
  102. /*
  103. * Add default region to deny access to whole address space to workaround speculative prefetch.
  104. * Refer to Arm errata 1013783-B for more details.
  105. *
  106. */
  107. /* Region 0 setting: Instruction access disabled, No data access permission. */
  108. MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
  109. MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
  110. /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
  111. MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
  112. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  113. /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
  114. MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
  115. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  116. #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
  117. /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
  118. MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
  119. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
  120. #endif
  121. /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
  122. MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
  123. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
  124. /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
  125. MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
  126. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
  127. /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
  128. MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
  129. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
  130. /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
  131. MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
  132. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
  133. /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
  134. MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U);
  135. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
  136. /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
  137. MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
  138. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
  139. while ((size >> i) > 0x1U)
  140. {
  141. i++;
  142. }
  143. if (i != 0)
  144. {
  145. /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
  146. assert(!(nonCacheStart % size));
  147. assert(size == (uint32_t)(1 << i));
  148. assert(i >= 5);
  149. /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
  150. MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
  151. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
  152. }
  153. /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
  154. MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
  155. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
  156. /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
  157. MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000);
  158. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
  159. /* Enable MPU */
  160. ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
  161. /* Enable I cache and D cache */
  162. SCB_EnableDCache();
  163. SCB_EnableICache();
  164. }
  165. /* This is the timer interrupt service routine. */
  166. void SysTick_Handler(void)
  167. {
  168. /* enter interrupt */
  169. rt_interrupt_enter();
  170. rt_tick_increase();
  171. /* leave interrupt */
  172. rt_interrupt_leave();
  173. }
  174. #ifdef BSP_USING_DMA
  175. void imxrt_dma_init(void)
  176. {
  177. edma_config_t config;
  178. DMAMUX_Init(DMAMUX);
  179. EDMA_GetDefaultConfig(&config);
  180. EDMA_Init(DMA0, &config);
  181. }
  182. #endif
  183. #ifdef BSP_USING_LPUART
  184. void imxrt_uart_pins_init(void)
  185. {
  186. #ifdef BSP_USING_LPUART1
  187. IOMUXC_SetPinMux(
  188. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
  189. 0U); /* Software Input On Field: Input Path is determined by functionality */
  190. IOMUXC_SetPinMux(
  191. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
  192. 0U); /* Software Input On Field: Input Path is determined by functionality */
  193. IOMUXC_SetPinConfig(
  194. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
  195. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  196. Drive Strength Field: R0/6
  197. Speed Field: medium(100MHz)
  198. Open Drain Enable Field: Open Drain Disabled
  199. Pull / Keep Enable Field: Pull/Keeper Enabled
  200. Pull / Keep Select Field: Keeper
  201. Pull Up / Down Config. Field: 100K Ohm Pull Down
  202. Hyst. Enable Field: Hysteresis Disabled */
  203. IOMUXC_SetPinConfig(
  204. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
  205. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  206. Drive Strength Field: R0/6
  207. Speed Field: medium(100MHz)
  208. Open Drain Enable Field: Open Drain Disabled
  209. Pull / Keep Enable Field: Pull/Keeper Enabled
  210. Pull / Keep Select Field: Keeper
  211. Pull Up / Down Config. Field: 100K Ohm Pull Down
  212. Hyst. Enable Field: Hysteresis Disabled */
  213. #endif
  214. #ifdef BSP_USING_LPUART2
  215. IOMUXC_SetPinMux(
  216. IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
  217. 0U);
  218. IOMUXC_SetPinMux(
  219. IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
  220. 0U);
  221. IOMUXC_SetPinConfig(
  222. IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
  223. 0x10B0u);
  224. IOMUXC_SetPinConfig(
  225. IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
  226. 0x10B0u);
  227. #endif
  228. #ifdef BSP_USING_LPUART3
  229. IOMUXC_SetPinMux(
  230. IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
  231. 0U);
  232. IOMUXC_SetPinMux(
  233. IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
  234. 0U);
  235. IOMUXC_SetPinConfig(
  236. IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
  237. 0x10B0u);
  238. IOMUXC_SetPinConfig(
  239. IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
  240. 0x10B0u);
  241. #endif
  242. #ifdef BSP_USING_LPUART4
  243. IOMUXC_SetPinMux(
  244. IOMUXC_GPIO_B1_00_LPUART4_TX,
  245. 0U);
  246. IOMUXC_SetPinMux(
  247. IOMUXC_GPIO_B1_01_LPUART4_RX,
  248. 0U);
  249. IOMUXC_SetPinConfig(
  250. IOMUXC_GPIO_B1_00_LPUART4_TX,
  251. 0x10B0u);
  252. IOMUXC_SetPinConfig(
  253. IOMUXC_GPIO_B1_01_LPUART4_RX,
  254. 0x10B0u);
  255. #endif
  256. #ifdef BSP_USING_LPUART5
  257. IOMUXC_SetPinMux(
  258. IOMUXC_GPIO_B1_12_LPUART5_TX,
  259. 0U);
  260. IOMUXC_SetPinMux(
  261. IOMUXC_GPIO_B1_13_LPUART5_RX,
  262. 0U);
  263. IOMUXC_SetPinConfig(
  264. IOMUXC_GPIO_B1_12_LPUART5_TX,
  265. 0x10B0u);
  266. IOMUXC_SetPinConfig(
  267. IOMUXC_GPIO_B1_13_LPUART5_RX,
  268. 0x10B0u);
  269. #endif
  270. #ifdef BSP_USING_LPUART6
  271. IOMUXC_SetPinMux(
  272. IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
  273. 0U);
  274. IOMUXC_SetPinMux(
  275. IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
  276. 0U);
  277. IOMUXC_SetPinConfig(
  278. IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
  279. 0x10B0u);
  280. IOMUXC_SetPinConfig(
  281. IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
  282. 0x10B0u);
  283. #endif
  284. #ifdef BSP_USING_LPUART7
  285. IOMUXC_SetPinMux(
  286. IOMUXC_GPIO_EMC_31_LPUART7_TX,
  287. 0U);
  288. IOMUXC_SetPinMux(
  289. IOMUXC_GPIO_EMC_32_LPUART7_RX,
  290. 0U);
  291. IOMUXC_SetPinConfig(
  292. IOMUXC_GPIO_EMC_31_LPUART7_TX,
  293. 0x10B0u);
  294. IOMUXC_SetPinConfig(
  295. IOMUXC_GPIO_EMC_32_LPUART7_RX,
  296. 0x10B0u);
  297. #endif
  298. #ifdef BSP_USING_LPUART8
  299. IOMUXC_SetPinMux(
  300. IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
  301. 0U);
  302. IOMUXC_SetPinMux(
  303. IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
  304. 0U);
  305. IOMUXC_SetPinConfig(
  306. IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
  307. 0x10B0u);
  308. IOMUXC_SetPinConfig(
  309. IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
  310. 0x10B0u);
  311. #endif
  312. }
  313. #endif /* BSP_USING_LPUART */
  314. #ifdef BSP_USING_I2C
  315. static void imxrt_i2c_pins_init(void)
  316. {
  317. #ifdef BSP_USING_I2C1
  318. IOMUXC_SetPinMux(
  319. IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
  320. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
  321. IOMUXC_SetPinMux(
  322. IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
  323. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
  324. IOMUXC_SetPinConfig(
  325. IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
  326. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  327. Drive Strength Field: R0/6
  328. Speed Field: medium(100MHz)
  329. Open Drain Enable Field: Open Drain Enabled
  330. Pull / Keep Enable Field: Pull/Keeper Enabled
  331. Pull / Keep Select Field: Keeper
  332. Pull Up / Down Config. Field: 22K Ohm Pull Up
  333. Hyst. Enable Field: Hysteresis Disabled */
  334. IOMUXC_SetPinConfig(
  335. IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
  336. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  337. Drive Strength Field: R0/6
  338. Speed Field: medium(100MHz)
  339. Open Drain Enable Field: Open Drain Enabled
  340. Pull / Keep Enable Field: Pull/Keeper Enabled
  341. Pull / Keep Select Field: Keeper
  342. Pull Up / Down Config. Field: 22K Ohm Pull Up
  343. Hyst. Enable Field: Hysteresis Disabled */
  344. #endif
  345. #ifdef BSP_USING_I2C3
  346. IOMUXC_SetPinMux(
  347. IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
  348. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
  349. IOMUXC_SetPinMux(
  350. IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
  351. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
  352. IOMUXC_SetPinConfig(
  353. IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
  354. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  355. Drive Strength Field: R0/6
  356. Speed Field: medium(100MHz)
  357. Open Drain Enable Field: Open Drain Enabled
  358. Pull / Keep Enable Field: Pull/Keeper Enabled
  359. Pull / Keep Select Field: Keeper
  360. Pull Up / Down Config. Field: 22K Ohm Pull Up
  361. Hyst. Enable Field: Hysteresis Disabled */
  362. IOMUXC_SetPinConfig(
  363. IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
  364. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  365. Drive Strength Field: R0/6
  366. Speed Field: medium(100MHz)
  367. Open Drain Enable Field: Open Drain Enabled
  368. Pull / Keep Enable Field: Pull/Keeper Enabled
  369. Pull / Keep Select Field: Keeper
  370. Pull Up / Down Config. Field: 22K Ohm Pull Up
  371. Hyst. Enable Field: Hysteresis Disabled */
  372. #endif
  373. #ifdef BSP_USING_I2C4
  374. IOMUXC_SetPinMux(
  375. IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL, /* GPIO_AD_B1_00 is configured as LPI2C1_SCL */
  376. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_00 */
  377. IOMUXC_SetPinMux(
  378. IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA, /* GPIO_AD_B1_01 is configured as LPI2C1_SDA */
  379. 1U); /* Software Input On Field: Force input path of pad GPIO_AD_B1_01 */
  380. IOMUXC_SetPinConfig(
  381. IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL, /* GPIO_AD_B1_00 PAD functional properties : */
  382. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  383. Drive Strength Field: R0/6
  384. Speed Field: medium(100MHz)
  385. Open Drain Enable Field: Open Drain Enabled
  386. Pull / Keep Enable Field: Pull/Keeper Enabled
  387. Pull / Keep Select Field: Keeper
  388. Pull Up / Down Config. Field: 22K Ohm Pull Up
  389. Hyst. Enable Field: Hysteresis Disabled */
  390. IOMUXC_SetPinConfig(
  391. IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA, /* GPIO_AD_B1_01 PAD functional properties : */
  392. 0xD8B0u); /* Slew Rate Field: Slow Slew Rate
  393. Drive Strength Field: R0/6
  394. Speed Field: medium(100MHz)
  395. Open Drain Enable Field: Open Drain Enabled
  396. Pull / Keep Enable Field: Pull/Keeper Enabled
  397. Pull / Keep Select Field: Keeper
  398. Pull Up / Down Config. Field: 22K Ohm Pull Up
  399. Hyst. Enable Field: Hysteresis Disabled */
  400. #endif
  401. }
  402. #endif /* BSP_USING_I2C */
  403. #ifdef BSP_USING_LCD
  404. static void imxrt_lcd_pins_init(void)
  405. {
  406. IOMUXC_SetPinMux(
  407. IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO_AD_B0_02 is configured as GPIO1_IO02 */
  408. 0U); /* Software Input On Field: Input Path is determined by functionality */
  409. IOMUXC_SetPinMux(
  410. IOMUXC_GPIO_B1_15_GPIO2_IO31, /* GPIO_B1_15 is configured as GPIO2_IO31 */
  411. 0U); /* Software Input On Field: Input Path is determined by functionality */
  412. IOMUXC_SetPinMux(
  413. IOMUXC_GPIO_B0_00_LCD_CLK, /* GPIO_B0_00 is configured as LCD_CLK */
  414. 0U); /* Software Input On Field: Input Path is determined by functionality */
  415. IOMUXC_SetPinMux(
  416. IOMUXC_GPIO_B0_01_LCD_ENABLE, /* GPIO_B0_01 is configured as LCD_ENABLE */
  417. 0U); /* Software Input On Field: Input Path is determined by functionality */
  418. IOMUXC_SetPinMux(
  419. IOMUXC_GPIO_B0_02_LCD_HSYNC, /* GPIO_B0_02 is configured as LCD_HSYNC */
  420. 0U); /* Software Input On Field: Input Path is determined by functionality */
  421. IOMUXC_SetPinMux(
  422. IOMUXC_GPIO_B0_03_LCD_VSYNC, /* GPIO_B0_03 is configured as LCD_VSYNC */
  423. 0U); /* Software Input On Field: Input Path is determined by functionality */
  424. IOMUXC_SetPinMux(
  425. IOMUXC_GPIO_B0_04_LCD_DATA00, /* GPIO_B0_04 is configured as LCD_DATA00 */
  426. 0U); /* Software Input On Field: Input Path is determined by functionality */
  427. IOMUXC_SetPinMux(
  428. IOMUXC_GPIO_B0_05_LCD_DATA01, /* GPIO_B0_05 is configured as LCD_DATA01 */
  429. 0U); /* Software Input On Field: Input Path is determined by functionality */
  430. IOMUXC_SetPinMux(
  431. IOMUXC_GPIO_B0_06_LCD_DATA02, /* GPIO_B0_06 is configured as LCD_DATA02 */
  432. 0U); /* Software Input On Field: Input Path is determined by functionality */
  433. IOMUXC_SetPinMux(
  434. IOMUXC_GPIO_B0_07_LCD_DATA03, /* GPIO_B0_07 is configured as LCD_DATA03 */
  435. 0U); /* Software Input On Field: Input Path is determined by functionality */
  436. IOMUXC_SetPinMux(
  437. IOMUXC_GPIO_B0_08_LCD_DATA04, /* GPIO_B0_08 is configured as LCD_DATA04 */
  438. 0U); /* Software Input On Field: Input Path is determined by functionality */
  439. IOMUXC_SetPinMux(
  440. IOMUXC_GPIO_B0_09_LCD_DATA05, /* GPIO_B0_09 is configured as LCD_DATA05 */
  441. 0U); /* Software Input On Field: Input Path is determined by functionality */
  442. IOMUXC_SetPinMux(
  443. IOMUXC_GPIO_B0_10_LCD_DATA06, /* GPIO_B0_10 is configured as LCD_DATA06 */
  444. 0U); /* Software Input On Field: Input Path is determined by functionality */
  445. IOMUXC_SetPinMux(
  446. IOMUXC_GPIO_B0_11_LCD_DATA07, /* GPIO_B0_11 is configured as LCD_DATA07 */
  447. 0U); /* Software Input On Field: Input Path is determined by functionality */
  448. IOMUXC_SetPinMux(
  449. IOMUXC_GPIO_B0_12_LCD_DATA08, /* GPIO_B0_12 is configured as LCD_DATA08 */
  450. 0U); /* Software Input On Field: Input Path is determined by functionality */
  451. IOMUXC_SetPinMux(
  452. IOMUXC_GPIO_B0_13_LCD_DATA09, /* GPIO_B0_13 is configured as LCD_DATA09 */
  453. 0U); /* Software Input On Field: Input Path is determined by functionality */
  454. IOMUXC_SetPinMux(
  455. IOMUXC_GPIO_B0_14_LCD_DATA10, /* GPIO_B0_14 is configured as LCD_DATA10 */
  456. 0U); /* Software Input On Field: Input Path is determined by functionality */
  457. IOMUXC_SetPinMux(
  458. IOMUXC_GPIO_B0_15_LCD_DATA11, /* GPIO_B0_15 is configured as LCD_DATA11 */
  459. 0U); /* Software Input On Field: Input Path is determined by functionality */
  460. IOMUXC_SetPinMux(
  461. IOMUXC_GPIO_B1_00_LCD_DATA12, /* GPIO_B1_00 is configured as LCD_DATA12 */
  462. 0U); /* Software Input On Field: Input Path is determined by functionality */
  463. IOMUXC_SetPinMux(
  464. IOMUXC_GPIO_B1_01_LCD_DATA13, /* GPIO_B1_01 is configured as LCD_DATA13 */
  465. 0U); /* Software Input On Field: Input Path is determined by functionality */
  466. IOMUXC_SetPinMux(
  467. IOMUXC_GPIO_B1_02_LCD_DATA14, /* GPIO_B1_02 is configured as LCD_DATA14 */
  468. 0U); /* Software Input On Field: Input Path is determined by functionality */
  469. IOMUXC_SetPinMux(
  470. IOMUXC_GPIO_B1_03_LCD_DATA15, /* GPIO_B1_03 is configured as LCD_DATA15 */
  471. 0U); /* Software Input On Field: Input Path is determined by functionality */
  472. IOMUXC_SetPinConfig(
  473. IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, /* GPIO_AD_B0_02 PAD functional properties : */
  474. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  475. Drive Strength Field: R0/6
  476. Speed Field: medium(100MHz)
  477. Open Drain Enable Field: Open Drain Disabled
  478. Pull / Keep Enable Field: Pull/Keeper Enabled
  479. Pull / Keep Select Field: Keeper
  480. Pull Up / Down Config. Field: 100K Ohm Pull Down
  481. Hyst. Enable Field: Hysteresis Disabled */
  482. IOMUXC_SetPinConfig(
  483. IOMUXC_GPIO_B1_15_GPIO2_IO31, /* GPIO_B1_15 PAD functional properties : */
  484. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  485. Drive Strength Field: R0/6
  486. Speed Field: medium(100MHz)
  487. Open Drain Enable Field: Open Drain Disabled
  488. Pull / Keep Enable Field: Pull/Keeper Enabled
  489. Pull / Keep Select Field: Keeper
  490. Pull Up / Down Config. Field: 100K Ohm Pull Down
  491. Hyst. Enable Field: Hysteresis Disabled */
  492. IOMUXC_SetPinConfig(
  493. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
  494. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  495. Drive Strength Field: R0/6
  496. Speed Field: medium(100MHz)
  497. Open Drain Enable Field: Open Drain Disabled
  498. Pull / Keep Enable Field: Pull/Keeper Enabled
  499. Pull / Keep Select Field: Keeper
  500. Pull Up / Down Config. Field: 100K Ohm Pull Down
  501. Hyst. Enable Field: Hysteresis Disabled */
  502. IOMUXC_SetPinConfig(
  503. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
  504. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  505. Drive Strength Field: R0/6
  506. Speed Field: medium(100MHz)
  507. Open Drain Enable Field: Open Drain Disabled
  508. Pull / Keep Enable Field: Pull/Keeper Enabled
  509. Pull / Keep Select Field: Keeper
  510. Pull Up / Down Config. Field: 100K Ohm Pull Down
  511. Hyst. Enable Field: Hysteresis Disabled */
  512. IOMUXC_SetPinConfig(
  513. IOMUXC_GPIO_B0_00_LCD_CLK, /* GPIO_B0_00 PAD functional properties : */
  514. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  515. Drive Strength Field: R0/6
  516. Speed Field: medium(100MHz)
  517. Open Drain Enable Field: Open Drain Disabled
  518. Pull / Keep Enable Field: Pull/Keeper Enabled
  519. Pull / Keep Select Field: Pull
  520. Pull Up / Down Config. Field: 100K Ohm Pull Up
  521. Hyst. Enable Field: Hysteresis Enabled */
  522. IOMUXC_SetPinConfig(
  523. IOMUXC_GPIO_B0_01_LCD_ENABLE, /* GPIO_B0_01 PAD functional properties : */
  524. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  525. Drive Strength Field: R0/6
  526. Speed Field: medium(100MHz)
  527. Open Drain Enable Field: Open Drain Disabled
  528. Pull / Keep Enable Field: Pull/Keeper Enabled
  529. Pull / Keep Select Field: Pull
  530. Pull Up / Down Config. Field: 100K Ohm Pull Up
  531. Hyst. Enable Field: Hysteresis Enabled */
  532. IOMUXC_SetPinConfig(
  533. IOMUXC_GPIO_B0_02_LCD_HSYNC, /* GPIO_B0_02 PAD functional properties : */
  534. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  535. Drive Strength Field: R0/6
  536. Speed Field: medium(100MHz)
  537. Open Drain Enable Field: Open Drain Disabled
  538. Pull / Keep Enable Field: Pull/Keeper Enabled
  539. Pull / Keep Select Field: Pull
  540. Pull Up / Down Config. Field: 100K Ohm Pull Up
  541. Hyst. Enable Field: Hysteresis Enabled */
  542. IOMUXC_SetPinConfig(
  543. IOMUXC_GPIO_B0_03_LCD_VSYNC, /* GPIO_B0_03 PAD functional properties : */
  544. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  545. Drive Strength Field: R0/6
  546. Speed Field: medium(100MHz)
  547. Open Drain Enable Field: Open Drain Disabled
  548. Pull / Keep Enable Field: Pull/Keeper Enabled
  549. Pull / Keep Select Field: Pull
  550. Pull Up / Down Config. Field: 100K Ohm Pull Up
  551. Hyst. Enable Field: Hysteresis Enabled */
  552. IOMUXC_SetPinConfig(
  553. IOMUXC_GPIO_B0_04_LCD_DATA00, /* GPIO_B0_04 PAD functional properties : */
  554. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  555. Drive Strength Field: R0/6
  556. Speed Field: medium(100MHz)
  557. Open Drain Enable Field: Open Drain Disabled
  558. Pull / Keep Enable Field: Pull/Keeper Enabled
  559. Pull / Keep Select Field: Pull
  560. Pull Up / Down Config. Field: 100K Ohm Pull Up
  561. Hyst. Enable Field: Hysteresis Enabled */
  562. IOMUXC_SetPinConfig(
  563. IOMUXC_GPIO_B0_05_LCD_DATA01, /* GPIO_B0_05 PAD functional properties : */
  564. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  565. Drive Strength Field: R0/6
  566. Speed Field: medium(100MHz)
  567. Open Drain Enable Field: Open Drain Disabled
  568. Pull / Keep Enable Field: Pull/Keeper Enabled
  569. Pull / Keep Select Field: Pull
  570. Pull Up / Down Config. Field: 100K Ohm Pull Up
  571. Hyst. Enable Field: Hysteresis Enabled */
  572. IOMUXC_SetPinConfig(
  573. IOMUXC_GPIO_B0_06_LCD_DATA02, /* GPIO_B0_06 PAD functional properties : */
  574. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  575. Drive Strength Field: R0/6
  576. Speed Field: medium(100MHz)
  577. Open Drain Enable Field: Open Drain Disabled
  578. Pull / Keep Enable Field: Pull/Keeper Enabled
  579. Pull / Keep Select Field: Pull
  580. Pull Up / Down Config. Field: 100K Ohm Pull Up
  581. Hyst. Enable Field: Hysteresis Enabled */
  582. IOMUXC_SetPinConfig(
  583. IOMUXC_GPIO_B0_07_LCD_DATA03, /* GPIO_B0_07 PAD functional properties : */
  584. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  585. Drive Strength Field: R0/6
  586. Speed Field: medium(100MHz)
  587. Open Drain Enable Field: Open Drain Disabled
  588. Pull / Keep Enable Field: Pull/Keeper Enabled
  589. Pull / Keep Select Field: Pull
  590. Pull Up / Down Config. Field: 100K Ohm Pull Up
  591. Hyst. Enable Field: Hysteresis Enabled */
  592. IOMUXC_SetPinConfig(
  593. IOMUXC_GPIO_B0_08_LCD_DATA04, /* GPIO_B0_08 PAD functional properties : */
  594. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  595. Drive Strength Field: R0/6
  596. Speed Field: medium(100MHz)
  597. Open Drain Enable Field: Open Drain Disabled
  598. Pull / Keep Enable Field: Pull/Keeper Enabled
  599. Pull / Keep Select Field: Pull
  600. Pull Up / Down Config. Field: 100K Ohm Pull Up
  601. Hyst. Enable Field: Hysteresis Enabled */
  602. IOMUXC_SetPinConfig(
  603. IOMUXC_GPIO_B0_09_LCD_DATA05, /* GPIO_B0_09 PAD functional properties : */
  604. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  605. Drive Strength Field: R0/6
  606. Speed Field: medium(100MHz)
  607. Open Drain Enable Field: Open Drain Disabled
  608. Pull / Keep Enable Field: Pull/Keeper Enabled
  609. Pull / Keep Select Field: Pull
  610. Pull Up / Down Config. Field: 100K Ohm Pull Up
  611. Hyst. Enable Field: Hysteresis Enabled */
  612. IOMUXC_SetPinConfig(
  613. IOMUXC_GPIO_B0_10_LCD_DATA06, /* GPIO_B0_10 PAD functional properties : */
  614. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  615. Drive Strength Field: R0/6
  616. Speed Field: medium(100MHz)
  617. Open Drain Enable Field: Open Drain Disabled
  618. Pull / Keep Enable Field: Pull/Keeper Enabled
  619. Pull / Keep Select Field: Pull
  620. Pull Up / Down Config. Field: 100K Ohm Pull Up
  621. Hyst. Enable Field: Hysteresis Enabled */
  622. IOMUXC_SetPinConfig(
  623. IOMUXC_GPIO_B0_11_LCD_DATA07, /* GPIO_B0_11 PAD functional properties : */
  624. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  625. Drive Strength Field: R0/6
  626. Speed Field: medium(100MHz)
  627. Open Drain Enable Field: Open Drain Disabled
  628. Pull / Keep Enable Field: Pull/Keeper Enabled
  629. Pull / Keep Select Field: Pull
  630. Pull Up / Down Config. Field: 100K Ohm Pull Up
  631. Hyst. Enable Field: Hysteresis Enabled */
  632. IOMUXC_SetPinConfig(
  633. IOMUXC_GPIO_B0_12_LCD_DATA08, /* GPIO_B0_12 PAD functional properties : */
  634. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  635. Drive Strength Field: R0/6
  636. Speed Field: medium(100MHz)
  637. Open Drain Enable Field: Open Drain Disabled
  638. Pull / Keep Enable Field: Pull/Keeper Enabled
  639. Pull / Keep Select Field: Pull
  640. Pull Up / Down Config. Field: 100K Ohm Pull Up
  641. Hyst. Enable Field: Hysteresis Enabled */
  642. IOMUXC_SetPinConfig(
  643. IOMUXC_GPIO_B0_13_LCD_DATA09, /* GPIO_B0_13 PAD functional properties : */
  644. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  645. Drive Strength Field: R0/6
  646. Speed Field: medium(100MHz)
  647. Open Drain Enable Field: Open Drain Disabled
  648. Pull / Keep Enable Field: Pull/Keeper Enabled
  649. Pull / Keep Select Field: Pull
  650. Pull Up / Down Config. Field: 100K Ohm Pull Up
  651. Hyst. Enable Field: Hysteresis Enabled */
  652. IOMUXC_SetPinConfig(
  653. IOMUXC_GPIO_B0_14_LCD_DATA10, /* GPIO_B0_14 PAD functional properties : */
  654. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  655. Drive Strength Field: R0/6
  656. Speed Field: medium(100MHz)
  657. Open Drain Enable Field: Open Drain Disabled
  658. Pull / Keep Enable Field: Pull/Keeper Enabled
  659. Pull / Keep Select Field: Pull
  660. Pull Up / Down Config. Field: 100K Ohm Pull Up
  661. Hyst. Enable Field: Hysteresis Enabled */
  662. IOMUXC_SetPinConfig(
  663. IOMUXC_GPIO_B0_15_LCD_DATA11, /* GPIO_B0_15 PAD functional properties : */
  664. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  665. Drive Strength Field: R0/6
  666. Speed Field: medium(100MHz)
  667. Open Drain Enable Field: Open Drain Disabled
  668. Pull / Keep Enable Field: Pull/Keeper Enabled
  669. Pull / Keep Select Field: Pull
  670. Pull Up / Down Config. Field: 100K Ohm Pull Up
  671. Hyst. Enable Field: Hysteresis Enabled */
  672. IOMUXC_SetPinConfig(
  673. IOMUXC_GPIO_B1_00_LCD_DATA12, /* GPIO_B1_00 PAD functional properties : */
  674. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  675. Drive Strength Field: R0/6
  676. Speed Field: medium(100MHz)
  677. Open Drain Enable Field: Open Drain Disabled
  678. Pull / Keep Enable Field: Pull/Keeper Enabled
  679. Pull / Keep Select Field: Pull
  680. Pull Up / Down Config. Field: 100K Ohm Pull Up
  681. Hyst. Enable Field: Hysteresis Enabled */
  682. IOMUXC_SetPinConfig(
  683. IOMUXC_GPIO_B1_01_LCD_DATA13, /* GPIO_B1_01 PAD functional properties : */
  684. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  685. Drive Strength Field: R0/6
  686. Speed Field: medium(100MHz)
  687. Open Drain Enable Field: Open Drain Disabled
  688. Pull / Keep Enable Field: Pull/Keeper Enabled
  689. Pull / Keep Select Field: Pull
  690. Pull Up / Down Config. Field: 100K Ohm Pull Up
  691. Hyst. Enable Field: Hysteresis Enabled */
  692. IOMUXC_SetPinConfig(
  693. IOMUXC_GPIO_B1_02_LCD_DATA14, /* GPIO_B1_02 PAD functional properties : */
  694. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  695. Drive Strength Field: R0/6
  696. Speed Field: medium(100MHz)
  697. Open Drain Enable Field: Open Drain Disabled
  698. Pull / Keep Enable Field: Pull/Keeper Enabled
  699. Pull / Keep Select Field: Pull
  700. Pull Up / Down Config. Field: 100K Ohm Pull Up
  701. Hyst. Enable Field: Hysteresis Enabled */
  702. IOMUXC_SetPinConfig(
  703. IOMUXC_GPIO_B1_03_LCD_DATA15, /* GPIO_B1_03 PAD functional properties : */
  704. 0x01B0B0u); /* Slew Rate Field: Slow Slew Rate
  705. Drive Strength Field: R0/6
  706. Speed Field: medium(100MHz)
  707. Open Drain Enable Field: Open Drain Disabled
  708. Pull / Keep Enable Field: Pull/Keeper Enabled
  709. Pull / Keep Select Field: Pull
  710. Pull Up / Down Config. Field: 100K Ohm Pull Up
  711. Hyst. Enable Field: Hysteresis Enabled */
  712. }
  713. #endif
  714. #ifdef BSP_USING_ETH
  715. void imxrt_enet_pins_init(void)
  716. {
  717. CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
  718. IOMUXC_SetPinMux(
  719. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
  720. 0U); /* Software Input On Field: Input Path is determined by functionality */
  721. IOMUXC_SetPinMux(
  722. IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
  723. 0U);
  724. IOMUXC_SetPinMux(
  725. IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
  726. 0U); /* Software Input On Field: Input Path is determined by functionality */
  727. IOMUXC_SetPinMux(
  728. IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
  729. 0U); /* Software Input On Field: Input Path is determined by functionality */
  730. IOMUXC_SetPinMux(
  731. IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
  732. 0U); /* Software Input On Field: Input Path is determined by functionality */
  733. IOMUXC_SetPinMux(
  734. IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
  735. 0U); /* Software Input On Field: Input Path is determined by functionality */
  736. IOMUXC_SetPinMux(
  737. IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
  738. 0U); /* Software Input On Field: Input Path is determined by functionality */
  739. IOMUXC_SetPinMux(
  740. IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
  741. 0U); /* Software Input On Field: Input Path is determined by functionality */
  742. IOMUXC_SetPinMux(
  743. IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
  744. 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */
  745. IOMUXC_SetPinMux(
  746. IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
  747. 0U); /* Software Input On Field: Input Path is determined by functionality */
  748. IOMUXC_SetPinMux(
  749. IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
  750. 0U); /* Software Input On Field: Input Path is determined by functionality */
  751. IOMUXC_SetPinMux(
  752. IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
  753. 0U); /* Software Input On Field: Input Path is determined by functionality */
  754. IOMUXC_SetPinConfig(
  755. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
  756. 0xB0A9u); /* Slew Rate Field: Fast Slew Rate
  757. Drive Strength Field: R0/5
  758. Speed Field: medium(100MHz)
  759. Open Drain Enable Field: Open Drain Disabled
  760. Pull / Keep Enable Field: Pull/Keeper Enabled
  761. Pull / Keep Select Field: Pull
  762. Pull Up / Down Config. Field: 100K Ohm Pull Up
  763. Hyst. Enable Field: Hysteresis Disabled */
  764. IOMUXC_SetPinConfig(
  765. IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
  766. 0xB0A9u); /* Slew Rate Field: Fast Slew Rate
  767. Drive Strength Field: R0/5
  768. Speed Field: medium(100MHz)
  769. Open Drain Enable Field: Open Drain Disabled
  770. Pull / Keep Enable Field: Pull/Keeper Enabled
  771. Pull / Keep Select Field: Pull
  772. Pull Up / Down Config. Field: 100K Ohm Pull Up
  773. Hyst. Enable Field: Hysteresis Disabled */
  774. IOMUXC_SetPinConfig(
  775. IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
  776. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  777. Drive Strength Field: R0/5
  778. Speed Field: max(200MHz)
  779. Open Drain Enable Field: Open Drain Disabled
  780. Pull / Keep Enable Field: Pull/Keeper Enabled
  781. Pull / Keep Select Field: Pull
  782. Pull Up / Down Config. Field: 100K Ohm Pull Up
  783. Hyst. Enable Field: Hysteresis Disabled */
  784. IOMUXC_SetPinConfig(
  785. IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
  786. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  787. Drive Strength Field: R0/5
  788. Speed Field: max(200MHz)
  789. Open Drain Enable Field: Open Drain Disabled
  790. Pull / Keep Enable Field: Pull/Keeper Enabled
  791. Pull / Keep Select Field: Pull
  792. Pull Up / Down Config. Field: 100K Ohm Pull Up
  793. Hyst. Enable Field: Hysteresis Disabled */
  794. IOMUXC_SetPinConfig(
  795. IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
  796. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  797. Drive Strength Field: R0/5
  798. Speed Field: max(200MHz)
  799. Open Drain Enable Field: Open Drain Disabled
  800. Pull / Keep Enable Field: Pull/Keeper Enabled
  801. Pull / Keep Select Field: Pull
  802. Pull Up / Down Config. Field: 100K Ohm Pull Up
  803. Hyst. Enable Field: Hysteresis Disabled */
  804. IOMUXC_SetPinConfig(
  805. IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
  806. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  807. Drive Strength Field: R0/5
  808. Speed Field: max(200MHz)
  809. Open Drain Enable Field: Open Drain Disabled
  810. Pull / Keep Enable Field: Pull/Keeper Enabled
  811. Pull / Keep Select Field: Pull
  812. Pull Up / Down Config. Field: 100K Ohm Pull Up
  813. Hyst. Enable Field: Hysteresis Disabled */
  814. IOMUXC_SetPinConfig(
  815. IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
  816. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  817. Drive Strength Field: R0/5
  818. Speed Field: max(200MHz)
  819. Open Drain Enable Field: Open Drain Disabled
  820. Pull / Keep Enable Field: Pull/Keeper Enabled
  821. Pull / Keep Select Field: Pull
  822. Pull Up / Down Config. Field: 100K Ohm Pull Up
  823. Hyst. Enable Field: Hysteresis Disabled */
  824. IOMUXC_SetPinConfig(
  825. IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
  826. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  827. Drive Strength Field: R0/5
  828. Speed Field: max(200MHz)
  829. Open Drain Enable Field: Open Drain Disabled
  830. Pull / Keep Enable Field: Pull/Keeper Enabled
  831. Pull / Keep Select Field: Pull
  832. Pull Up / Down Config. Field: 100K Ohm Pull Up
  833. Hyst. Enable Field: Hysteresis Disabled */
  834. IOMUXC_SetPinConfig(
  835. IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
  836. 0x31u); /* Slew Rate Field: Fast Slew Rate
  837. Drive Strength Field: R0/6
  838. Speed Field: low(50MHz)
  839. Open Drain Enable Field: Open Drain Disabled
  840. Pull / Keep Enable Field: Pull/Keeper Disabled
  841. Pull / Keep Select Field: Keeper
  842. Pull Up / Down Config. Field: 100K Ohm Pull Down
  843. Hyst. Enable Field: Hysteresis Disabled */
  844. IOMUXC_SetPinConfig(
  845. IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
  846. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  847. Drive Strength Field: R0/5
  848. Speed Field: max(200MHz)
  849. Open Drain Enable Field: Open Drain Disabled
  850. Pull / Keep Enable Field: Pull/Keeper Enabled
  851. Pull / Keep Select Field: Pull
  852. Pull Up / Down Config. Field: 100K Ohm Pull Up
  853. Hyst. Enable Field: Hysteresis Disabled */
  854. IOMUXC_SetPinConfig(
  855. IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
  856. 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
  857. Drive Strength Field: R0/5
  858. Speed Field: max(200MHz)
  859. Open Drain Enable Field: Open Drain Disabled
  860. Pull / Keep Enable Field: Pull/Keeper Enabled
  861. Pull / Keep Select Field: Pull
  862. Pull Up / Down Config. Field: 100K Ohm Pull Up
  863. Hyst. Enable Field: Hysteresis Disabled */
  864. IOMUXC_SetPinConfig(
  865. IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
  866. 0xB829u); /* Slew Rate Field: Fast Slew Rate
  867. Drive Strength Field: R0/5
  868. Speed Field: low(50MHz)
  869. Open Drain Enable Field: Open Drain Enabled
  870. Pull / Keep Enable Field: Pull/Keeper Enabled
  871. Pull / Keep Select Field: Pull
  872. Pull Up / Down Config. Field: 100K Ohm Pull Up
  873. Hyst. Enable Field: Hysteresis Disabled */
  874. }
  875. #ifndef BSP_USING_PHY
  876. void imxrt_enet_phy_reset_by_gpio(void)
  877. {
  878. gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
  879. GPIO_PinInit(GPIO1, 9, &gpio_config);
  880. GPIO_PinInit(GPIO1, 10, &gpio_config);
  881. /* pull up the ENET_INT before RESET. */
  882. GPIO_WritePinOutput(GPIO1, 10, 1);
  883. GPIO_WritePinOutput(GPIO1, 9, 0);
  884. rt_thread_delay(100);
  885. GPIO_WritePinOutput(GPIO1, 9, 1);
  886. }
  887. #endif /* BSP_USING_PHY */
  888. #endif /* BSP_USING_ETH */
  889. #ifdef BSP_USING_PHY
  890. void imxrt_phy_pins_init( void )
  891. {
  892. IOMUXC_SetPinMux(
  893. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
  894. 0U); /* Software Input On Field: Input Path is determined by functionality */
  895. IOMUXC_SetPinConfig(
  896. IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_B0_00 PAD functional properties : */
  897. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  898. Drive Strength Field: R0/6
  899. Speed Field: medium(100MHz)
  900. Open Drain Enable Field: Open Drain Disabled
  901. Pull / Keep Enable Field: Pull/Keeper Enabled
  902. Pull / Keep Select Field: Keeper
  903. Pull Up / Down Config. Field: 100K Ohm Pull Down
  904. Hyst. Enable Field: Hysteresis Disabled */
  905. }
  906. #endif /* BSP_USING_PHY */
  907. /*
  908. * When PXP fetch images from FlexSPI flash, the default FlexSPI RX buffer
  909. * configuration does not meet the PXP bandwidth requirement. Reconfigure
  910. * here.
  911. */
  912. void BOARD_ReconfigFlexSpiRxBuffer(void)
  913. {
  914. uint32_t ahbcr;
  915. /* Disable I cache and D cache */
  916. if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
  917. {
  918. SCB_DisableICache();
  919. }
  920. if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
  921. {
  922. SCB_DisableDCache();
  923. }
  924. ahbcr = FLEXSPI->AHBCR;
  925. /* Temporarily disable prefetching while changing the buffer settings */
  926. FLEXSPI->AHBCR = ahbcr & ~(FLEXSPI_AHBCR_CACHABLEEN_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK);
  927. /* Wait for FlexSPI idle to make sure no flash data transfer. */
  928. while ((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) == 0U)
  929. {
  930. }
  931. /* Allocate half of the prefetch buffer to the core */
  932. FLEXSPI->AHBRXBUFCR0[0] =
  933. FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_MSTRID(0) | FLEXSPI_AHBRXBUFCR0_BUFSZ(0x40);
  934. /* Disable dedicate prefetch buffer for DMA. */
  935. FLEXSPI->AHBRXBUFCR0[1] =
  936. FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_MSTRID(1) | FLEXSPI_AHBRXBUFCR0_BUFSZ(0x00);
  937. /* Disable dedicate prefetch buffer for DCP. */
  938. FLEXSPI->AHBRXBUFCR0[2] =
  939. FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_MSTRID(2) | FLEXSPI_AHBRXBUFCR0_BUFSZ(0x00);
  940. /* Other half of the buffer for other masters incl. PXP */
  941. FLEXSPI->AHBRXBUFCR0[3] =
  942. FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_MSTRID(3) | FLEXSPI_AHBRXBUFCR0_BUFSZ(0x40);
  943. FLEXSPI->AHBCR = ahbcr; /* Set AHBCR back to the original value */
  944. /* Enable I cache and D cache */
  945. SCB_EnableDCache();
  946. SCB_EnableICache();
  947. }
  948. /**
  949. * This function will initial rt1050 board.
  950. */
  951. void rt_hw_board_init()
  952. {
  953. /* Init board hardware. */
  954. /* Set the eLCDIF read_qos priority high, to make sure eLCDIF
  955. * can fetch data in time when PXP is used.
  956. */
  957. *((volatile uint32_t *)0x41044100) = 5;
  958. BOARD_ConfigMPU();
  959. // BOARD_ReconfigFlexSpiRxBuffer();
  960. BOARD_InitPins();
  961. BOARD_InitSemcPins();
  962. BOARD_BootClockRUN();
  963. NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  964. SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
  965. #ifdef BSP_USING_LPUART
  966. imxrt_uart_pins_init();
  967. #endif
  968. #ifdef BSP_USING_I2C
  969. imxrt_i2c_pins_init();
  970. #endif
  971. #ifdef BSP_USING_ETH
  972. imxrt_enet_pins_init();
  973. #endif
  974. #ifdef BSP_USING_PHY
  975. imxrt_phy_pins_init();
  976. #endif
  977. #ifdef BSP_USING_LCD
  978. imxrt_lcd_pins_init();
  979. #endif
  980. #ifdef BSP_USING_DMA
  981. imxrt_dma_init();
  982. #endif
  983. #ifdef RT_USING_HEAP
  984. rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
  985. #endif
  986. #ifdef RT_USING_COMPONENTS_INIT
  987. rt_components_board_init();
  988. #endif
  989. #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
  990. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  991. #endif
  992. }