fsl_enet_cmsis.c 23 KB

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  1. /*
  2. * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
  3. * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
  4. * Copyright 2016-2021 NXP. Not a Contribution.
  5. *
  6. * SPDX-License-Identifier: Apache-2.0
  7. *
  8. * Licensed under the Apache License, Version 2.0 (the License); you may
  9. * not use this file except in compliance with the License.
  10. * You may obtain a copy of the License at
  11. *
  12. * http://www.apache.org/licenses/LICENSE-2.0
  13. *
  14. * Unless required by applicable law or agreed to in writing, software
  15. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  16. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  17. * See the License for the specific language governing permissions and
  18. * limitations under the License.
  19. */
  20. #include "fsl_enet_cmsis.h"
  21. /* Component ID definition, used by tools. */
  22. #ifndef FSL_COMPONENT_ID
  23. #define FSL_COMPONENT_ID "platform.drivers.enet_cmsis"
  24. #endif
  25. #define ARM_ETH_MAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2)
  26. /* Define the alignment macro. */
  27. #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
  28. #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) && \
  29. ((!defined(FSL_SDK_DISBLE_L2CACHE_PRESENT)) || (FSL_SDK_DISBLE_L2CACHE_PRESENT == 0))
  30. #define CMSIS_CACHE_LINESIZE_MAX MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
  31. #define CMSIS_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, CMSIS_CACHE_LINESIZE_MAX)
  32. #elif defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
  33. #define CMSIS_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
  34. #endif
  35. #else
  36. #define CMSIS_ENET_BUFF_ALIGNMENT ENET_BUFF_ALIGNMENT
  37. #endif
  38. /* Define the ENET buffer information. */
  39. #define ENET_RXBD_NUM (4)
  40. #define ENET_TXBD_NUM (4)
  41. #define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
  42. #define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
  43. /* Define the timeout macro. */
  44. #define ENET_SMI_TIMEOUT_COUNT 0xffff
  45. typedef const struct _cmsis_enet_mac_resource
  46. {
  47. ENET_Type *base; /*!< ENET peripheral base address. */
  48. uint32_t (*GetFreq)(void); /*!< Function to get frequency. */
  49. } cmsis_enet_mac_resource_t;
  50. typedef struct _cmsis_enet_mac_driver_state
  51. {
  52. cmsis_enet_mac_resource_t *resource; /*!< Basic enet resource. */
  53. enet_handle_t *handle; /*!< ENET handler. */
  54. enet_buffer_config_t *buffers; /*!< Buffers res*/
  55. ARM_ETH_MAC_SignalEvent_t cb_event; /*!< Callback function. */
  56. volatile enet_tx_bd_struct_t *txBdTs; /*!< Tx timestamp index. */
  57. uint8_t flags; /*!< Control and state flags. */
  58. } cmsis_enet_mac_driver_state_t;
  59. static const ARM_DRIVER_VERSION s_enetDriverVersion = {ARM_ETH_MAC_API_VERSION, ARM_ETH_MAC_DRV_VERSION};
  60. /* Driver Capabilities */
  61. static const ARM_ETH_MAC_CAPABILITIES s_enetDriverCapabilities = {
  62. 1, /* checksum_offload_rx_ip4 */
  63. 0, /* checksum_offload_rx_ip6 */
  64. 1, /* checksum_offload_rx_udp */
  65. 1, /* checksum_offload_rx_tcp */
  66. 1, /* checksum_offload_rx_icmp */
  67. 1, /* checksum_offload_tx_ip4 */
  68. 1, /* checksum_offload_tx_ip6 */
  69. 1, /* checksum_offload_tx_udp */
  70. 1, /* checksum_offload_tx_tcp */
  71. 1, /* checksum_offload_tx_icmp */
  72. (RTE_ENET_RMII) ? ARM_ETH_INTERFACE_RMII : ARM_ETH_INTERFACE_MII, /* media_interface */
  73. 0, /* mac_address */
  74. 1, /* event_rx_frame */
  75. 1, /* event_tx_frame */
  76. 1, /* event_wakeup */
  77. 0 /* precision_timer */
  78. };
  79. static ARM_DRIVER_VERSION ENETx_GetVersion(void)
  80. {
  81. return s_enetDriverVersion;
  82. }
  83. static ARM_ETH_MAC_CAPABILITIES ENETx_GetCapabilities(void)
  84. {
  85. return s_enetDriverCapabilities;
  86. }
  87. static int32_t ENET_CommonInitialize(ARM_ETH_MAC_SignalEvent_t cb_event, cmsis_enet_mac_driver_state_t *enet)
  88. {
  89. if ((enet->flags & ENET_FLAG_INIT) == 0U)
  90. {
  91. enet->cb_event = cb_event;
  92. enet->flags = ENET_FLAG_INIT;
  93. }
  94. return ARM_DRIVER_OK;
  95. }
  96. static void ENET_SetInterruptCallback(ENET_Type *base,
  97. enet_handle_t *handle,
  98. #if FSL_FEATURE_ENET_QUEUE > 1
  99. uint32_t ringId,
  100. #endif
  101. enet_event_t event,
  102. enet_frame_info_t *frameInfo,
  103. void *userData)
  104. {
  105. uint32_t newEvent;
  106. switch (event)
  107. {
  108. case kENET_RxEvent:
  109. newEvent = ARM_ETH_MAC_EVENT_RX_FRAME;
  110. break;
  111. case kENET_TxEvent:
  112. newEvent = ARM_ETH_MAC_EVENT_TX_FRAME;
  113. break;
  114. case kENET_WakeUpEvent:
  115. newEvent = ARM_ETH_MAC_EVENT_WAKEUP;
  116. break;
  117. case kENET_TimeStampEvent:
  118. newEvent = ARM_ETH_MAC_EVENT_TIMER_ALARM;
  119. break;
  120. default:
  121. newEvent = ETH_MAC_EVENT_OTHERS;
  122. break;
  123. }
  124. /* User data is actually CMSIS driver callback. */
  125. if (userData != NULL)
  126. {
  127. ((ARM_ETH_MAC_SignalEvent_t)userData)(newEvent);
  128. }
  129. }
  130. static int32_t ENET_CommonUninitialize(cmsis_enet_mac_driver_state_t *enet)
  131. {
  132. enet->flags = ENET_FLAG_UNINIT;
  133. return ARM_DRIVER_OK;
  134. }
  135. static int32_t ENET_CommonControl(uint32_t control, uint32_t arg, cmsis_enet_mac_driver_state_t *enet)
  136. {
  137. int32_t result = ARM_DRIVER_OK;
  138. if (enet->flags == ENET_FLAG_UNINIT)
  139. {
  140. return ARM_DRIVER_ERROR;
  141. }
  142. switch (control)
  143. {
  144. case (uint32_t)ARM_ETH_MAC_CONFIGURE:
  145. {
  146. uint32_t rcr = enet->resource->base->RCR;
  147. uint32_t tcr = enet->resource->base->TCR;
  148. #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
  149. uint32_t ecr = enet->resource->base->ECR;
  150. if (FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(enet->resource->base) > 0)
  151. {
  152. ecr &= ~ENET_ECR_SPEED_MASK;
  153. }
  154. #endif /* FSL_FEATURE_ENET_HAS_AVB */
  155. switch (arg & (uint32_t)ARM_ETH_MAC_SPEED_Msk)
  156. {
  157. case (uint32_t)ARM_ETH_MAC_SPEED_10M:
  158. rcr |= ENET_RCR_RMII_10T_MASK;
  159. break;
  160. case (uint32_t)ARM_ETH_MAC_SPEED_100M:
  161. rcr &= ~ENET_RCR_RMII_10T_MASK;
  162. break;
  163. #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
  164. case (uint32_t)ARM_ETH_MAC_SPEED_1G:
  165. /* If the selected enet doesn't support 1G, return unsupported status */
  166. if (FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(enet->resource->base) > 0)
  167. {
  168. ecr |= ENET_ECR_SPEED_MASK;
  169. rcr &= ~ENET_RCR_RMII_10T_MASK;
  170. }
  171. else
  172. {
  173. result = ARM_DRIVER_ERROR_UNSUPPORTED;
  174. }
  175. break;
  176. #endif /* FSL_FEATURE_ENET_HAS_AVB */
  177. default:
  178. result = ARM_DRIVER_ERROR_UNSUPPORTED;
  179. break;
  180. }
  181. if (result != ARM_DRIVER_OK)
  182. {
  183. return result;
  184. }
  185. switch (arg & ARM_ETH_MAC_DUPLEX_Msk)
  186. {
  187. case (uint32_t)ARM_ETH_MAC_DUPLEX_HALF:
  188. rcr |= ENET_RCR_DRT_MASK;
  189. tcr &= ~ENET_TCR_FDEN_MASK;
  190. break;
  191. case (uint32_t)ARM_ETH_MAC_DUPLEX_FULL:
  192. rcr &= ~ENET_RCR_DRT_MASK;
  193. tcr |= ENET_TCR_FDEN_MASK;
  194. break;
  195. default:
  196. result = ARM_DRIVER_ERROR_UNSUPPORTED;
  197. break;
  198. }
  199. if (result != ARM_DRIVER_OK)
  200. {
  201. return result;
  202. }
  203. if ((arg & (ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX | ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX)) != 0U)
  204. {
  205. return ARM_DRIVER_ERROR_UNSUPPORTED;
  206. }
  207. if ((arg & ARM_ETH_MAC_ADDRESS_BROADCAST) != 0U)
  208. {
  209. rcr &= ~ENET_RCR_BC_REJ_MASK;
  210. }
  211. else
  212. {
  213. rcr |= ENET_RCR_BC_REJ_MASK;
  214. }
  215. if ((arg & ARM_ETH_MAC_ADDRESS_MULTICAST) != 0U)
  216. {
  217. return ARM_DRIVER_ERROR_UNSUPPORTED;
  218. }
  219. if ((arg & ARM_ETH_MAC_ADDRESS_ALL) != 0U)
  220. {
  221. rcr |= ENET_RCR_PROM_MASK;
  222. }
  223. if ((arg & ARM_ETH_MAC_LOOPBACK) != 0U)
  224. {
  225. /* Loop back only supported on MII mode. */
  226. if ((rcr & ENET_RCR_RMII_MODE_MASK) == 0U)
  227. {
  228. rcr |= ENET_RCR_LOOP_MASK;
  229. rcr &= ~ENET_RCR_DRT_MASK;
  230. }
  231. }
  232. enet->resource->base->RCR = rcr;
  233. enet->resource->base->TCR = tcr;
  234. #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
  235. if (FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(enet->resource->base) > 0)
  236. {
  237. enet->resource->base->ECR = ecr;
  238. }
  239. #endif /* FSL_FEATURE_ENET_HAS_AVB */
  240. }
  241. break;
  242. case (uint32_t)ARM_ETH_MAC_CONTROL_TX:
  243. if (arg != 0U)
  244. {
  245. enet->resource->base->TDAR = ENET_TDAR_TDAR_MASK;
  246. }
  247. else
  248. {
  249. enet->resource->base->TDAR &= ~ENET_TDAR_TDAR_MASK;
  250. }
  251. break;
  252. case (uint32_t)ARM_ETH_MAC_CONTROL_RX:
  253. if (arg != 0U)
  254. {
  255. ENET_ActiveRead(enet->resource->base);
  256. }
  257. else
  258. {
  259. enet->resource->base->RDAR &= ~ENET_RDAR_RDAR_MASK;
  260. }
  261. break;
  262. case (uint32_t)ARM_ETH_MAC_SLEEP:
  263. ENET_EnableSleepMode(enet->resource->base, (bool)arg);
  264. break;
  265. default:
  266. result = ARM_DRIVER_ERROR_UNSUPPORTED;
  267. break;
  268. }
  269. return result;
  270. }
  271. static int32_t ENET_CommonPowerControl(ARM_POWER_STATE state, cmsis_enet_mac_driver_state_t *enet)
  272. {
  273. int32_t result = ARM_DRIVER_OK;
  274. ARM_ETH_MAC_CAPABILITIES capabilities;
  275. switch (state)
  276. {
  277. case ARM_POWER_OFF:
  278. if ((enet->flags & ENET_FLAG_POWER) != 0U)
  279. {
  280. (void)ENET_CommonControl(ARM_ETH_MAC_CONTROL_TX, 0, enet);
  281. (void)ENET_CommonControl(ARM_ETH_MAC_CONTROL_RX, 0, enet);
  282. ENET_Reset(enet->resource->base);
  283. ENET_Deinit(enet->resource->base);
  284. enet->flags = ENET_FLAG_INIT;
  285. }
  286. break;
  287. case ARM_POWER_LOW:
  288. result = ARM_DRIVER_ERROR_UNSUPPORTED;
  289. break;
  290. case ARM_POWER_FULL:
  291. {
  292. if (enet->flags == ENET_FLAG_UNINIT)
  293. {
  294. return ARM_DRIVER_ERROR;
  295. }
  296. if ((enet->flags & ENET_FLAG_POWER) != 0U)
  297. {
  298. /* Driver already powered */
  299. break;
  300. }
  301. enet_config_t config;
  302. uint8_t macAddr[6] = {0};
  303. uint32_t freq;
  304. /* Get default configuration. */
  305. ENET_GetDefaultConfig(&config);
  306. /* Change the MII interface mode according to the MII interface macro. */
  307. capabilities = ENETx_GetCapabilities();
  308. if (capabilities.media_interface == (uint32_t)ARM_ETH_INTERFACE_MII)
  309. {
  310. config.miiMode = kENET_MiiMode;
  311. }
  312. else if (capabilities.media_interface == (uint32_t)ARM_ETH_INTERFACE_RMII)
  313. {
  314. #if defined(RTE_ENET_RGMII) && RTE_ENET_RGMII
  315. #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
  316. if (FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(enet->resource->base) > 0)
  317. {
  318. config.miiMode = kENET_RgmiiMode;
  319. }
  320. else
  321. {
  322. result = ARM_DRIVER_ERROR_UNSUPPORTED;
  323. break;
  324. }
  325. #endif /* FSL_FEATURE_ENET_HAS_AVB */
  326. #else
  327. config.miiMode = kENET_RmiiMode;
  328. #endif /* RTE_ENET_RGMII */
  329. }
  330. else
  331. {
  332. /* Intentional empty */
  333. }
  334. /* Enable the tx/rx interrupt mode. */
  335. config.interrupt = (uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt |
  336. (uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt;
  337. /* Enable tx accelerate function. */
  338. config.txAccelerConfig = (uint8_t)kENET_TxAccelIpCheckEnabled | (uint8_t)kENET_TxAccelProtoCheckEnabled;
  339. /* Initialize Ethernet Mac. */
  340. freq = enet->resource->GetFreq();
  341. (void)ENET_Init(enet->resource->base, enet->handle, &config, enet->buffers, &macAddr[0], freq);
  342. /* Callback setup */
  343. ENET_SetCallback(enet->handle, ENET_SetInterruptCallback, (void *)enet->cb_event);
  344. enet->flags |= ENET_FLAG_POWER;
  345. break;
  346. }
  347. default:
  348. result = ARM_DRIVER_ERROR_UNSUPPORTED;
  349. break;
  350. }
  351. return result;
  352. }
  353. static int32_t ENET_Phy_Write(cmsis_enet_mac_resource_t *enet, uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
  354. {
  355. uint32_t counter;
  356. /* Clear the SMI interrupt event. */
  357. ENET_ClearInterruptStatus(enet->base, ENET_EIR_MII_MASK);
  358. /* Starts a SMI write command. */
  359. ENET_StartSMIWrite(enet->base, phy_addr, reg_addr, kENET_MiiWriteValidFrame, data);
  360. /* Wait for SMI complete. */
  361. for (counter = ENET_SMI_TIMEOUT_COUNT; counter > 0U; counter--)
  362. {
  363. if ((ENET_GetInterruptStatus(enet->base) & ENET_EIR_MII_MASK) != 0U)
  364. {
  365. break;
  366. }
  367. }
  368. /* Check for timeout. */
  369. if (counter == 0U)
  370. {
  371. return ARM_DRIVER_ERROR;
  372. }
  373. /* Clear MII interrupt event. */
  374. ENET_ClearInterruptStatus(enet->base, ENET_EIR_MII_MASK);
  375. return ARM_DRIVER_OK;
  376. }
  377. static int32_t ENET_Phy_Read(cmsis_enet_mac_resource_t *enet, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
  378. {
  379. assert(data);
  380. uint32_t counter;
  381. /* Clear the MII interrupt event. */
  382. ENET_ClearInterruptStatus(enet->base, ENET_EIR_MII_MASK);
  383. /* Starts a SMI read command operation. */
  384. ENET_StartSMIRead(enet->base, phy_addr, reg_addr, kENET_MiiReadValidFrame);
  385. /* Wait for MII complete. */
  386. for (counter = ENET_SMI_TIMEOUT_COUNT; counter > 0U; counter--)
  387. {
  388. if ((ENET_GetInterruptStatus(enet->base) & ENET_EIR_MII_MASK) != 0U)
  389. {
  390. break;
  391. }
  392. }
  393. /* Check for timeout. */
  394. if (counter == 0U)
  395. {
  396. return ARM_DRIVER_ERROR;
  397. }
  398. /* Get data from MII register. */
  399. *data = (uint16_t)ENET_ReadSMIData(enet->base);
  400. /* Clear MII interrupt event. */
  401. ENET_ClearInterruptStatus(enet->base, ENET_EIR_MII_MASK);
  402. return ARM_DRIVER_OK;
  403. }
  404. static int32_t ENET_CommonSendFrame(cmsis_enet_mac_driver_state_t *enet,
  405. const uint8_t *frame,
  406. uint32_t len,
  407. uint32_t flags)
  408. {
  409. status_t status;
  410. /* The SDK send frame driver is send with a whole frame and
  411. * the timestamp will be enabled automatically when it is a PTP frame
  412. * by parse the frame.
  413. */
  414. if ((flags & (ARM_ETH_MAC_TX_FRAME_FRAGMENT | ARM_ETH_MAC_TX_FRAME_TIMESTAMP)) != 0U)
  415. {
  416. return ARM_DRIVER_ERROR;
  417. }
  418. status = ENET_SendFrame(enet->resource->base, enet->handle, frame, len, 0, false, NULL);
  419. if (status == kStatus_ENET_TxFrameOverLen)
  420. {
  421. return ARM_DRIVER_ERROR_PARAMETER;
  422. }
  423. else if (status == kStatus_ENET_TxFrameBusy)
  424. {
  425. return ARM_DRIVER_ERROR_BUSY;
  426. }
  427. else if (status == kStatus_ENET_TxFrameFail)
  428. {
  429. return ARM_DRIVER_ERROR;
  430. }
  431. else
  432. {
  433. return ARM_DRIVER_OK;
  434. }
  435. }
  436. static uint32_t ENET_CommonGetFrameSize(cmsis_enet_mac_driver_state_t *enet)
  437. {
  438. status_t status;
  439. uint32_t length = 0;
  440. status = ENET_GetRxFrameSize(enet->handle, &length, 0);
  441. if (status == kStatus_ENET_RxFrameError)
  442. {
  443. /* Should update the buffers. */
  444. (void)ENET_ReadFrame(enet->resource->base, enet->handle, NULL, 0, 0, NULL);
  445. }
  446. return length;
  447. }
  448. static int32_t ENET_CommonReadFrame(cmsis_enet_mac_driver_state_t *enet, uint8_t *frame, uint32_t len)
  449. {
  450. status_t status;
  451. status = ENET_ReadFrame(enet->resource->base, enet->handle, frame, len, 0, NULL);
  452. if (status != kStatus_Success)
  453. {
  454. return ARM_DRIVER_ERROR;
  455. }
  456. return (int32_t)len;
  457. }
  458. #if RTE_ENET
  459. /*! @brief Buffer descriptors should be in non-cacheable region and should be align to "ENET_BUFF_ALIGNMENT". */
  460. AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM], ENET_BUFF_ALIGNMENT);
  461. AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM], ENET_BUFF_ALIGNMENT);
  462. /*! @brief The data buffers can be in cacheable region or in non-cacheable region.
  463. * If use cacheable region, the alignment size should be the maximum size of "CACHE LINE SIZE" and "ENET_BUFF_ALIGNMENT"
  464. * If use non-cache region, the alignment size is the "ENET_BUFF_ALIGNMENT".
  465. */
  466. SDK_ALIGN(static uint8_t g_rxDataBuff[ENET_RXBD_NUM][SDK_SIZEALIGN(ENET_RXBUFF_SIZE, CMSIS_ENET_BUFF_ALIGNMENT)],
  467. CMSIS_ENET_BUFF_ALIGNMENT);
  468. SDK_ALIGN(static uint8_t g_txDataBuff[ENET_TXBD_NUM][SDK_SIZEALIGN(ENET_TXBUFF_SIZE, CMSIS_ENET_BUFF_ALIGNMENT)],
  469. CMSIS_ENET_BUFF_ALIGNMENT);
  470. extern void ENET0_InitPins(void);
  471. extern void ENET0_DeinitPins(void);
  472. #if (defined(ENET) && defined(ENET_1G))
  473. static cmsis_enet_mac_resource_t ENET0_Resource = {ENET_1G, ENET0_GetFreq};
  474. #elif defined(ENET)
  475. static cmsis_enet_mac_resource_t ENET0_Resource = {ENET, ENET0_GetFreq};
  476. #elif defined(ENET0)
  477. static cmsis_enet_mac_resource_t ENET0_Resource = {ENET0, ENET0_GetFreq};
  478. #elif defined(ENET1)
  479. static cmsis_enet_mac_resource_t ENET0_Resource = {ENET1, ENET0_GetFreq};
  480. #else
  481. static cmsis_enet_mac_resource_t ENET0_Resource = {CONNECTIVITY__ENET0, ENET0_GetFreq};
  482. #endif
  483. static enet_handle_t ENET0_Handle;
  484. static enet_buffer_config_t ENET0_BuffConfig = {ENET_RXBD_NUM,
  485. ENET_TXBD_NUM,
  486. SDK_SIZEALIGN(ENET_RXBUFF_SIZE, CMSIS_ENET_BUFF_ALIGNMENT),
  487. SDK_SIZEALIGN(ENET_TXBUFF_SIZE, CMSIS_ENET_BUFF_ALIGNMENT),
  488. &g_rxBuffDescrip[0],
  489. &g_txBuffDescrip[0],
  490. &g_rxDataBuff[0][0],
  491. &g_txDataBuff[0][0],
  492. (bool)true,
  493. (bool)true,
  494. NULL};
  495. static cmsis_enet_mac_driver_state_t ENET0_DriverState = {&ENET0_Resource, &ENET0_Handle, &ENET0_BuffConfig};
  496. static int32_t ENET0_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event)
  497. {
  498. ENET0_InitPins();
  499. return ENET_CommonInitialize(cb_event, &ENET0_DriverState);
  500. }
  501. static int32_t ENET0_Uninitialize(void)
  502. {
  503. ENET0_DeinitPins();
  504. return ENET_CommonUninitialize(&ENET0_DriverState);
  505. }
  506. static int32_t ENET0_PowerControl(ARM_POWER_STATE state)
  507. {
  508. return ENET_CommonPowerControl(state, &ENET0_DriverState);
  509. }
  510. static int32_t ENET0_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr)
  511. {
  512. ENET_GetMacAddr(ENET0_Resource.base, &ptr_addr->b[0]);
  513. return ARM_DRIVER_OK;
  514. }
  515. static int32_t ENET0_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr)
  516. {
  517. uint8_t mac[6];
  518. (void)memcpy((void *)&mac[0], (const void *)ptr_addr, 6);
  519. ENET_SetMacAddr(ENET0_Resource.base, &mac[0]);
  520. return ARM_DRIVER_OK;
  521. }
  522. static int32_t ENET0_TransmitFrame(const uint8_t *frame, uint32_t len, uint32_t flags)
  523. {
  524. return ENET_CommonSendFrame(&ENET0_DriverState, frame, len, flags);
  525. }
  526. static uint32_t ENET0_GetReceiveFrameSize(void)
  527. {
  528. return ENET_CommonGetFrameSize(&ENET0_DriverState);
  529. }
  530. static int32_t ENET0_ReceiveFrame(uint8_t *frame, uint32_t len)
  531. {
  532. return ENET_CommonReadFrame(&ENET0_DriverState, frame, len);
  533. }
  534. static int32_t ENET0_Control(uint32_t control, uint32_t arg)
  535. {
  536. return ENET_CommonControl(control, arg, &ENET0_DriverState);
  537. }
  538. static int32_t ENET0_PhyWrite(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
  539. {
  540. return ENET_Phy_Write(&ENET0_Resource, phy_addr, reg_addr, data);
  541. }
  542. static int32_t ENET0_PhyRead(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
  543. {
  544. return ENET_Phy_Read(&ENET0_Resource, phy_addr, reg_addr, data);
  545. }
  546. static int32_t ENET0_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)
  547. {
  548. return ARM_DRIVER_ERROR_UNSUPPORTED;
  549. }
  550. static int32_t ENET0_GetRxFrameTime(ARM_ETH_MAC_TIME *time)
  551. {
  552. return ARM_DRIVER_ERROR_UNSUPPORTED;
  553. }
  554. static int32_t ENET0_GetTxFrameTime(ARM_ETH_MAC_TIME *time)
  555. {
  556. return ARM_DRIVER_ERROR_UNSUPPORTED;
  557. }
  558. static int32_t ENET0_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time)
  559. {
  560. return ARM_DRIVER_ERROR_UNSUPPORTED;
  561. }
  562. ARM_DRIVER_ETH_MAC Driver_ETH_MAC0 = {ENETx_GetVersion,
  563. ENETx_GetCapabilities,
  564. ENET0_Initialize,
  565. ENET0_Uninitialize,
  566. ENET0_PowerControl,
  567. ENET0_GetMacAddress,
  568. ENET0_SetMacAddress,
  569. ENET0_SetAddressFilter,
  570. ENET0_TransmitFrame,
  571. ENET0_ReceiveFrame,
  572. ENET0_GetReceiveFrameSize,
  573. ENET0_GetRxFrameTime,
  574. ENET0_GetTxFrameTime,
  575. ENET0_ControlTimer,
  576. ENET0_Control,
  577. ENET0_PhyRead,
  578. ENET0_PhyWrite};
  579. #endif