fsl_aipstz.h 5.0 KB

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  1. /*
  2. * Copyright (c) 2015, Freescale Semiconductor, Inc.
  3. * Copyright 2020 NXP
  4. * All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. */
  8. #ifndef _FSL_AIPSTZ_H_
  9. #define _FSL_AIPSTZ_H_
  10. #include "fsl_common.h"
  11. /*!
  12. * @addtogroup aipstz
  13. * @{
  14. */
  15. /*******************************************************************************
  16. * Definitions
  17. ******************************************************************************/
  18. /*! @name Driver version */
  19. /*@{*/
  20. #define FSL_AIPSTZ_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
  21. /*@}*/
  22. /*! @brief List of AIPSTZ privilege configuration.*/
  23. typedef enum _aipstz_master_privilege_level
  24. {
  25. kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */
  26. kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */
  27. kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */
  28. kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */
  29. } aipstz_master_privilege_level_t;
  30. /*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/
  31. typedef enum _aipstz_master
  32. {
  33. kAIPSTZ_Master0 = (0x400U | 28U),
  34. kAIPSTZ_Master1 = (0x400U | 24U),
  35. kAIPSTZ_Master2 = (0x400U | 20U),
  36. kAIPSTZ_Master3 = (0x400U | 16U),
  37. kAIPSTZ_Master5 = (0x400U | 8U)
  38. } aipstz_master_t;
  39. /*! @brief List of AIPSTZ peripheral access control configuration.*/
  40. typedef enum _aipstz_peripheral_access_control
  41. {
  42. kAIPSTZ_PeripheralAllowUntrustedMaster = 1U,
  43. kAIPSTZ_PeripheralWriteProtected = (1U << 1),
  44. kAIPSTZ_PeripheralRequireSupervisor = (1U << 2),
  45. kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3)
  46. } aipstz_peripheral_access_control_t;
  47. /*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and
  48. * shift for lower 8 bits.*/
  49. typedef enum _aipstz_peripheral
  50. {
  51. kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28),
  52. kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24),
  53. kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20),
  54. kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16),
  55. kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12),
  56. kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8),
  57. kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4),
  58. kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0),
  59. kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28),
  60. kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24),
  61. kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20),
  62. kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16),
  63. kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12),
  64. kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8),
  65. kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4),
  66. kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0),
  67. kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28),
  68. kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24),
  69. kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20),
  70. kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16),
  71. kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12),
  72. kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8),
  73. kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4),
  74. kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0),
  75. kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28),
  76. kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24),
  77. kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20),
  78. kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16),
  79. kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12),
  80. kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8),
  81. kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4),
  82. kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0),
  83. kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28),
  84. kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24)
  85. } aipstz_peripheral_t;
  86. /*******************************************************************************
  87. * API
  88. ******************************************************************************/
  89. #if defined(__cplusplus)
  90. extern "C" {
  91. #endif
  92. /*!
  93. * @name Initialization and deinitialization
  94. * @{
  95. */
  96. /*!
  97. * @brief Configure the privilege level for master.
  98. *
  99. * @param base AIPSTZ peripheral base pointer
  100. * @param master Masters for AIPSTZ.
  101. * @param privilegeConfig Configuration is ORed from @ref aipstz_master_privilege_level_t.
  102. */
  103. void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig);
  104. /*!
  105. * @brief Configure the access for peripheral.
  106. *
  107. * @param base AIPSTZ peripheral base pointer
  108. * @param peripheral Peripheral for AIPSTZ.
  109. * @param accessControl Configuration is ORed from @ref aipstz_peripheral_access_control_t.
  110. */
  111. void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl);
  112. /*! @}*/
  113. #if defined(__cplusplus)
  114. }
  115. #endif
  116. /*! @}*/
  117. #endif /* _FSL_AIPSTZ_H_ */