fsl_flexspi.h 37 KB

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  1. /*
  2. * Copyright (c) 2016, Freescale Semiconductor, Inc.
  3. * Copyright 2016-2021 NXP
  4. * All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. */
  8. #ifndef __FSL_FLEXSPI_H_
  9. #define __FSL_FLEXSPI_H_
  10. #include <stddef.h>
  11. #include "fsl_device_registers.h"
  12. #include "fsl_common.h"
  13. /*!
  14. * @addtogroup flexspi
  15. * @{
  16. */
  17. /*******************************************************************************
  18. * Definitions
  19. ******************************************************************************/
  20. /*! @name Driver version */
  21. /*@{*/
  22. /*! @brief FLEXSPI driver version 2.3.5. */
  23. #define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 5))
  24. /*@}*/
  25. #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
  26. /*! @brief Formula to form FLEXSPI instructions in LUT table. */
  27. #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
  28. (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
  29. FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
  30. /*! @brief Status structure of FLEXSPI.*/
  31. enum
  32. {
  33. kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */
  34. kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout
  35. error occurred during FLEXSPI transfer. */
  36. kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution
  37. timeout error occurred during FLEXSPI transfer. */
  38. kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3), /*!< IP command grant timeout error
  39. occurred during FLEXSPI transfer. */
  40. };
  41. /*! @brief CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command. */
  42. enum
  43. {
  44. kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */
  45. kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */
  46. kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */
  47. kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */
  48. kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
  49. kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
  50. kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
  51. kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
  52. kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */
  53. kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */
  54. kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */
  55. kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */
  56. kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/
  57. kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller,
  58. dummy cycles decided by RWDS. */
  59. kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */
  60. kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */
  61. kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */
  62. kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
  63. kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
  64. kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
  65. kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
  66. kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */
  67. kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */
  68. kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */
  69. kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */
  70. kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/
  71. kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller,
  72. dummy cycles decided by RWDS. */
  73. kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the
  74. instruction start pointer for next sequence */
  75. };
  76. /*! @brief pad definition of FLEXSPI, use to form LUT instruction. */
  77. typedef enum _flexspi_pad
  78. {
  79. kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */
  80. kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */
  81. kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */
  82. kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */
  83. } flexspi_pad_t;
  84. /*! @brief FLEXSPI interrupt status flags.*/
  85. typedef enum _flexspi_flags
  86. {
  87. kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */
  88. #if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN
  89. kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK, /*!< AHB Bus error flag. */
  90. #else
  91. kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */
  92. #endif
  93. kFLEXSPI_SckStoppedBecauseTxEmptyFlag =
  94. FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command
  95. sequence because Async TX FIFO empty. */
  96. kFLEXSPI_SckStoppedBecauseRxFullFlag =
  97. FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command
  98. sequence because Async RX FIFO full. */
  99. #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
  100. kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */
  101. #endif
  102. kFLEXSPI_IpTxFifoWatermarkEmptyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */
  103. kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */
  104. kFLEXSPI_AhbCommandSequenceErrorFlag =
  105. FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */
  106. kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */
  107. kFLEXSPI_AhbCommandGrantTimeoutFlag =
  108. FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */
  109. kFLEXSPI_IpCommandGrantTimeoutFlag =
  110. FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */
  111. kFLEXSPI_IpCommandExecutionDoneFlag =
  112. FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */
  113. kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */
  114. } flexspi_flags_t;
  115. /*! @brief FLEXSPI sample clock source selection for Flash Reading.*/
  116. typedef enum _flexspi_read_sample_clock
  117. {
  118. kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U, /*!< Dummy Read strobe generated by FlexSPI Controller
  119. and loopback internally. */
  120. kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller
  121. and loopback from DQS pad. */
  122. kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */
  123. kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */
  124. } flexspi_read_sample_clock_t;
  125. /*! @brief FLEXSPI interval unit for flash device select.*/
  126. typedef enum _flexspi_cs_interval_cycle_unit
  127. {
  128. kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */
  129. kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */
  130. } flexspi_cs_interval_cycle_unit_t;
  131. /*! @brief FLEXSPI AHB wait interval unit for writing.*/
  132. typedef enum _flexspi_ahb_write_wait_unit
  133. {
  134. kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */
  135. kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */
  136. kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */
  137. kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */
  138. kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */
  139. kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */
  140. kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */
  141. kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */
  142. } flexspi_ahb_write_wait_unit_t;
  143. /*! @brief Error Code when IP command Error detected.*/
  144. typedef enum _flexspi_ip_error_code
  145. {
  146. kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */
  147. kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */
  148. kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
  149. kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR
  150. used in DDR sequence. */
  151. kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
  152. used in SDR sequence. */
  153. kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole
  154. flash address range (A1/A2/B1/B2). */
  155. kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */
  156. kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */
  157. } flexspi_ip_error_code_t;
  158. /*! @brief Error Code when AHB command Error detected.*/
  159. typedef enum _flexspi_ahb_error_code
  160. {
  161. kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */
  162. kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction
  163. used in the sequence. */
  164. kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
  165. kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used
  166. in DDR sequence. */
  167. kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
  168. used in SDR sequence. */
  169. kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U, /*!< Sequence execution timeout. */
  170. } flexspi_ahb_error_code_t;
  171. /*! @brief FLEXSPI operation port select.*/
  172. typedef enum _flexspi_port
  173. {
  174. kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
  175. kFLEXSPI_PortA2, /*!< Access flash on A2 port. */
  176. kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
  177. kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
  178. kFLEXSPI_PortCount
  179. } flexspi_port_t;
  180. /*! @brief Trigger source of current command sequence granted by arbitrator.*/
  181. typedef enum _flexspi_arb_command_source
  182. {
  183. kFLEXSPI_AhbReadCommand = 0x0U,
  184. kFLEXSPI_AhbWriteCommand = 0x1U,
  185. kFLEXSPI_IpCommand = 0x2U,
  186. kFLEXSPI_SuspendedCommand = 0x3U,
  187. } flexspi_arb_command_source_t;
  188. /*! @brief Command type. */
  189. typedef enum _flexspi_command_type
  190. {
  191. kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */
  192. kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */
  193. kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */
  194. kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */
  195. } flexspi_command_type_t;
  196. typedef struct _flexspi_ahbBuffer_config
  197. {
  198. uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */
  199. uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */
  200. uint16_t bufferSize; /*!< AHB buffer size in byte. */
  201. bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows
  202. prefetch disable/enable separately for each master. */
  203. } flexspi_ahbBuffer_config_t;
  204. /*! @brief FLEXSPI configuration structure. */
  205. typedef struct _flexspi_config
  206. {
  207. flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */
  208. bool enableSckFreeRunning; /*!< Enable/disable SCK output free-running. */
  209. #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
  210. bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins
  211. (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */
  212. #endif
  213. bool enableDoze; /*!< Enable/disable doze mode support. */
  214. bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half
  215. speed commands. */
  216. bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
  217. output, when enable, Port B flash access is not available. */
  218. bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices
  219. when enabled, same configuration in FLASHA1CRx is applied to all. */
  220. uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution,
  221. timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */
  222. uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after
  223. ipGrantTimeoutCycle*1024 AHB clock cycles. */
  224. uint8_t txWatermark; /*!< FLEXSPI IP transmit watermark value. */
  225. uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */
  226. struct
  227. {
  228. #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
  229. bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */
  230. #endif
  231. #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
  232. bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */
  233. #endif
  234. uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant,
  235. timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */
  236. uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access,
  237. timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */
  238. uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence
  239. resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */
  240. flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */
  241. bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer
  242. when FLEXSPI returns STOP mode ACK. */
  243. bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation.
  244. when enable, there is no AHB read burst start address alignment limitation. */
  245. bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI
  246. will fetch more data than current AHB burst. */
  247. bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled,
  248. FLEXSPI return before waiting for command execution finished. */
  249. bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */
  250. } ahbConfig;
  251. } flexspi_config_t;
  252. /*! @brief External device configuration items. */
  253. typedef struct _flexspi_device_config
  254. {
  255. uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */
  256. bool isSck2Enabled; /*!< FLEXSPI use SCK2. */
  257. uint32_t flashSize; /*!< Flash size in KByte. */
  258. flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */
  259. uint16_t CSInterval; /*!< CS line assert interval, multiply CS interval unit to
  260. get the CS line assert interval cycles. */
  261. uint8_t CSHoldTime; /*!< CS line hold time. */
  262. uint8_t CSSetupTime; /*!< CS line setup time. */
  263. uint8_t dataValidTime; /*!< Data valid time for external device. */
  264. uint8_t columnspace; /*!< Column space size. */
  265. bool enableWordAddress; /*!< If enable word address.*/
  266. uint8_t AWRSeqIndex; /*!< Sequence ID for AHB write command. */
  267. uint8_t AWRSeqNumber; /*!< Sequence number for AHB write command. */
  268. uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */
  269. uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */
  270. flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */
  271. uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, multiply AHB write interval
  272. unit to get the AHB write wait cycles. */
  273. bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask
  274. when writing to external device. */
  275. } flexspi_device_config_t;
  276. /*! @brief Transfer structure for FLEXSPI. */
  277. typedef struct _flexspi_transfer
  278. {
  279. uint32_t deviceAddress; /*!< Operation device address. */
  280. flexspi_port_t port; /*!< Operation port. */
  281. flexspi_command_type_t cmdType; /*!< Execution command type. */
  282. uint8_t seqIndex; /*!< Sequence ID for command. */
  283. uint8_t SeqNumber; /*!< Sequence number for command. */
  284. uint32_t *data; /*!< Data buffer. */
  285. size_t dataSize; /*!< Data size in bytes. */
  286. } flexspi_transfer_t;
  287. /* Forward declaration of the handle typedef. */
  288. typedef struct _flexspi_handle flexspi_handle_t;
  289. /*! @brief FLEXSPI transfer callback function. */
  290. typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base,
  291. flexspi_handle_t *handle,
  292. status_t status,
  293. void *userData);
  294. /*! @brief Transfer handle structure for FLEXSPI. */
  295. struct _flexspi_handle
  296. {
  297. uint32_t state; /*!< Internal state for FLEXSPI transfer */
  298. uint32_t *data; /*!< Data buffer. */
  299. size_t dataSize; /*!< Remaining Data size in bytes. */
  300. size_t transferTotalSize; /*!< Total Data size in bytes. */
  301. flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */
  302. void *userData; /*!< FLEXSPI callback function parameter.*/
  303. };
  304. /*******************************************************************************
  305. * API
  306. ******************************************************************************/
  307. #if defined(__cplusplus)
  308. extern "C" {
  309. #endif /*_cplusplus. */
  310. /*!
  311. * @name Initialization and deinitialization
  312. * @{
  313. */
  314. /*!
  315. * @brief Get the instance number for FLEXSPI.
  316. *
  317. * @param base FLEXSPI base pointer.
  318. */
  319. uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
  320. /*!
  321. * @brief Check and clear IP command execution errors.
  322. *
  323. * @param base FLEXSPI base pointer.
  324. * @param status interrupt status.
  325. */
  326. status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
  327. /*!
  328. * @brief Initializes the FLEXSPI module and internal state.
  329. *
  330. * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the
  331. * input configure parameters. Users should call this function before any FLEXSPI operations.
  332. *
  333. * @param base FLEXSPI peripheral base address.
  334. * @param config FLEXSPI configure structure.
  335. */
  336. void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config);
  337. /*!
  338. * @brief Gets default settings for FLEXSPI.
  339. *
  340. * @param config FLEXSPI configuration structure.
  341. */
  342. void FLEXSPI_GetDefaultConfig(flexspi_config_t *config);
  343. /*!
  344. * @brief Deinitializes the FLEXSPI module.
  345. *
  346. * Clears the FLEXSPI state and FLEXSPI module registers.
  347. * @param base FLEXSPI peripheral base address.
  348. */
  349. void FLEXSPI_Deinit(FLEXSPI_Type *base);
  350. /*!
  351. * @brief Update FLEXSPI DLL value depending on currently flexspi root clock.
  352. *
  353. * @param base FLEXSPI peripheral base address.
  354. * @param config Flash configuration parameters.
  355. * @param port FLEXSPI Operation port.
  356. */
  357. void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
  358. /*!
  359. * @brief Configures the connected device parameter.
  360. *
  361. * This function configures the connected device relevant parameters, such as the size, command, and so on.
  362. * The flash configuration value cannot have a default value. The user needs to configure it according to the
  363. * connected device.
  364. *
  365. * @param base FLEXSPI peripheral base address.
  366. * @param config Flash configuration parameters.
  367. * @param port FLEXSPI Operation port.
  368. */
  369. void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
  370. /*!
  371. * @brief Software reset for the FLEXSPI logic.
  372. *
  373. * This function sets the software reset flags for both AHB and buffer domain and
  374. * resets both AHB buffer and also IP FIFOs.
  375. *
  376. * @param base FLEXSPI peripheral base address.
  377. */
  378. static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
  379. {
  380. base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
  381. while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK))
  382. {
  383. }
  384. }
  385. /*!
  386. * @brief Enables or disables the FLEXSPI module.
  387. *
  388. * @param base FLEXSPI peripheral base address.
  389. * @param enable True means enable FLEXSPI, false means disable.
  390. */
  391. static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
  392. {
  393. if (enable)
  394. {
  395. base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
  396. }
  397. else
  398. {
  399. base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
  400. }
  401. }
  402. /* @} */
  403. /*!
  404. * @name Interrupts
  405. * @{
  406. */
  407. /*!
  408. * @brief Enables the FLEXSPI interrupts.
  409. *
  410. * @param base FLEXSPI peripheral base address.
  411. * @param mask FLEXSPI interrupt source.
  412. */
  413. static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
  414. {
  415. base->INTEN |= mask;
  416. }
  417. /*!
  418. * @brief Disable the FLEXSPI interrupts.
  419. *
  420. * @param base FLEXSPI peripheral base address.
  421. * @param mask FLEXSPI interrupt source.
  422. */
  423. static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
  424. {
  425. base->INTEN &= ~mask;
  426. }
  427. /* @} */
  428. /*! @name DMA control */
  429. /*@{*/
  430. /*!
  431. * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests.
  432. *
  433. * @param base FLEXSPI peripheral base address.
  434. * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable.
  435. */
  436. static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
  437. {
  438. if (enable)
  439. {
  440. base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK;
  441. }
  442. else
  443. {
  444. base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK;
  445. }
  446. }
  447. /*!
  448. * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests.
  449. *
  450. * @param base FLEXSPI peripheral base address.
  451. * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable.
  452. */
  453. static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
  454. {
  455. if (enable)
  456. {
  457. base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK;
  458. }
  459. else
  460. {
  461. base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK;
  462. }
  463. }
  464. /*!
  465. * @brief Gets FLEXSPI IP tx fifo address for DMA transfer.
  466. *
  467. * @param base FLEXSPI peripheral base address.
  468. * @retval The tx fifo address.
  469. */
  470. static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
  471. {
  472. return (uint32_t)&base->TFDR[0];
  473. }
  474. /*!
  475. * @brief Gets FLEXSPI IP rx fifo address for DMA transfer.
  476. *
  477. * @param base FLEXSPI peripheral base address.
  478. * @retval The rx fifo address.
  479. */
  480. static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
  481. {
  482. return (uint32_t)&base->RFDR[0];
  483. }
  484. /*@}*/
  485. /*! @name FIFO control */
  486. /*@{*/
  487. /*! @brief Clears the FLEXSPI IP FIFO logic.
  488. *
  489. * @param base FLEXSPI peripheral base address.
  490. * @param txFifo Pass true to reset TX FIFO.
  491. * @param rxFifo Pass true to reset RX FIFO.
  492. */
  493. static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
  494. {
  495. if (txFifo)
  496. {
  497. base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
  498. }
  499. if (rxFifo)
  500. {
  501. base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
  502. }
  503. }
  504. /*!
  505. * @brief Gets the valid data entries in the FLEXSPI FIFOs.
  506. *
  507. * @param base FLEXSPI peripheral base address.
  508. * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned.
  509. * Pass NULL if this value is not required.
  510. * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
  511. * Pass NULL if this value is not required.
  512. */
  513. static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
  514. {
  515. if (NULL != txCount)
  516. {
  517. *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U;
  518. }
  519. if (NULL != rxCount)
  520. {
  521. *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U;
  522. }
  523. }
  524. /*@}*/
  525. /*!
  526. * @name Status
  527. * @{
  528. */
  529. /*!
  530. * @brief Get the FLEXSPI interrupt status flags.
  531. *
  532. * @param base FLEXSPI peripheral base address.
  533. * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status.
  534. */
  535. static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
  536. {
  537. return base->INTR;
  538. }
  539. /*!
  540. * @brief Get the FLEXSPI interrupt status flags.
  541. *
  542. * @param base FLEXSPI peripheral base address.
  543. * @param mask FLEXSPI interrupt source.
  544. */
  545. static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
  546. {
  547. base->INTR |= mask;
  548. }
  549. #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
  550. /*! @brief Gets the sampling clock phase selection after Data Learning.
  551. *
  552. * @param base FLEXSPI peripheral base address.
  553. * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA.
  554. * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB.
  555. */
  556. static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase)
  557. {
  558. if (portAPhase != NULL)
  559. {
  560. *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT);
  561. }
  562. if (portBPhase != NULL)
  563. {
  564. *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT);
  565. }
  566. }
  567. #endif
  568. /*! @brief Gets the trigger source of current command sequence granted by arbitrator.
  569. *
  570. * @param base FLEXSPI peripheral base address.
  571. * @retval trigger source of current command sequence.
  572. */
  573. static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
  574. {
  575. return (flexspi_arb_command_source_t)(
  576. (uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT));
  577. }
  578. /*! @brief Gets the error code when IP command error detected.
  579. *
  580. * @param base FLEXSPI peripheral base address.
  581. * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
  582. * @retval error code when IP command error detected.
  583. */
  584. static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
  585. {
  586. *index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT);
  587. return (flexspi_ip_error_code_t)(
  588. (uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT));
  589. }
  590. /*! @brief Gets the error code when AHB command error detected.
  591. *
  592. * @param base FLEXSPI peripheral base address.
  593. * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
  594. * @retval error code when AHB command error detected.
  595. */
  596. static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
  597. {
  598. *index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
  599. return (flexspi_ahb_error_code_t)(
  600. (uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT));
  601. }
  602. /*! @brief Returns whether the bus is idle.
  603. *
  604. * @param base FLEXSPI peripheral base address.
  605. * @retval true Bus is idle.
  606. * @retval false Bus is busy.
  607. */
  608. static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
  609. {
  610. return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
  611. }
  612. /*@}*/
  613. /*!
  614. * @name Bus Operations
  615. * @{
  616. */
  617. /*! @brief Update read sample clock source
  618. *
  619. * @param base FLEXSPI peripheral base address.
  620. * @param clockSource clockSource of type #flexspi_read_sample_clock_t
  621. */
  622. void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource);
  623. /*! @brief Enables/disables the FLEXSPI IP command parallel mode.
  624. *
  625. * @param base FLEXSPI peripheral base address.
  626. * @param enable True means enable parallel mode, false means disable parallel mode.
  627. */
  628. static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
  629. {
  630. if (enable)
  631. {
  632. base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK;
  633. }
  634. else
  635. {
  636. base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK;
  637. }
  638. }
  639. /*! @brief Enables/disables the FLEXSPI AHB command parallel mode.
  640. *
  641. * @param base FLEXSPI peripheral base address.
  642. * @param enable True means enable parallel mode, false means disable parallel mode.
  643. */
  644. static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
  645. {
  646. if (enable)
  647. {
  648. base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK;
  649. }
  650. else
  651. {
  652. base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK;
  653. }
  654. }
  655. /*! @brief Updates the LUT table.
  656. *
  657. * @param base FLEXSPI peripheral base address.
  658. * @param index From which index start to update. It could be any index of the LUT table, which
  659. * also allows user to update command content inside a command. Each command consists of up to
  660. * 8 instructions and occupy 4*32-bit memory.
  661. * @param cmd Command sequence array.
  662. * @param count Number of sequences.
  663. */
  664. void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
  665. /*!
  666. * @brief Writes data into FIFO.
  667. *
  668. * @param base FLEXSPI peripheral base address
  669. * @param data The data bytes to send
  670. * @param fifoIndex Destination fifo index.
  671. */
  672. static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
  673. {
  674. base->TFDR[fifoIndex] = data;
  675. }
  676. /*!
  677. * @brief Receives data from data FIFO.
  678. *
  679. * @param base FLEXSPI peripheral base address
  680. * @param fifoIndex Source fifo index.
  681. * @return The data in the FIFO.
  682. */
  683. static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
  684. {
  685. return base->RFDR[fifoIndex];
  686. }
  687. /*!
  688. * @brief Sends a buffer of data bytes using blocking method.
  689. * @note This function blocks via polling until all bytes have been sent.
  690. * @param base FLEXSPI peripheral base address
  691. * @param buffer The data bytes to send
  692. * @param size The number of data bytes to send
  693. * @retval kStatus_Success write success without error
  694. * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
  695. * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
  696. * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
  697. */
  698. status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
  699. /*!
  700. * @brief Receives a buffer of data bytes using a blocking method.
  701. * @note This function blocks via polling until all bytes have been sent.
  702. * @param base FLEXSPI peripheral base address
  703. * @param buffer The data bytes to send
  704. * @param size The number of data bytes to receive
  705. * @retval kStatus_Success read success without error
  706. * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
  707. * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
  708. * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
  709. */
  710. status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
  711. /*!
  712. * @brief Execute command to transfer a buffer data bytes using a blocking method.
  713. * @param base FLEXSPI peripheral base address
  714. * @param xfer pointer to the transfer structure.
  715. * @retval kStatus_Success command transfer success without error
  716. * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
  717. * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
  718. * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
  719. */
  720. status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer);
  721. /*! @} */
  722. /*!
  723. * @name Transactional
  724. * @{
  725. */
  726. /*!
  727. * @brief Initializes the FLEXSPI handle which is used in transactional functions.
  728. *
  729. * @param base FLEXSPI peripheral base address.
  730. * @param handle pointer to flexspi_handle_t structure to store the transfer state.
  731. * @param callback pointer to user callback function.
  732. * @param userData user parameter passed to the callback function.
  733. */
  734. void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
  735. flexspi_handle_t *handle,
  736. flexspi_transfer_callback_t callback,
  737. void *userData);
  738. /*!
  739. * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus.
  740. *
  741. * @note Calling the API returns immediately after transfer initiates. The user needs
  742. * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
  743. * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
  744. * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or
  745. * FLEXSPI could not read data properly.
  746. *
  747. * @param base FLEXSPI peripheral base address.
  748. * @param handle pointer to flexspi_handle_t structure which stores the transfer state.
  749. * @param xfer pointer to flexspi_transfer_t structure.
  750. * @retval kStatus_Success Successfully start the data transmission.
  751. * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished.
  752. */
  753. status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer);
  754. /*!
  755. * @brief Gets the master transfer status during a interrupt non-blocking transfer.
  756. *
  757. * @param base FLEXSPI peripheral base address.
  758. * @param handle pointer to flexspi_handle_t structure which stores the transfer state.
  759. * @param count Number of bytes transferred so far by the non-blocking transaction.
  760. * @retval kStatus_InvalidArgument count is Invalid.
  761. * @retval kStatus_Success Successfully return the count.
  762. */
  763. status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count);
  764. /*!
  765. * @brief Aborts an interrupt non-blocking transfer early.
  766. *
  767. * @note This API can be called at any time when an interrupt non-blocking transfer initiates
  768. * to abort the transfer early.
  769. *
  770. * @param base FLEXSPI peripheral base address.
  771. * @param handle pointer to flexspi_handle_t structure which stores the transfer state
  772. */
  773. void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle);
  774. /*!
  775. * @brief Master interrupt handler.
  776. *
  777. * @param base FLEXSPI peripheral base address.
  778. * @param handle pointer to flexspi_handle_t structure.
  779. */
  780. void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle);
  781. /*! @} */
  782. #if defined(__cplusplus)
  783. }
  784. #endif /*_cplusplus. */
  785. /*@}*/
  786. #endif /* __FSL_FLEXSPI_H_ */