fsl_gpio.c 5.1 KB

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  1. /*
  2. * Copyright (c) 2016, Freescale Semiconductor, Inc.
  3. * Copyright 2016-2017, 2020 NXP
  4. * All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. */
  8. #include "fsl_gpio.h"
  9. /* Component ID definition, used by tools. */
  10. #ifndef FSL_COMPONENT_ID
  11. #define FSL_COMPONENT_ID "platform.drivers.igpio"
  12. #endif
  13. /*******************************************************************************
  14. * Variables
  15. ******************************************************************************/
  16. /* Array of GPIO peripheral base address. */
  17. static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
  18. #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
  19. /* Array of GPIO clock name. */
  20. static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS;
  21. #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
  22. /*******************************************************************************
  23. * Prototypes
  24. ******************************************************************************/
  25. /*!
  26. * @brief Gets the GPIO instance according to the GPIO base
  27. *
  28. * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
  29. * @retval GPIO instance
  30. */
  31. static uint32_t GPIO_GetInstance(GPIO_Type *base);
  32. /*******************************************************************************
  33. * Code
  34. ******************************************************************************/
  35. static uint32_t GPIO_GetInstance(GPIO_Type *base)
  36. {
  37. uint32_t instance;
  38. /* Find the instance index from base address mappings. */
  39. for (instance = 0U; instance < ARRAY_SIZE(s_gpioBases); instance++)
  40. {
  41. if (s_gpioBases[instance] == base)
  42. {
  43. break;
  44. }
  45. }
  46. assert(instance < ARRAY_SIZE(s_gpioBases));
  47. return instance;
  48. }
  49. /*!
  50. * brief Initializes the GPIO peripheral according to the specified
  51. * parameters in the initConfig.
  52. *
  53. * param base GPIO base pointer.
  54. * param pin Specifies the pin number
  55. * param initConfig pointer to a ref gpio_pin_config_t structure that
  56. * contains the configuration information.
  57. */
  58. void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)
  59. {
  60. #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
  61. /* Enable GPIO clock. */
  62. uint32_t instance = GPIO_GetInstance(base);
  63. /* If The clock IP is valid, enable the clock gate. */
  64. if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance]))
  65. {
  66. (void)CLOCK_EnableClock(s_gpioClock[instance]);
  67. }
  68. #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
  69. /* Register reset to default value */
  70. base->IMR &= ~(1UL << pin);
  71. /* Configure GPIO pin direction */
  72. if (Config->direction == kGPIO_DigitalInput)
  73. {
  74. base->GDIR &= ~(1UL << pin);
  75. }
  76. else
  77. {
  78. GPIO_PinWrite(base, pin, Config->outputLogic);
  79. base->GDIR |= (1UL << pin);
  80. }
  81. /* Configure GPIO pin interrupt mode */
  82. GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode);
  83. }
  84. /*!
  85. * brief Sets the output level of the individual GPIO pin to logic 1 or 0.
  86. *
  87. * param base GPIO base pointer.
  88. * param pin GPIO port pin number.
  89. * param output GPIOpin output logic level.
  90. * - 0: corresponding pin output low-logic level.
  91. * - 1: corresponding pin output high-logic level.
  92. */
  93. void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
  94. {
  95. assert(pin < 32U);
  96. if (output == 0U)
  97. {
  98. #if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR)
  99. base->DR_CLEAR = (1UL << pin);
  100. #else
  101. base->DR &= ~(1UL << pin); /* Set pin output to low level.*/
  102. #endif
  103. }
  104. else
  105. {
  106. #if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET)
  107. base->DR_SET = (1UL << pin);
  108. #else
  109. base->DR |= (1UL << pin); /* Set pin output to high level.*/
  110. #endif
  111. }
  112. }
  113. /*!
  114. * brief Sets the current pin interrupt mode.
  115. *
  116. * param base GPIO base pointer.
  117. * param pin GPIO port pin number.
  118. * param pininterruptMode pointer to a ref gpio_interrupt_mode_t structure
  119. * that contains the interrupt mode information.
  120. */
  121. void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
  122. {
  123. volatile uint32_t *icr;
  124. uint32_t icrShift;
  125. icrShift = pin;
  126. /* Register reset to default value */
  127. base->EDGE_SEL &= ~(1UL << pin);
  128. if (pin < 16U)
  129. {
  130. icr = &(base->ICR1);
  131. }
  132. else
  133. {
  134. icr = &(base->ICR2);
  135. icrShift -= 16U;
  136. }
  137. switch (pinInterruptMode)
  138. {
  139. case (kGPIO_IntLowLevel):
  140. *icr &= ~(3UL << (2UL * icrShift));
  141. break;
  142. case (kGPIO_IntHighLevel):
  143. *icr = (*icr & (~(3UL << (2UL * icrShift)))) | (1UL << (2UL * icrShift));
  144. break;
  145. case (kGPIO_IntRisingEdge):
  146. *icr = (*icr & (~(3UL << (2UL * icrShift)))) | (2UL << (2UL * icrShift));
  147. break;
  148. case (kGPIO_IntFallingEdge):
  149. *icr |= (3UL << (2UL * icrShift));
  150. break;
  151. case (kGPIO_IntRisingOrFallingEdge):
  152. base->EDGE_SEL |= (1UL << pin);
  153. break;
  154. default:; /* Intentional empty default */
  155. break;
  156. }
  157. }