fsl_src.h 23 KB

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  1. /*
  2. * Copyright (c) 2016, Freescale Semiconductor, Inc.
  3. * Copyright 2016-2020 NXP
  4. * All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. */
  8. #ifndef _FSL_SRC_H_
  9. #define _FSL_SRC_H_
  10. #include "fsl_common.h"
  11. /*!
  12. * @addtogroup src
  13. * @{
  14. */
  15. /*******************************************************************************
  16. * Definitions
  17. ******************************************************************************/
  18. /*! @name Driver version */
  19. /*@{*/
  20. /*! @brief SRC driver version 2.0.1. */
  21. #define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
  22. /*@}*/
  23. /*!
  24. * @brief SRC reset status flags.
  25. */
  26. enum _src_reset_status_flags
  27. {
  28. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT) && FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT)
  29. kSRC_ResetOutputEnableFlag = SRC_SRSR_RESET_OUT_MASK, /*!< This bit indicates if RESET status is
  30. driven out on PTE0 pin. */
  31. #endif /* FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT */
  32. #if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI)
  33. kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK, /*!< WARM boot indication shows that WARM boot
  34. was initiated by software. */
  35. #endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */
  36. kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK, /*!< Indicates whether the reset was the
  37. result of software reset from on-chip
  38. Temperature Sensor. Temperature Sensor
  39. Interrupt needs to be served before this
  40. bit can be cleaned.*/
  41. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B)
  42. kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK, /*!< IC Watchdog3 Time-out reset. Indicates
  43. whether the reset was the result of the
  44. watchdog3 time-out event. */
  45. #endif /* FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B */
  46. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW)
  47. kSRC_SoftwareResetFlag = SRC_SRSR_SW_MASK, /*!< Indicates a reset has been caused by software
  48. setting of SYSRESETREQ bit in Application
  49. Interrupt and Reset Control Register in the
  50. ARM core. */
  51. #endif /* FSL_FEATURE_SRC_HAS_SRSR_SW */
  52. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST) && FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST)
  53. kSRC_JTAGSystemResetFlag =
  54. SRC_SRSR_JTAG_SW_RST_MASK, /*!< Indicates whether the reset was the result of software reset form JTAG */
  55. #endif /* FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST */
  56. kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK, /*!< Indicates whether the reset was the result of
  57. setting SJC_GPCCR bit 31. */
  58. kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK, /*!< Indicates a reset has been caused by JTAG
  59. selection of certain IR codes: EXTEST or
  60. HIGHZ. */
  61. kSRC_WatchdogResetFlag = SRC_SRSR_WDOG_MASK, /*!< Indicates a reset has been caused by the
  62. watchdog timer timing out. This reset source
  63. can be blocked by disabling the watchdog. */
  64. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B)
  65. kSRC_IppUserResetFlag = SRC_SRSR_IPP_USER_RESET_B_MASK, /*!< Indicates whether the reset was the
  66. result of the ipp_user_reset_b
  67. qualified reset. */
  68. #endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B */
  69. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS)
  70. kSRC_SNVSFailResetFlag = SRC_SRSR_SNVS_MASK, /*!< SNVS hardware failure will always cause a cold
  71. reset. This flag indicates whether the reset
  72. is a result of SNVS hardware failure. */
  73. #endif /* FSL_FEATURE_SRC_HAS_SRSR_SNVS */
  74. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B)
  75. kSRC_CsuResetFlag = SRC_SRSR_CSU_RESET_B_MASK, /*!< Indicates whether the reset was the result
  76. of the csu_reset_b input. */
  77. #endif /* FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B */
  78. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP)
  79. kSRC_CoreLockupResetFlag = SRC_SRSR_LOCKUP_MASK, /*!< Indicates a reset has been caused by the
  80. ARM core indication of a LOCKUP event. */
  81. #endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP */
  82. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR)
  83. kSRC_PowerOnResetFlag = SRC_SRSR_POR_MASK, /*!< Indicates a reset has been caused by the
  84. power-on detection logic. */
  85. #endif /* FSL_FEATURE_SRC_HAS_SRSR_POR */
  86. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ)
  87. kSRC_LockupSysResetFlag =
  88. SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software
  89. setting of SYSRESETREQ bit in Application Interrupt and
  90. Reset Control Register of the ARM core. */
  91. #endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */
  92. #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B)
  93. kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK, /*!< Indicates whether reset was the result of
  94. ipp_reset_b pin (Power-up sequence). */
  95. #endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B */
  96. };
  97. #if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR)
  98. /*!
  99. * @brief SRC interrupt status flag.
  100. */
  101. enum _src_status_flags
  102. {
  103. kSRC_Core0WdogResetReqFlag =
  104. SRC_SISR_CORE0_WDOG_RST_REQ_MASK, /*!< WDOG reset request from core0. Read-only status bit. */
  105. };
  106. #endif /* FSL_FEATURE_SRC_HAS_SISR */
  107. #if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH)
  108. /*!
  109. * @brief Selection of SoC mix power reset stretch.
  110. *
  111. * This type defines the SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset
  112. * stretch mix reset width with the optional count of cycles
  113. */
  114. typedef enum _src_mix_reset_stretch_cycles
  115. {
  116. kSRC_MixResetStretchCycleAlt0 = 0U, /*!< mix reset width is 1 x 88 ipg_cycle cycles. */
  117. kSRC_MixResetStretchCycleAlt1 = 1U, /*!< mix reset width is 2 x 88 ipg_cycle cycles. */
  118. kSRC_MixResetStretchCycleAlt2 = 2U, /*!< mix reset width is 3 x 88 ipg_cycle cycles. */
  119. kSRC_MixResetStretchCycleAlt3 = 3U, /*!< mix reset width is 4 x 88 ipg_cycle cycles. */
  120. } src_mix_reset_stretch_cycles_t;
  121. #endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */
  122. #if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN)
  123. /*!
  124. * @brief Selection of WDOG3 reset option.
  125. */
  126. typedef enum _src_wdog3_reset_option
  127. {
  128. kSRC_Wdog3ResetOptionAlt0 = 0U, /*!< Wdog3_rst_b asserts M4 reset (default). */
  129. kSRC_Wdog3ResetOptionAlt1 = 1U, /*!< Wdog3_rst_b asserts global reset. */
  130. } src_wdog3_reset_option_t;
  131. #endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */
  132. /*!
  133. * @brief Selection of WARM reset bypass count.
  134. *
  135. * This type defines the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM
  136. * reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will
  137. * be initiated.
  138. */
  139. typedef enum _src_warm_reset_bypass_count
  140. {
  141. kSRC_WarmResetWaitAlways = 0U, /*!< System will wait until MMDC acknowledge is asserted. */
  142. kSRC_WarmResetWaitClk16 = 1U, /*!< Wait 16 32KHz clock cycles before switching the reset. */
  143. kSRC_WarmResetWaitClk32 = 2U, /*!< Wait 32 32KHz clock cycles before switching the reset. */
  144. kSRC_WarmResetWaitClk64 = 3U, /*!< Wait 64 32KHz clock cycles before switching the reset. */
  145. } src_warm_reset_bypass_count_t;
  146. #if defined(__cplusplus)
  147. extern "C" {
  148. #endif
  149. /*******************************************************************************
  150. * API
  151. ******************************************************************************/
  152. #if (defined(FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST) && FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST)
  153. /*!
  154. * @brief Enable the WDOG3 reset.
  155. *
  156. * The WDOG3 reset is enabled by default.
  157. *
  158. * @param base SRC peripheral base address.
  159. * @param enable Enable the reset or not.
  160. */
  161. static inline void SRC_EnableWDOG3Reset(SRC_Type *base, bool enable)
  162. {
  163. if (enable)
  164. {
  165. base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0xA);
  166. }
  167. else
  168. {
  169. base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0x5);
  170. }
  171. }
  172. #endif /* FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST */
  173. #if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH)
  174. /*!
  175. * @brief Set the mix power up reset stretch mix reset width.
  176. *
  177. * @param base SRC peripheral base address.
  178. * @param option Setting option, see to #src_mix_reset_stretch_cycles_t.
  179. */
  180. static inline void SRC_SetMixResetStretchCycles(SRC_Type *base, src_mix_reset_stretch_cycles_t option)
  181. {
  182. base->SCR = (base->SCR & ~SRC_SCR_MIX_RST_STRCH_MASK) | SRC_SCR_MIX_RST_STRCH(option);
  183. }
  184. #endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */
  185. #if (defined(FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG) && FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG)
  186. /*!
  187. * @brief Debug reset would be asserted after power gating event.
  188. *
  189. * @param base SRC peripheral base address.
  190. * @param enable Enable the reset or not.
  191. */
  192. static inline void SRC_EnableCoreDebugResetAfterPowerGate(SRC_Type *base, bool enable)
  193. {
  194. if (enable)
  195. {
  196. base->SCR &= ~SRC_SCR_DBG_RST_MSK_PG_MASK;
  197. }
  198. else
  199. {
  200. base->SCR |= SRC_SCR_DBG_RST_MSK_PG_MASK;
  201. }
  202. }
  203. #endif /* FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG */
  204. #if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN)
  205. /*!
  206. * @brief Set the Wdog3_rst_b option.
  207. *
  208. * @param base SRC peripheral base address.
  209. * @param option Setting option, see to #src_wdog3_reset_option_t.
  210. */
  211. static inline void SRC_SetWdog3ResetOption(SRC_Type *base, src_wdog3_reset_option_t option)
  212. {
  213. base->SCR = (base->SCR & ~SRC_SCR_WDOG3_RST_OPTN_MASK) | SRC_SCR_WDOG3_RST_OPTN(option);
  214. }
  215. #endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */
  216. #if (defined(FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST) && FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST)
  217. /*!
  218. * @brief Software reset for debug of arm platform only.
  219. *
  220. * @param base SRC peripheral base address.
  221. */
  222. static inline void SRC_DoSoftwareResetARMCoreDebug(SRC_Type *base)
  223. {
  224. base->SCR |= SRC_SCR_CORES_DBG_RST_MASK;
  225. }
  226. /*!
  227. * @brief Check if the software reset for debug of arm platform only is done.
  228. *
  229. * @param base SRC peripheral base address.
  230. */
  231. static inline bool SRC_GetSoftwareResetARMCoreDebugDone(SRC_Type *base)
  232. {
  233. return (0U == (base->SCR & SRC_SCR_CORES_DBG_RST_MASK));
  234. }
  235. #endif /* FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST */
  236. #if (defined(FSL_FEATURE_SRC_HAS_SCR_MTSR) && FSL_FEATURE_SRC_HAS_SCR_MTSR)
  237. /*!
  238. * @brief Enable the temperature sensor reset.
  239. *
  240. * The temperature sersor reset is enabled by default. When the sensor reset happens, an flag bit
  241. * would be asserted. This flag bit can be cleared only by the hardware reset.
  242. *
  243. * @param base SRC peripheral base address.
  244. * @param enable Enable the reset or not.
  245. */
  246. static inline void SRC_EnableTemperatureSensorReset(SRC_Type *base, bool enable)
  247. {
  248. if (enable) /* Temperature sensor reset is not masked. (default) */
  249. {
  250. base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x2);
  251. }
  252. else /* The on-chip temperature sensor interrupt will not create a reset to the chip. */
  253. {
  254. base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x5);
  255. }
  256. }
  257. #endif /* FSL_FEATURE_SRC_HAS_SCR_MTSR */
  258. #if (defined(FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST) && FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST)
  259. /*!
  260. * @brief Do assert the core0 debug reset.
  261. *
  262. * @param base SRC peripheral base address.
  263. */
  264. static inline void SRC_DoAssertCore0DebugReset(SRC_Type *base)
  265. {
  266. base->SCR |= SRC_SCR_CORE0_DBG_RST_MASK;
  267. }
  268. /*!
  269. * @brief Check if the core0 debug reset is done.
  270. *
  271. * @param base SRC peripheral base address.
  272. */
  273. static inline bool SRC_GetAssertCore0DebugResetDone(SRC_Type *base)
  274. {
  275. return (0U == (base->SCR & SRC_SCR_CORE0_DBG_RST_MASK));
  276. }
  277. #endif /* FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST */
  278. #if (defined(FSL_FEATURE_SRC_HAS_SCR_CORE0_RST) && FSL_FEATURE_SRC_HAS_SCR_CORE0_RST)
  279. /*!
  280. * @brief Do software reset the ARM core0 only.
  281. *
  282. * @param base SRC peripheral base address.
  283. */
  284. static inline void SRC_DoSoftwareResetARMCore0(SRC_Type *base)
  285. {
  286. base->SCR |= SRC_SCR_CORE0_RST_MASK;
  287. }
  288. /*!
  289. * @brief Check if the software for ARM core0 is done.
  290. *
  291. * @param base SRC peripheral base address.
  292. * @return If the reset is done.
  293. */
  294. static inline bool SRC_GetSoftwareResetARMCore0Done(SRC_Type *base)
  295. {
  296. return (0U == (base->SCR & SRC_SCR_CORE0_RST_MASK));
  297. }
  298. #endif /* FSL_FEATURE_SRC_HAS_SCR_CORE0_RST */
  299. #if (defined(FSL_FEATURE_SRC_HAS_SCR_SWRC) && FSL_FEATURE_SRC_HAS_SCR_SWRC)
  300. /*!
  301. * @brief Do software reset for ARM core.
  302. *
  303. * This function can be used to assert the ARM core reset. Once it is called, the reset process will
  304. * begin. After the reset process is finished, the command bit would be self cleared.
  305. *
  306. * @param base SRC peripheral base address.
  307. */
  308. static inline void SRC_DoSoftwareResetARMCore(SRC_Type *base)
  309. {
  310. base->SCR |= SRC_SCR_SWRC_MASK;
  311. }
  312. /*!
  313. * @brief Check if the software for ARM core is done.
  314. *
  315. * @param base SRC peripheral base address.
  316. * @return If the reset is done.
  317. */
  318. static inline bool SRC_GetSoftwareResetARMCoreDone(SRC_Type *base)
  319. {
  320. return (0U == (base->SCR & SRC_SCR_SWRC_MASK));
  321. }
  322. #endif /* FSL_FEATURE_SRC_HAS_SCR_SWRC */
  323. #if (defined(FSL_FEATURE_SRC_HAS_SCR_EIM_RST) && FSL_FEATURE_SRC_HAS_SCR_EIM_RST)
  324. /*!
  325. * @brief Assert the EIM reset.
  326. *
  327. * EIM reset is needed in order to reconfigure the EIM chip select.
  328. * The software reset bit must de-asserted since this is not self-refresh.
  329. *
  330. * @param base SRC peripheral base address.
  331. * @param enable Make the assertion or not.
  332. */
  333. static inline void SRC_AssertEIMReset(SRC_Type *base, bool enable)
  334. {
  335. if (enable)
  336. {
  337. base->SCR |= SRC_SCR_EIM_RST_MASK;
  338. }
  339. else
  340. {
  341. base->SCR &= ~SRC_SCR_EIM_RST_MASK;
  342. }
  343. }
  344. #endif /* FSL_FEATURE_SRC_HAS_SCR_EIM_RST */
  345. /*!
  346. * @brief Enable the WDOG Reset in SRC.
  347. *
  348. * WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create
  349. * a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is
  350. * asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear
  351. * that bit is the hardware reset.
  352. *
  353. * @param base SRC peripheral base address.
  354. * @param enable Enable the reset or not.
  355. */
  356. static inline void SRC_EnableWDOGReset(SRC_Type *base, bool enable)
  357. {
  358. if (enable) /* WDOG Reset is not masked in SRC (default). */
  359. {
  360. base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0xA);
  361. }
  362. else /* WDOG Reset is masked in SRC. */
  363. {
  364. base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0x5);
  365. }
  366. }
  367. #if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRBC) && FSL_FEATURE_SRC_HAS_NO_SCR_WRBC)
  368. /*!
  369. * @brief Set the delay count of waiting MMDC's acknowledge.
  370. *
  371. * This function would define the 32KHz clock cycles to count before bypassing the MMDC acknowledge
  372. * for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD
  373. * reset will be initiated.
  374. *
  375. * @param base SRC peripheral base address.
  376. * @param option The option of setting mode, see to #src_warm_reset_bypass_count_t.
  377. */
  378. static inline void SRC_SetWarmResetBypassCount(SRC_Type *base, src_warm_reset_bypass_count_t option)
  379. {
  380. base->SCR = (base->SCR & ~SRC_SCR_WRBC_MASK) | SRC_SCR_WRBC(option);
  381. }
  382. #endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRBC */
  383. #if (defined(FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) && FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST)
  384. /*!
  385. * @brief Enable the lockup reset.
  386. *
  387. * @param base SRC peripheral base address.
  388. * @param enable Enable the reset or not.
  389. */
  390. static inline void SRC_EnableLockupReset(SRC_Type *base, bool enable)
  391. {
  392. if (enable) /* Enable lockup reset. */
  393. {
  394. base->SCR |= SRC_SCR_LOCKUP_RST_MASK;
  395. }
  396. else /* Disable lockup reset. */
  397. {
  398. base->SCR &= ~SRC_SCR_LOCKUP_RST_MASK;
  399. }
  400. }
  401. #endif /* FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST */
  402. #if (defined(FSL_FEATURE_SRC_HAS_SCR_LUEN) && FSL_FEATURE_SRC_HAS_SCR_LUEN)
  403. /*!
  404. * @brief Enable the core lockup reset.
  405. *
  406. * When enable the core luckup reset, the system would be reset when core luckup event happens.
  407. *
  408. * @param base SRC peripheral base address.
  409. * @param enable Enable the reset or not.
  410. */
  411. static inline void SRC_EnableCoreLockupReset(SRC_Type *base, bool enable)
  412. {
  413. if (enable) /* Core lockup will cause system reset. */
  414. {
  415. base->SCR |= SRC_SCR_LUEN_MASK;
  416. }
  417. else /* Core lockup will not cause system reset. */
  418. {
  419. base->SCR &= ~SRC_SCR_LUEN_MASK;
  420. }
  421. }
  422. #endif /* FSL_FEATURE_SRC_HAS_SCR_LUEN */
  423. #if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRE) && FSL_FEATURE_SRC_HAS_NO_SCR_WRE)
  424. /*!
  425. * @brief Enable the WARM reset.
  426. *
  427. * Only when the WARM reset is enabled, the WARM reset requests would be served by WARM reset.
  428. * Otherwise, all the WARM reset sources would generate COLD reset.
  429. *
  430. * @param base SRC peripheral base address.
  431. * @param enable Enable the WARM reset or not.
  432. */
  433. static inline void SRC_EnableWarmReset(SRC_Type *base, bool enable)
  434. {
  435. if (enable)
  436. {
  437. base->SCR |= SRC_SCR_WRE_MASK;
  438. }
  439. else
  440. {
  441. base->SCR &= ~SRC_SCR_WRE_MASK;
  442. }
  443. }
  444. #endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRE */
  445. #if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR)
  446. /*!
  447. * @brief Get interrupt status flags.
  448. *
  449. * @param base SRC peripheral base address.
  450. * @return Mask value of status flags. See to $_src_status_flags.
  451. */
  452. static inline uint32_t SRC_GetStatusFlags(SRC_Type *base)
  453. {
  454. return base->SISR;
  455. }
  456. #endif /* FSL_FEATURE_SRC_HAS_SISR */
  457. /*!
  458. * @brief Get the boot mode register 1 value.
  459. *
  460. * The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip.
  461. * See to chip-specific document for detail information about value.
  462. *
  463. * @param base SRC peripheral base address.
  464. * @return status of BOOT_CFGx pins of the chip.
  465. */
  466. static inline uint32_t SRC_GetBootModeWord1(SRC_Type *base)
  467. {
  468. return base->SBMR1;
  469. }
  470. /*!
  471. * @brief Get the boot mode register 2 value.
  472. *
  473. * The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values
  474. * that controls boot of the chip. See to chip-specific document for detail information about value.
  475. *
  476. * @param base SRC peripheral base address.
  477. * @return status of BOOT_MODEx Pins and fuse values that controls boot of the chip.
  478. */
  479. static inline uint32_t SRC_GetBootModeWord2(SRC_Type *base)
  480. {
  481. return base->SBMR2;
  482. }
  483. #if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI)
  484. /*!
  485. * @brief Set the warm boot indication flag.
  486. *
  487. * WARM boot indication shows that WARM boot was initiated by software. This indicates to the
  488. * software that it saved the needed information in the memory before initiating the WARM reset.
  489. * In this case, software will set this bit to '1', before initiating the WARM reset. The warm_boot
  490. * bit should be used as indication only after a warm_reset sequence. Software should clear this bit
  491. * after warm_reset to indicate that the next warm_reset is not performed with warm_boot.
  492. *
  493. * @param base SRC peripheral base address.
  494. * @param enable Assert the flag or not.
  495. */
  496. static inline void SRC_SetWarmBootIndication(SRC_Type *base, bool enable)
  497. {
  498. if (enable)
  499. {
  500. base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) | SRC_SRSR_WBI_MASK;
  501. }
  502. else
  503. {
  504. base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) & ~SRC_SRSR_WBI_MASK;
  505. }
  506. }
  507. #endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */
  508. /*!
  509. * @brief Get the status flags of SRC.
  510. *
  511. * @param base SRC peripheral base address.
  512. * @return Mask value of status flags, see to #_src_reset_status_flags.
  513. */
  514. static inline uint32_t SRC_GetResetStatusFlags(SRC_Type *base)
  515. {
  516. return base->SRSR;
  517. }
  518. /*!
  519. * @brief Clear the status flags of SRC.
  520. *
  521. * @param base SRC peripheral base address.
  522. * @param flags value of status flags to be cleared, see to #_src_reset_status_flags.
  523. */
  524. void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags);
  525. /*!
  526. * @brief Set value to general purpose registers.
  527. *
  528. * General purpose registers (GPRx) would hold the value during reset process. Wakeup function could
  529. * be kept in these register. For example, the GPR1 holds the entry function for waking-up from
  530. * Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the
  531. * arbitray values.
  532. *
  533. * @param base SRC peripheral base address.
  534. * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register.
  535. * @param value Setting value for GPRx register.
  536. */
  537. static inline void SRC_SetGeneralPurposeRegister(SRC_Type *base, uint32_t index, uint32_t value)
  538. {
  539. assert(index < SRC_GPR_COUNT);
  540. base->GPR[index] = value;
  541. }
  542. /*!
  543. * @brief Get the value from general purpose registers.
  544. *
  545. * @param base SRC peripheral base address.
  546. * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register.
  547. * @return The setting value for GPRx register.
  548. */
  549. static inline uint32_t SRC_GetGeneralPurposeRegister(SRC_Type *base, uint32_t index)
  550. {
  551. assert(index < SRC_GPR_COUNT);
  552. return base->GPR[index];
  553. }
  554. #if defined(__cplusplus)
  555. }
  556. #endif
  557. /*!
  558. * @}
  559. */
  560. #endif /* _FSL_SRC_H_ */