fsl_adc_etc.h 14 KB

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  1. /*
  2. * Copyright (c) 2016, Freescale Semiconductor, Inc.
  3. * Copyright 2016-2021 NXP
  4. * All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. */
  8. #ifndef _FSL_ADC_ETC_H_
  9. #define _FSL_ADC_ETC_H_
  10. #include "fsl_common.h"
  11. /*!
  12. * @addtogroup adc_etc
  13. * @{
  14. */
  15. /*******************************************************************************
  16. * Definitions
  17. ******************************************************************************/
  18. /*! @brief ADC_ETC driver version */
  19. #define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */
  20. /*! @brief The mask of status flags cleared by writing 1. */
  21. #define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
  22. /*!
  23. * @brief ADC_ETC customized status flags mask.
  24. */
  25. enum _adc_etc_status_flag_mask
  26. {
  27. kADC_ETC_Done0StatusFlagMask = 1U << 0U,
  28. kADC_ETC_Done1StatusFlagMask = 1U << 1U,
  29. kADC_ETC_Done2StatusFlagMask = 1U << 2U,
  30. #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
  31. kADC_ETC_Done3StatusFlagMask = 1U << 3U,
  32. kADC_ETC_ErrorStatusFlagMask = 1U << 4U,
  33. #else
  34. kADC_ETC_ErrorStatusFlagMask = 1U << 3U,
  35. #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
  36. };
  37. /*!
  38. * @brief External triggers sources.
  39. */
  40. typedef enum _adc_etc_external_trigger_source
  41. {
  42. /* External XBAR sources. Support HW or SW mode. */
  43. kADC_ETC_Trg0TriggerSource = 0U, /* External XBAR trigger0 source. */
  44. kADC_ETC_Trg1TriggerSource = 1U, /* External XBAR trigger1 source. */
  45. kADC_ETC_Trg2TriggerSource = 2U, /* External XBAR trigger2 source. */
  46. kADC_ETC_Trg3TriggerSource = 3U, /* External XBAR trigger3 source. */
  47. kADC_ETC_Trg4TriggerSource = 4U, /* External XBAR trigger4 source. */
  48. kADC_ETC_Trg5TriggerSource = 5U, /* External XBAR trigger5 source. */
  49. kADC_ETC_Trg6TriggerSource = 6U, /* External XBAR trigger6 source. */
  50. kADC_ETC_Trg7TriggerSource = 7U, /* External XBAR trigger7 source. */
  51. /* External TSC sources. Only support HW mode. */
  52. kADC_ETC_TSC0TriggerSource = 8U, /* External TSC trigger0 source. */
  53. kADC_ETC_TSC1TriggerSource = 9U, /* External TSC trigger1 source. */
  54. } adc_etc_external_trigger_source_t;
  55. /*!
  56. * @brief Interrupt enable/disable mask.
  57. */
  58. typedef enum _adc_etc_interrupt_enable
  59. {
  60. #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
  61. kADC_ETC_Done0InterruptEnable = 0U, /* Enable the DONE0 interrupt when ADC conversions complete. */
  62. kADC_ETC_Done1InterruptEnable = 1U, /* Enable the DONE1 interrupt when ADC conversions complete. */
  63. kADC_ETC_Done2InterruptEnable = 2U, /* Enable the DONE2 interrupt when ADC conversions complete. */
  64. kADC_ETC_Done3InterruptEnable = 3U, /* Enable the DONE3 interrupt when ADC conversions complete. */
  65. #else
  66. kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */
  67. kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */
  68. kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */
  69. kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
  70. #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
  71. } adc_etc_interrupt_enable_t;
  72. #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
  73. /*!
  74. * @brief DMA mode selection.
  75. */
  76. typedef enum _adc_etc_dma_mode_selection
  77. {
  78. kADC_ETC_TrigDMAWithLatchedSignal =
  79. 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
  80. kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
  81. } adc_etc_dma_mode_selection_t;
  82. #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
  83. /*!
  84. * @brief ADC_ETC configuration.
  85. */
  86. typedef struct _adc_etc_config
  87. {
  88. #if ((!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
  89. (!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)))
  90. bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly.
  91. Otherwise TSC would trigger ADC through ADC_ETC. */
  92. #endif
  93. #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
  94. bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
  95. #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
  96. #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
  97. bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
  98. #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
  99. #if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
  100. adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
  101. #endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
  102. #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
  103. uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
  104. #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
  105. #if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
  106. uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
  107. #endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
  108. uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255.
  109. Clock would be divided by (clockPreDivider+1). */
  110. uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
  111. trigger7:0x80
  112. For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
  113. enabled. */
  114. } adc_etc_config_t;
  115. /*!
  116. * @brief ADC_ETC trigger chain configuration.
  117. */
  118. typedef struct _adc_etc_trigger_chain_config
  119. {
  120. bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode,
  121. wait until interval delay is reached. */
  122. uint32_t ADCHCRegisterSelect; /* Select relevant ADC_HCx register to trigger. 1U : HC0, 2U: HC1, 4U: HC2 ... */
  123. uint32_t ADCChannelSelect; /* Select ADC sample channel. */
  124. adc_etc_interrupt_enable_t InterruptEnable; /* Enable/disable Interrupt. */
  125. #if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
  126. bool enableIrq; /* Enable IRQ for selected interrupt enable choice in "InterruptEnable" */
  127. #endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
  128. } adc_etc_trigger_chain_config_t;
  129. /*!
  130. * @brief ADC_ETC trigger configuration.
  131. */
  132. typedef struct _adc_etc_trigger_config
  133. {
  134. bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source.
  135. In AsyncMode ADC1 and ADC2 are controlled by separate trigger source. */
  136. bool enableSWTriggerMode; /* Enable the sofware trigger mode. */
  137. uint32_t triggerChainLength; /* TRIG chain length to the ADC. 0: Trig length is 1. ... 7: Trig length is 8. */
  138. uint32_t triggerPriority; /* External trigger priority, 7 is highest, 0 is lowest. */
  139. uint32_t sampleIntervalDelay; /* Set sampling interval delay. */
  140. uint32_t initialDelay; /* Set trigger initial delay. */
  141. } adc_etc_trigger_config_t;
  142. /*******************************************************************************
  143. * API
  144. ******************************************************************************/
  145. #if defined(__cplusplus)
  146. extern "C" {
  147. #endif
  148. /*!
  149. * @name Initialization
  150. * @{
  151. */
  152. /*!
  153. * @brief Initialize the ADC_ETC module.
  154. *
  155. * @param base ADC_ETC peripheral base address.
  156. * @param config Pointer to "adc_etc_config_t" structure.
  157. */
  158. void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config);
  159. /*!
  160. * @brief De-Initialize the ADC_ETC module.
  161. *
  162. * @param base ADC_ETC peripheral base address.
  163. */
  164. void ADC_ETC_Deinit(ADC_ETC_Type *base);
  165. /*!
  166. * @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
  167. * This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
  168. * @code
  169. * config->enableTSCBypass = true;
  170. * config->enableTSC0Trigger = false;
  171. * config->enableTSC1Trigger = false;
  172. * config->TSC0triggerPriority = 0U;
  173. * config->TSC1triggerPriority = 0U;
  174. * config->clockPreDivider = 0U;
  175. * config->XBARtriggerMask = 0U;
  176. * @endcode
  177. *
  178. * @param config Pointer to "adc_etc_config_t" structure.
  179. */
  180. void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config);
  181. /*!
  182. * @brief Set the external XBAR trigger configuration.
  183. *
  184. * @param base ADC_ETC peripheral base address.
  185. * @param triggerGroup Trigger group index.
  186. * @param config Pointer to "adc_etc_trigger_config_t" structure.
  187. */
  188. void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config);
  189. /*!
  190. * @brief Set the external XBAR trigger chain configuration.
  191. * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
  192. * configurated.
  193. *
  194. * @param base ADC_ETC peripheral base address.
  195. * @param triggerGroup Trigger group index. Available number is 0~7.
  196. * @param chainGroup Trigger chain group index. Available number is 0~7.
  197. * @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
  198. */
  199. void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
  200. uint32_t triggerGroup,
  201. uint32_t chainGroup,
  202. const adc_etc_trigger_chain_config_t *config);
  203. /*!
  204. * @brief Gets the interrupt status flags of external XBAR and TSC triggers.
  205. *
  206. * @param base ADC_ETC peripheral base address.
  207. * @param sourceIndex trigger source index.
  208. *
  209. * @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
  210. */
  211. uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex);
  212. /*!
  213. * @brief Clears the ADC_ETC's interrupt status falgs.
  214. *
  215. * @param base ADC_ETC peripheral base address.
  216. * @param sourceIndex trigger source index.
  217. * @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
  218. */
  219. void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base,
  220. adc_etc_external_trigger_source_t sourceIndex,
  221. uint32_t mask);
  222. /*!
  223. * @brief Enable the DMA corresponding to each trigger source.
  224. *
  225. * @param base ADC_ETC peripheral base address.
  226. * @param triggerGroup Trigger group index. Available number is 0~7.
  227. */
  228. static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
  229. {
  230. /* Avoid clearing status flags at the same time. */
  231. base->DMA_CTRL = (base->DMA_CTRL | ((uint32_t)ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << (uint32_t)triggerGroup)) &
  232. ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
  233. }
  234. /*!
  235. * @brief Disable the DMA corresponding to each trigger sources.
  236. *
  237. * @param base ADC_ETC peripheral base address.
  238. * @param triggerGroup Trigger group index. Available number is 0~7.
  239. */
  240. static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
  241. {
  242. /* Avoid clearing status flags at the same time. */
  243. base->DMA_CTRL = (base->DMA_CTRL & ~((uint32_t)ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << (uint32_t)triggerGroup)) &
  244. ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
  245. }
  246. /*!
  247. * @brief Get the DMA request status falgs. Only external XBAR sources support DMA request.
  248. *
  249. * @param base ADC_ETC peripheral base address.
  250. * @return Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
  251. * trigger7:0x80.
  252. */
  253. static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base)
  254. {
  255. return (((base->DMA_CTRL) & ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) >> ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
  256. }
  257. /*!
  258. * @brief Clear the DMA request status falgs. Only external XBAR sources support DMA request.
  259. *
  260. * @param base ADC_ETC peripheral base address.
  261. * @param mask Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
  262. * trigger7:0x80.
  263. */
  264. static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask)
  265. {
  266. base->DMA_CTRL = ((base->DMA_CTRL) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) | (mask << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
  267. }
  268. /*!
  269. * @brief When enable, all logical will be reset.
  270. *
  271. * @param base ADC_ETC peripheral base address.
  272. * @param enable Enable/Disable the software reset.
  273. */
  274. static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
  275. {
  276. if (enable)
  277. {
  278. base->CTRL |= ADC_ETC_CTRL_SOFTRST_MASK;
  279. }
  280. else
  281. {
  282. base->CTRL &= ~ADC_ETC_CTRL_SOFTRST_MASK;
  283. }
  284. }
  285. /*!
  286. * @brief Do software trigger corresponding to each XBAR trigger sources.
  287. * Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
  288. * trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
  289. * can only work in hardware trigger mode.
  290. *
  291. * @param base ADC_ETC peripheral base address.
  292. * @param triggerGroup Trigger group index. Available number is 0~7.
  293. */
  294. static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup)
  295. {
  296. assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
  297. base->TRIG[triggerGroup].TRIGn_CTRL |= ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK;
  298. }
  299. /*!
  300. * @brief Get ADC conversion result from external XBAR sources.
  301. * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
  302. * return Trigger0 source's chain1 conversion result.
  303. *
  304. * @param base ADC_ETC peripheral base address.
  305. * @param triggerGroup Trigger group index. Available number is 0~7.
  306. * @param chainGroup Trigger chain group index. Available number is 0~7.
  307. * @return ADC conversion result value.
  308. */
  309. uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup);
  310. /* @} */
  311. #if defined(__cplusplus)
  312. }
  313. #endif
  314. /* @} */
  315. #endif /* _FSL_ADC_ETC_H_ */