fsl_dcdc.h 44 KB

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  1. /*
  2. * Copyright 2020-2021 NXP
  3. * All rights reserved.
  4. *
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. */
  8. #ifndef __FSL_DCDC_H__
  9. #define __FSL_DCDC_H__
  10. #include "fsl_common.h"
  11. /*!
  12. * @addtogroup dcdc_soc
  13. * @{
  14. */
  15. /*******************************************************************************
  16. * Definitions
  17. ******************************************************************************/
  18. /*! @brief DCDC driver version. */
  19. #define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */
  20. /*! @brief The array of VDD1P0 target voltage in standby mode. */
  21. #define STANDBY_MODE_VDD1P0_TARGET_VOLTAGE \
  22. { \
  23. 625, 650, 675, 700, 725, 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125, \
  24. 1150, 1175, 1200, 1225, 1250, 1275, 1300, 1325, 1350, 1375, 1400 \
  25. }
  26. /*! @brief The array of VDD1P8 target voltage in standby mode. */
  27. #define STANDBY_MODE_VDD1P8_TARGET_VOLTAGE \
  28. { \
  29. 1525, 1550, 1575, 1600, 1625, 1650, 1675, 1700, 1725, 1750, 1775, 1800, 1825, 1850, 1875, 1900, 1925, 1950, \
  30. 1975, 2000, 2025, 2050, 2075, 2100, 2125, 2150, 2175, 2200, 2225, 2250, 2275, 2300 \
  31. }
  32. /*! @brief The array of VDD1P0 target voltage in buck mode. */
  33. #define BUCK_MODE_VDD1P0_TARGET_VOLTAGE \
  34. { \
  35. 600, 625, 650, 675, 700, 725, 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, \
  36. 1125, 1150, 1175, 1200, 1225, 1250, 1275, 1300, 1325, 1350, 1375 \
  37. }
  38. /*! @brief The array of VDD1P8 target voltage in buck mode. */
  39. #define BUCK_MODE_VDD1P8_TARGET_VOLTAGE \
  40. { \
  41. 1500, 1525, 1550, 1575, 1600, 1625, 1650, 1675, 1700, 1725, 1750, 1775, 1800, 1825, 1850, 1875, 1900, 1925, \
  42. 1950, 1975, 2000, 2025, 2050, 2075, 2100, 2125, 2150, 2175, 2200, 2225, 2250, 2275 \
  43. }
  44. /*!
  45. * @brief The enumeration of DCDC status flags.
  46. */
  47. enum _dcdc_status_flags
  48. {
  49. kDCDC_AlreadySettledStatusFlag = DCDC_REG0_STS_DC_OK_MASK, /*!< Indicate DCDC status.
  50. 1'b1: DCDC already settled
  51. 1'b0: DCDC is settling. */
  52. };
  53. /*!
  54. * @brief System setpoints enumeration.
  55. */
  56. enum _dcdc_setpoint_map
  57. {
  58. kDCDC_SetPoint0 = 1UL << 0UL, /*!< Set point 0. */
  59. kDCDC_SetPoint1 = 1UL << 1UL, /*!< Set point 1. */
  60. kDCDC_SetPoint2 = 1UL << 2UL, /*!< Set point 2. */
  61. kDCDC_SetPoint3 = 1UL << 3UL, /*!< Set point 3. */
  62. kDCDC_SetPoint4 = 1UL << 4UL, /*!< Set point 4. */
  63. kDCDC_SetPoint5 = 1UL << 5UL, /*!< Set point 5. */
  64. kDCDC_SetPoint6 = 1UL << 6UL, /*!< Set point 6. */
  65. kDCDC_SetPoint7 = 1UL << 7UL, /*!< Set point 7. */
  66. kDCDC_SetPoint8 = 1UL << 8UL, /*!< Set point 8. */
  67. kDCDC_SetPoint9 = 1UL << 9UL, /*!< Set point 9. */
  68. kDCDC_SetPoint10 = 1UL << 10UL, /*!< Set point 10. */
  69. kDCDC_SetPoint11 = 1UL << 11UL, /*!< Set point 11. */
  70. kDCDC_SetPoint12 = 1UL << 12UL, /*!< Set point 12. */
  71. kDCDC_SetPoint13 = 1UL << 13UL, /*!< Set point 13. */
  72. kDCDC_SetPoint14 = 1UL << 14UL, /*!< Set point 14. */
  73. kDCDC_SetPoint15 = 1UL << 15UL /*!< Set point 15. */
  74. };
  75. /*!
  76. * @brief DCDC control mode, including setpoint control mode and static control mode.
  77. */
  78. typedef enum _dcdc_control_mode
  79. {
  80. kDCDC_StaticControl = 0U, /*!< Static control. */
  81. kDCDC_SetPointControl = 1U, /*!< Controlled by GPC set points. */
  82. } dcdc_control_mode_t;
  83. /*!
  84. * @brief DCDC trim input mode, including sample trim input and hold trim input.
  85. */
  86. typedef enum _dcdc_trim_input_mode
  87. {
  88. kDCDC_SampleTrimInput = 0U, /*!< Sample trim input. */
  89. kDCDC_HoldTrimInput = 1U, /*!< Hold trim input. */
  90. } dcdc_trim_input_mode_t;
  91. /*!
  92. * @brief The enumeration VDD1P0's target voltage value in standby mode.
  93. */
  94. typedef enum _dcdc_standby_mode_1P0_target_vol
  95. {
  96. kDCDC_1P0StbyTarget0P625V = 0U, /*!< In standby mode, the target voltage value of VDD1P0 is 0.625V. */
  97. kDCDC_1P0StbyTarget0P65V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.65V. */
  98. kDCDC_1P0StbyTarget0P675V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.675V. */
  99. kDCDC_1P0StbyTarget0P7V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.7V. */
  100. kDCDC_1P0StbyTarget0P725V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.725V. */
  101. kDCDC_1P0StbyTarget0P75V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.75V. */
  102. kDCDC_1P0StbyTarget0P775V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.775V. */
  103. kDCDC_1P0StbyTarget0P8V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.8V. */
  104. kDCDC_1P0StbyTarget0P825V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.825V. */
  105. kDCDC_1P0StbyTarget0P85V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.85V. */
  106. kDCDC_1P0StbyTarget0P875V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.875V. */
  107. kDCDC_1P0StbyTarget0P9V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.9V. */
  108. kDCDC_1P0StbyTarget0P925V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.925V. */
  109. kDCDC_1P0StbyTarget0P95V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.95V. */
  110. kDCDC_1P0StbyTarget0P975V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.975V. */
  111. kDCDC_1P0StbyTarget1P0V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.0V. */
  112. kDCDC_1P0StbyTarget1P025V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.025V. */
  113. kDCDC_1P0StbyTarget1P05V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.05V. */
  114. kDCDC_1P0StbyTarget1P075V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.075V. */
  115. kDCDC_1P0StbyTarget1P1V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.1V. */
  116. kDCDC_1P0StbyTarget1P125V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.125V. */
  117. kDCDC_1P0StbyTarget1P15V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.15V. */
  118. kDCDC_1P0StbyTarget1P175V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.175V. */
  119. kDCDC_1P0StbyTarget1P2V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.2V. */
  120. kDCDC_1P0StbyTarget1P225V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.225V. */
  121. kDCDC_1P0StbyTarget1P25V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.25V. */
  122. kDCDC_1P0StbyTarget1P275V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.275V. */
  123. kDCDC_1P0StbyTarget1P3V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.3V. */
  124. kDCDC_1P0StbyTarget1P325V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.325V. */
  125. kDCDC_1P0StbyTarget1P35V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.35V. */
  126. kDCDC_1P0StbyTarget1P375V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.375V. */
  127. kDCDC_1P0StbyTarget1P4V = 0x1FU, /*!< In standby mode, The target voltage value of VDD1P0 is 1.4V */
  128. } dcdc_standby_mode_1P0_target_vol_t;
  129. /*!
  130. * @brief The enumeration VDD1P8's target voltage value in standby mode.
  131. */
  132. typedef enum _dcdc_standby_mode_1P8_target_vol
  133. {
  134. kDCDC_1P8StbyTarget1P525V = 0U, /*!< In standby mode, the target voltage value of VDD1P8 is 1.525V. */
  135. kDCDC_1P8StbyTarget1P55V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.55V. */
  136. kDCDC_1P8StbyTarget1P575V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.575V. */
  137. kDCDC_1P8StbyTarget1P6V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.6V. */
  138. kDCDC_1P8StbyTarget1P625V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.625V. */
  139. kDCDC_1P8StbyTarget1P65V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.65V. */
  140. kDCDC_1P8StbyTarget1P675V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.675V. */
  141. kDCDC_1P8StbyTarget1P7V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.7V. */
  142. kDCDC_1P8StbyTarget1P725V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.725V. */
  143. kDCDC_1P8StbyTarget1P75V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.75V. */
  144. kDCDC_1P8StbyTarget1P775V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.775V. */
  145. kDCDC_1P8StbyTarget1P8V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.8V. */
  146. kDCDC_1P8StbyTarget1P825V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.825V. */
  147. kDCDC_1P8StbyTarget1P85V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.85V. */
  148. kDCDC_1P8StbyTarget1P875V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.875V. */
  149. kDCDC_1P8StbyTarget1P9V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.9V. */
  150. kDCDC_1P8StbyTarget1P925V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.925V. */
  151. kDCDC_1P8StbyTarget1P95V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.95V. */
  152. kDCDC_1P8StbyTarget1P975V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.975V. */
  153. kDCDC_1P8StbyTarget2P0V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.0V. */
  154. kDCDC_1P8StbyTarget2P025V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.025V. */
  155. kDCDC_1P8StbyTarget2P05V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.05V. */
  156. kDCDC_1P8StbyTarget2P075V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.075V. */
  157. kDCDC_1P8StbyTarget2P1V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.1V. */
  158. kDCDC_1P8StbyTarget2P125V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.125V. */
  159. kDCDC_1P8StbyTarget2P15V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.15V. */
  160. kDCDC_1P8StbyTarget2P175V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.175V. */
  161. kDCDC_1P8StbyTarget2P2V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.2V. */
  162. kDCDC_1P8StbyTarget2P225V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.225V. */
  163. kDCDC_1P8StbyTarget2P25V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.25V. */
  164. kDCDC_1P8StbyTarget2P275V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.275V. */
  165. kDCDC_1P8StbyTarget2P3V = 0x1FU, /*!< In standby mode, the target voltage value is 2.3V. */
  166. } dcdc_standby_mode_1P8_target_vol_t;
  167. /*!
  168. * @brief The enumeration VDD1P0's target voltage value in buck mode.
  169. */
  170. typedef enum _dcdc_buck_mode_1P0_target_vol
  171. {
  172. kDCDC_1P0BuckTarget0P6V = 0U, /*!< In buck mode, the target voltage value of VDD1P0 is 0.6V. */
  173. kDCDC_1P0BuckTarget0P625V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.625V. */
  174. kDCDC_1P0BuckTarget0P65V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.65V. */
  175. kDCDC_1P0BuckTarget0P675V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.675V. */
  176. kDCDC_1P0BuckTarget0P7V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.7V. */
  177. kDCDC_1P0BuckTarget0P725V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.725V. */
  178. kDCDC_1P0BuckTarget0P75V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.75V. */
  179. kDCDC_1P0BuckTarget0P775V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.775V. */
  180. kDCDC_1P0BuckTarget0P8V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.8V. */
  181. kDCDC_1P0BuckTarget0P825V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.825V. */
  182. kDCDC_1P0BuckTarget0P85V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.85V. */
  183. kDCDC_1P0BuckTarget0P875V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.875V. */
  184. kDCDC_1P0BuckTarget0P9V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.9V. */
  185. kDCDC_1P0BuckTarget0P925V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.925V. */
  186. kDCDC_1P0BuckTarget0P95V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.95V. */
  187. kDCDC_1P0BuckTarget0P975V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.975V. */
  188. kDCDC_1P0BuckTarget1P0V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.0V. */
  189. kDCDC_1P0BuckTarget1P025V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.025V. */
  190. kDCDC_1P0BuckTarget1P05V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.05V. */
  191. kDCDC_1P0BuckTarget1P075V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.075V. */
  192. kDCDC_1P0BuckTarget1P1V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.1V. */
  193. kDCDC_1P0BuckTarget1P125V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.125V. */
  194. kDCDC_1P0BuckTarget1P15V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.15V. */
  195. kDCDC_1P0BuckTarget1P175V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.175V. */
  196. kDCDC_1P0BuckTarget1P2V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.2V. */
  197. kDCDC_1P0BuckTarget1P225V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.225V. */
  198. kDCDC_1P0BuckTarget1P25V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.25V. */
  199. kDCDC_1P0BuckTarget1P275V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.275V. */
  200. kDCDC_1P0BuckTarget1P3V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.3V. */
  201. kDCDC_1P0BuckTarget1P325V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.325V. */
  202. kDCDC_1P0BuckTarget1P35V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.35V. */
  203. kDCDC_1P0BuckTarget1P375V = 0x1FU, /*!< In buck mode, the target voltage value of VDD1P0 is 1.375V. */
  204. } dcdc_buck_mode_1P0_target_vol_t;
  205. /*!
  206. * @brief The enumeration VDD1P8's target voltage value in buck mode.
  207. */
  208. typedef enum _dcdc_buck_mode_1P8_target_vol
  209. {
  210. kDCDC_1P8BuckTarget1P5V = 0U, /*!< In buck mode, the target voltage value of VDD1P0 is 1.5V. */
  211. kDCDC_1P8BuckTarget1P525V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.525V. */
  212. kDCDC_1P8BuckTarget1P55V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.55V. */
  213. kDCDC_1P8BuckTarget1P575V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.575V. */
  214. kDCDC_1P8BuckTarget1P6V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.6V. */
  215. kDCDC_1P8BuckTarget1P625V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.625V. */
  216. kDCDC_1P8BuckTarget1P65V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.65V. */
  217. kDCDC_1P8BuckTarget1P675V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.675V. */
  218. kDCDC_1P8BuckTarget1P7V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.7V. */
  219. kDCDC_1P8BuckTarget1P725V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.725V. */
  220. kDCDC_1P8BuckTarget1P75V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.75V. */
  221. kDCDC_1P8BuckTarget1P775V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.775V. */
  222. kDCDC_1P8BuckTarget1P8V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.8V. */
  223. kDCDC_1P8BuckTarget1P825V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.825V. */
  224. kDCDC_1P8BuckTarget1P85V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.85V. */
  225. kDCDC_1P8BuckTarget1P875V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.875V. */
  226. kDCDC_1P8BuckTarget1P9V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.9V. */
  227. kDCDC_1P8BuckTarget1P925V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.925V. */
  228. kDCDC_1P8BuckTarget1P95V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.95V. */
  229. kDCDC_1P8BuckTarget1P975V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.975V. */
  230. kDCDC_1P8BuckTarget2P0V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.0V. */
  231. kDCDC_1P8BuckTarget2P025V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.025V. */
  232. kDCDC_1P8BuckTarget2P05V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.05V. */
  233. kDCDC_1P8BuckTarget2P075V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.075V. */
  234. kDCDC_1P8BuckTarget2P1V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.1V. */
  235. kDCDC_1P8BuckTarget2P125V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.125V. */
  236. kDCDC_1P8BuckTarget2P15V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.15V. */
  237. kDCDC_1P8BuckTarget2P175V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.175V. */
  238. kDCDC_1P8BuckTarget2P2V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.2V. */
  239. kDCDC_1P8BuckTarget2P225V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.225V. */
  240. kDCDC_1P8BuckTarget2P25V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.25V. */
  241. kDCDC_1P8BuckTarget2P275V = 0x1FU, /*!< In buck mode, the target voltage value of VDD1P0 is 2.275V. */
  242. } dcdc_buck_mode_1P8_target_vol_t;
  243. /*!
  244. * @brief The current bias of low power comparator.
  245. */
  246. typedef enum _dcdc_comparator_current_bias
  247. {
  248. kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */
  249. kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */
  250. kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */
  251. kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */
  252. } dcdc_comparator_current_bias_t;
  253. /*!
  254. * @brief The threshold if peak current detection.
  255. */
  256. typedef enum _dcdc_peak_current_threshold
  257. {
  258. kDCDC_PeakCurrentRunMode250mALPMode1P5A = 0U, /*!< Over peak current threshold in low power mode is 250mA,
  259. in run mode is 1.5A */
  260. kDCDC_PeakCurrentRunMode200mALPMode1P5A, /*!< Over peak current threshold in low power mode is 200mA,
  261. in run mode is 1.5A */
  262. kDCDC_PeakCurrentRunMode250mALPMode2A, /*!< Over peak current threshold in low power mode is 250mA,
  263. in run mode is 2A */
  264. kDCDC_PeakCurrentRunMode200mALPMode2A, /*!< Over peak current threshold in low power mode is 200mA,
  265. in run mode is 2A */
  266. } dcdc_peak_current_threshold_t;
  267. /*!
  268. * @brief Oscillator clock option.
  269. */
  270. typedef enum _dcdc_clock_source
  271. {
  272. kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */
  273. kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */
  274. kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */
  275. } dcdc_clock_source_t;
  276. /*!
  277. * @brief Voltage output option.
  278. */
  279. typedef enum _dcdc_voltage_output_sel
  280. {
  281. kDCDC_VoltageOutput1P8 = 0U, /*!< 1.8V output. */
  282. kDCDC_VoltageOutput1P0 = 1U, /*!< 1.0V output. */
  283. } dcdc_voltage_output_sel_t;
  284. /*!
  285. * @brief Configuration for DCDC.
  286. */
  287. typedef struct _dcdc_config
  288. {
  289. dcdc_control_mode_t controlMode; /*!< DCDC control mode. */
  290. dcdc_trim_input_mode_t trimInputMode; /*!< Hold trim input. */
  291. bool enableDcdcTimeout; /*!< Enable internal count for DCDC_OK timeout. */
  292. bool enableSwitchingConverterOutput; /*!< Enable the VDDIO switching converter output.*/
  293. } dcdc_config_t;
  294. /*!
  295. * @brief Configuration for min power setting.
  296. */
  297. typedef struct _dcdc_min_power_config
  298. {
  299. bool enableUseHalfFreqForContinuous; /*!< Set DCDC clock to half frequency for the continuous mode. */
  300. } dcdc_min_power_config_t;
  301. /*!
  302. * @brief Configuration for DCDC detection.
  303. */
  304. typedef struct _dcdc_detection_config
  305. {
  306. bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */
  307. bool powerDownOverVoltageVdd1P8Detection; /*!< Power down over-voltage detection comparator for VDD1P8. */
  308. bool powerDownOverVoltageVdd1P0Detection; /*!< Power down over-voltage detection comparator for VDD1P0. */
  309. bool powerDownLowVoltageDetection; /*!< Power down low-voltage detection comparator. */
  310. bool powerDownOverCurrentDetection; /*!< Power down over-current detection. */
  311. bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */
  312. bool powerDownZeroCrossDetection; /*!< Power down the zero cross detection function for discontinuous conductor
  313. mode. */
  314. dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */
  315. } dcdc_detection_config_t;
  316. /*!
  317. * @brief Configuration for the loop control.
  318. */
  319. typedef struct _dcdc_loop_control_config
  320. {
  321. bool enableCommonHysteresis; /*!< Enable hysteresis in switching converter common mode analog comparators.
  322. This feature will improve transient supply ripple and efficiency. */
  323. bool enableCommonThresholdDetection; /*!< Increase the threshold detection for common mode analog comparator. */
  324. bool enableDifferentialHysteresis; /*!< Enable hysteresis in switching converter differential mode analog
  325. comparators. This feature will improve transient supply ripple and
  326. efficiency. */
  327. bool enableDifferentialThresholdDetection; /*!< Increase the threshold detection for differential mode analog
  328. comparators. */
  329. bool enableInvertHysteresisSign; /*!< Invert the sign of the hysteresis in DC-DC analog comparators. */
  330. bool enableRCThresholdDetection; /*!< Increase the threshold detection for RC scale circuit. */
  331. uint32_t enableRCScaleCircuit; /*!< Available range is 0~7. Enable analog circuit of DC-DC converter to respond
  332. faster under transient load conditions. */
  333. uint32_t complementFeedForwardStep; /*!< Available range is 0~7. Two's complement feed forward step in duty cycle in
  334. the switching DC-DC converter. Each time this field makes a transition from
  335. 0x0, the loop filter of the DC-DC converter is stepped once by a value
  336. proportional to the change. This can be used to force a certain control loop
  337. behavior, such as improving response under known heavy load transients. */
  338. uint32_t controlParameterMagnitude; /*!< Available range is 0~15. Magnitude of proportional control parameter in the
  339. switching DC-DC converter control loop. */
  340. uint32_t integralProportionalRatio; /*!< Available range is 0~3.Ratio of integral control parameter to proportional
  341. control parameter in the switching DC-DC converter, and can be used to
  342. optimize efficiency and loop response. */
  343. } dcdc_loop_control_config_t;
  344. /*!
  345. * @brief Configuration for DCDC internal regulator.
  346. */
  347. typedef struct _dcdc_internal_regulator_config
  348. {
  349. uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */
  350. } dcdc_internal_regulator_config_t;
  351. /*!
  352. * @brief Configuration for DCDC low power.
  353. */
  354. typedef struct _dcdc_low_power_config
  355. {
  356. bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */
  357. } dcdc_low_power_config_t;
  358. /*!
  359. * @brief DCDC configuration in set point mode.
  360. */
  361. typedef struct _dcdc_setpoint_config
  362. {
  363. uint32_t enableDCDCMap; /*!< The setpoint map that enable the DCDC module. Should be the OR'ed value of @ref
  364. _dcdc_setpoint_map. */
  365. uint32_t enableDigLogicMap; /*!< The setpoint map that enable the DCDC dig logic. Should be the OR'ed value of @ref
  366. _dcdc_setpoint_map. */
  367. uint32_t lowpowerMap; /*!< The setpoint map that enable the DCDC Low powermode. Should be the OR'ed value of @ref
  368. _dcdc_setpoint_map. */
  369. uint32_t standbyMap; /*!< The setpoint map that enable the DCDC standby mode. Should be the OR'ed value of @ref
  370. _dcdc_setpoint_map. */
  371. uint32_t standbyLowpowerMap; /*!< The setpoint map that enable the DCDC low power mode, when the related setpoint is
  372. in standby mode. Please refer to @ref _dcdc_setpoint_map. */
  373. dcdc_buck_mode_1P8_target_vol_t *buckVDD1P8TargetVoltage; /*!< Point to the array that store the target voltage
  374. level of VDD1P8 in buck mode, please refer to
  375. @ref dcdc_buck_mode_1P8_target_vol_t. Note that the
  376. pointed array must have 16 elements. */
  377. dcdc_buck_mode_1P0_target_vol_t *buckVDD1P0TargetVoltage; /*!< Point to the array that store the target voltage
  378. level of VDD1P0 in buck mode, please refer to
  379. @ref dcdc_buck_mode_1P0_target_vol_t. Note that the
  380. pointed array must have 16 elements. */
  381. dcdc_standby_mode_1P8_target_vol_t *standbyVDD1P8TargetVoltage; /*!< Point to the array that store the target
  382. voltage level of VDD1P8 in standby mode, please
  383. refer to @ref dcdc_standby_mode_1P8_target_vol_t.
  384. Note that the pointed array must have 16 elements. */
  385. dcdc_standby_mode_1P0_target_vol_t *standbyVDD1P0TargetVoltage; /*!< Point to the array that store the target
  386. voltage level of VDD1P0 in standby mode, please
  387. refer to @ref dcdc_standby_mode_1P0_target_vol_t.
  388. Note that the pointed array must have 16 elements. */
  389. } dcdc_setpoint_config_t;
  390. /*******************************************************************************
  391. * API
  392. ******************************************************************************/
  393. /*!
  394. * @name Initialization and De-initialization Interfaces
  395. * @{
  396. */
  397. /*!
  398. * @brief Initializes the basic resource of DCDC module, such as control mode, etc.
  399. *
  400. * @param base DCDC peripheral base address.
  401. * @param config Pointer to the @ref dcdc_config_t structure.
  402. */
  403. void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config);
  404. /*!
  405. * @brief De-initializes the DCDC module.
  406. *
  407. * @param base DCDC peripheral base address.
  408. */
  409. void DCDC_Deinit(DCDC_Type *base);
  410. /*!
  411. * @brief Gets the default setting for DCDC, such as control mode, etc.
  412. *
  413. * This function initializes the user configuration structure to a default value. The default values are:
  414. * @code
  415. * config->controlMode = kDCDC_StaticControl;
  416. * config->trimInputMode = kDCDC_SampleTrimInput;
  417. * config->enableDcdcTimeout = false;
  418. * config->enableSwitchingConverterOutput = false;
  419. * @endcode
  420. *
  421. * @param config Pointer to configuration structure. See to @ref dcdc_config_t.
  422. */
  423. void DCDC_GetDefaultConfig(dcdc_config_t *config);
  424. /*! @} */
  425. /*!
  426. * @name Power Mode Related Interfaces
  427. * @{
  428. */
  429. /*!
  430. * @brief Makes the DCDC enter into low power mode for GPC standby request or not.
  431. *
  432. * @param base DCDC peripheral base address.
  433. * @param enable Used to control the behavior.
  434. * - \b true Makes DCDC enter into low power mode for GPC standby mode.
  435. */
  436. static inline void DCDC_EnterLowPowerModeViaStandbyRequest(DCDC_Type *base, bool enable)
  437. {
  438. if (enable)
  439. {
  440. base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK;
  441. }
  442. else
  443. {
  444. base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK;
  445. }
  446. }
  447. /*!
  448. * @brief Makes DCDC enter into low power mode or not, before entering low power mode must disable stepping for VDD1P8
  449. * and VDD1P0.
  450. *
  451. * @param base DCDC peripheral base address.
  452. * @param enable Used to control the behavior.
  453. * - \b true Makes DCDC enter into low power mode.
  454. */
  455. static inline void DCDC_EnterLowPowerMode(DCDC_Type *base, bool enable)
  456. {
  457. if (enable)
  458. {
  459. base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
  460. base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK;
  461. }
  462. else
  463. {
  464. base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK;
  465. }
  466. }
  467. /*!
  468. * @brief Makes DCDC enter into standby mode or not.
  469. *
  470. * @param base DCDC peripheral base address.
  471. * @param enable Used to control the behavior.
  472. * - \b true Makes DCDC enter into standby mode.
  473. */
  474. static inline void DCDC_EnterStandbyMode(DCDC_Type *base, bool enable)
  475. {
  476. if (enable)
  477. {
  478. base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK;
  479. }
  480. else
  481. {
  482. base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK;
  483. }
  484. }
  485. /*! @} */
  486. /*!
  487. * @name Outputs' Target Voltage Related Interfaces
  488. * @{
  489. */
  490. /*!
  491. * @brief Sets the target value(ranges from 0.625V to 1.4V) of VDD1P0 in standby mode, 25mV each step.
  492. *
  493. * @param base DCDC peripheral base address.
  494. * @param targetVoltage The target value of VDD1P0 in standby mode, see @ref dcdc_standby_mode_1P0_target_vol_t.
  495. */
  496. static inline void DCDC_SetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base,
  497. dcdc_standby_mode_1P0_target_vol_t targetVoltage)
  498. {
  499. base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
  500. base->CTRL1 =
  501. ((base->CTRL1) & (~DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(targetVoltage);
  502. while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
  503. {
  504. }
  505. }
  506. /*!
  507. * @brief Gets the target value of VDD1P0 in standby mode, the result takes "mV" as the unit.
  508. *
  509. * @param base DCDC peripheral base address.
  510. *
  511. * @return The VDD1P0's voltage value in standby mode and the unit is "mV".
  512. */
  513. static inline uint16_t DCDC_GetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base)
  514. {
  515. const uint16_t vdd1P0TargetVoltage[] = STANDBY_MODE_VDD1P0_TARGET_VOLTAGE;
  516. uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT;
  517. return vdd1P0TargetVoltage[voltageValue];
  518. }
  519. /*!
  520. * @brief Sets the target value(ranges from 1.525V to 2.3V) of VDD1P8 in standby mode, 25mV each step.
  521. *
  522. * @param base DCDC peripheral base address.
  523. * @param targetVoltage The target value of VDD1P8 in standby mode, see @ref dcdc_standby_mode_1P8_target_vol_t.
  524. */
  525. static inline void DCDC_SetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base,
  526. dcdc_standby_mode_1P8_target_vol_t targetVoltage)
  527. {
  528. base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
  529. base->CTRL1 =
  530. ((base->CTRL1) & (~DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(targetVoltage);
  531. while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
  532. {
  533. }
  534. }
  535. /*!
  536. * @brief Gets the target value of VDD1P8 in standby mode, the result takes "mV" as the unit.
  537. *
  538. * @param base DCDC peripheral base address.
  539. *
  540. * @return The VDD1P8's voltage value in standby mode and the unit is "mV".
  541. */
  542. static inline uint16_t DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base)
  543. {
  544. const uint16_t vdd1P8TargetVoltage[] = STANDBY_MODE_VDD1P8_TARGET_VOLTAGE;
  545. uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT;
  546. return vdd1P8TargetVoltage[voltageValue];
  547. }
  548. /*!
  549. * @brief Sets the target value(ranges from 0.6V to 1.375V) of VDD1P0 in buck mode, 25mV each step.
  550. *
  551. * @param base DCDC peripheral base address.
  552. * @param targetVoltage The target value of VDD1P0 in buck mode, see @ref dcdc_buck_mode_1P0_target_vol_t.
  553. */
  554. static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P0_target_vol_t targetVoltage)
  555. {
  556. base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
  557. base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_TRG(targetVoltage));
  558. while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
  559. {
  560. }
  561. }
  562. /*!
  563. * @brief Gets the target value of VDD1P0 in buck mode, the result takes "mV" as the unit.
  564. *
  565. * @param base DCDC peripheral base address.
  566. *
  567. * @return The VDD1P0's voltage value in buck mode and the unit is "mV".
  568. */
  569. static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base)
  570. {
  571. const uint16_t vdd1P0TargetVoltage[] = BUCK_MODE_VDD1P0_TARGET_VOLTAGE;
  572. uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT;
  573. return vdd1P0TargetVoltage[voltageValue];
  574. }
  575. /*!
  576. * @brief Sets the target value(ranges from 1.5V to 2.275V) of VDD1P8 in buck mode, 25mV each step.
  577. *
  578. * @param base DCDC peripheral base address.
  579. * @param targetVoltage The target value of VDD1P8 in buck mode, see @ref dcdc_buck_mode_1P8_target_vol_t.
  580. */
  581. static inline void DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P8_target_vol_t targetVoltage)
  582. {
  583. base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
  584. base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P8CTRL_TRG(targetVoltage));
  585. while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
  586. {
  587. }
  588. }
  589. /*!
  590. * @brief Gets the target value of VDD1P8 in buck mode, the result takes "mV" as the unit.
  591. *
  592. * @param base DCDC peripheral base address.
  593. *
  594. * @return The VDD1P8's voltage value in buck mode and the unit is "mV".
  595. */
  596. static inline uint16_t DCDC_GetVDD1P8BuckModeTargetVoltage(DCDC_Type *base)
  597. {
  598. const uint16_t vdd1P8TargetVoltage[] = BUCK_MODE_VDD1P8_TARGET_VOLTAGE;
  599. uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT;
  600. return vdd1P8TargetVoltage[voltageValue];
  601. }
  602. /*!
  603. * @brief Enables/Disables stepping for VDD1P0, before entering low power modes the stepping for VDD1P0 must be
  604. * disabled.
  605. *
  606. * @param base DCDC peripheral base address.
  607. * @param enable Used to control the behavior.
  608. * - \b true Enables stepping for VDD1P0.
  609. * - \b false Disables stepping for VDD1P0.
  610. */
  611. static inline void DCDC_EnableVDD1P0TargetVoltageStepping(DCDC_Type *base, bool enable)
  612. {
  613. if (enable)
  614. {
  615. base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
  616. }
  617. else
  618. {
  619. base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
  620. }
  621. }
  622. /*!
  623. * @brief Enables/Disables stepping for VDD1P8, before entering low power modes the stepping for VDD1P8 must be
  624. * disabled.
  625. *
  626. * @param base DCDC peripheral base address.
  627. * @param enable Used to control the behavior.
  628. * - \b true Enables stepping for VDD1P8.
  629. * - \b false Disables stepping for VDD1P8.
  630. */
  631. static inline void DCDC_EnableVDD1P8TargetVoltageStepping(DCDC_Type *base, bool enable)
  632. {
  633. if (enable)
  634. {
  635. base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
  636. }
  637. else
  638. {
  639. base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
  640. }
  641. }
  642. /*! @} */
  643. /*!
  644. * @name Detection Related Inferfaces
  645. * @{
  646. */
  647. /*!
  648. * @brief Gets the default setting for detection configuration.
  649. *
  650. * The default configuration are set according to responding registers' setting when powered on.
  651. * They are:
  652. * @code
  653. * config->enableXtalokDetection = false;
  654. * config->powerDownOverVoltageVdd1P8Detection = true;
  655. * config->powerDownOverVoltageVdd1P0Detection = true;
  656. * config->powerDownLowVoltageDetection = false;
  657. * config->powerDownOverCurrentDetection = true;
  658. * config->powerDownPeakCurrentDetection = true;
  659. * config->powerDownZeroCrossDetection = true;
  660. * config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
  661. * config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
  662. * @endcode
  663. *
  664. * @param config Pointer to configuration structure. See to @ref dcdc_detection_config_t.
  665. */
  666. void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config);
  667. /*!
  668. * @brief Configures the DCDC detection.
  669. *
  670. * @param base DCDC peripheral base address.
  671. * @param config Pointer to configuration structure. See to @ref dcdc_detection_config_t.
  672. */
  673. void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config);
  674. /*! @} */
  675. /*!
  676. * @name DCDC Miscellaneous Inferfaces
  677. * @{
  678. */
  679. /*!
  680. * @brief Enables/Disables the output range comparator.
  681. *
  682. * The output range comparator is disabled by default.
  683. *
  684. * @param base DCDC peripheral base address.
  685. * @param enable Enable the feature or not.
  686. * - \b true Enable the output range comparator.
  687. * - \b false Disable the output range comparator.
  688. */
  689. static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable)
  690. {
  691. if (enable)
  692. {
  693. base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK;
  694. }
  695. else
  696. {
  697. base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK;
  698. }
  699. }
  700. /*!
  701. * @brief Configures the DCDC clock source.
  702. *
  703. * @param base DCDC peripheral base address.
  704. * @param clockSource Clock source for DCDC. See to @ref dcdc_clock_source_t.
  705. */
  706. void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource);
  707. /*!
  708. * @brief Gets the default setting for low power configuration.
  709. *
  710. * The default configuration are set according to responding registers' setting when powered on.
  711. * They are:
  712. * @code
  713. * config->enableAdjustHystereticValue = false;
  714. * @endcode
  715. *
  716. * @param config Pointer to configuration structure. See to @ref dcdc_low_power_config_t.
  717. */
  718. void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config);
  719. /*!
  720. * @brief Configures the DCDC low power.
  721. *
  722. * @param base DCDC peripheral base address.
  723. * @param config Pointer to configuration structure. See to @ref dcdc_low_power_config_t.
  724. */
  725. void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config);
  726. /*!
  727. * @brief Sets the bangap trim value(0~31) to trim bandgap voltage.
  728. *
  729. * @param base DCDC peripheral base address.
  730. * @param trimValue The bangap trim value. Available range is 0U-31U.
  731. */
  732. static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)
  733. {
  734. base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK;
  735. base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue);
  736. }
  737. /*!
  738. * @brief Gets the default setting for loop control configuration.
  739. *
  740. * The default configuration are set according to responding registers' setting when powered on.
  741. * They are:
  742. * @code
  743. * config->enableCommonHysteresis = false;
  744. * config->enableCommonThresholdDetection = false;
  745. * config->enableInvertHysteresisSign = false;
  746. * config->enableRCThresholdDetection = false;
  747. * config->enableRCScaleCircuit = 0U;
  748. * config->complementFeedForwardStep = 0U;
  749. * config->controlParameterMagnitude = 2U;
  750. * config->integralProportionalRatio = 2U;
  751. * @endcode
  752. *
  753. * @param config Pointer to configuration structure. See to @ref dcdc_loop_control_config_t.
  754. */
  755. void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config);
  756. /*!
  757. * @brief Configures the DCDC loop control.
  758. *
  759. * @param base DCDC peripheral base address.
  760. * @param config Pointer to configuration structure. See to @ref dcdc_loop_control_config_t.
  761. */
  762. void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config);
  763. /*!
  764. * @brief Configures for the min power.
  765. *
  766. * @param base DCDC peripheral base address.
  767. * @param config Pointer to configuration structure. See to @ref dcdc_min_power_config_t.
  768. */
  769. void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config);
  770. /*!
  771. * @brief Sets the current bias of low power comparator.
  772. *
  773. * @param base DCDC peripheral base address.
  774. * @param biasValue The current bias of low power comparator. Refer to @ref dcdc_comparator_current_bias_t.
  775. */
  776. static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasValue)
  777. {
  778. base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK;
  779. base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue);
  780. }
  781. /*!
  782. * @brief Configures the DCDC internal regulator.
  783. *
  784. * @param base DCDC peripheral base address.
  785. * @param config Pointer to configuration structure. See to @ref dcdc_internal_regulator_config_t.
  786. */
  787. void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config);
  788. /*!
  789. * @brief Adjusts delay to reduce ground noise.
  790. *
  791. * @param base DCDC peripheral base address.
  792. * @param enable Enable the feature or not.
  793. */
  794. static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)
  795. {
  796. if (enable)
  797. {
  798. base->REG3 |= DCDC_REG3_MISC_DELAY_TIMING_MASK;
  799. }
  800. else
  801. {
  802. base->REG3 &= ~DCDC_REG3_MISC_DELAY_TIMING_MASK;
  803. }
  804. }
  805. /*!
  806. * @brief Enables/Disables to improve the transition from heavy load to light load.
  807. *
  808. * @note It is valid while zero cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from
  809. * DCM.
  810. *
  811. * @param base DCDC peripheral base address.
  812. * @param enable Enable the feature or not.
  813. */
  814. static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
  815. {
  816. if (enable)
  817. {
  818. base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK;
  819. }
  820. else
  821. {
  822. base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK;
  823. }
  824. }
  825. /*! @} */
  826. /*!
  827. * @name Setpoint Control Related Interfaces
  828. */
  829. /*!
  830. * @brief Initializes DCDC module when the control mode selected as setpoint mode.
  831. *
  832. * @note The function should be invoked in the initial step to config the
  833. * DCDC via setpoint control mode.
  834. *
  835. * @param base DCDC peripheral base address.
  836. * @param config The pointer to the structure @ref dcdc_setpoint_config_t.
  837. */
  838. void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config);
  839. /*!
  840. * @brief Disable DCDC module when the control mode selected as setpoint mode.
  841. *
  842. * @param base DCDC peripheral base address.
  843. * @param setpointMap The map of the setpoint to disable the DCDC module,
  844. * Should be the OR'ed value of _dcdc_setpoint_map.
  845. */
  846. static inline void DCDC_SetPointDeinit(DCDC_Type *base, uint32_t setpointMap)
  847. {
  848. base->REG4 &= ~setpointMap;
  849. }
  850. /*! @} */
  851. /*!
  852. * @name DCDC Status Related Interfaces
  853. * @{
  854. */
  855. /*!
  856. * @brief Get DCDC status flags.
  857. *
  858. * @param base peripheral base address.
  859. * @return Mask of asserted status flags. See to @ref _dcdc_status_flags.
  860. */
  861. static inline uint32_t DCDC_GetStatusFlags(DCDC_Type *base)
  862. {
  863. return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK);
  864. }
  865. /* @} */
  866. /*!
  867. * @name Application Guideline Interfaces
  868. * @{
  869. */
  870. /*!
  871. * @brief Boots DCDC into DCM(discontinous conduction mode).
  872. *
  873. * @code
  874. * pwd_zcd=0x0;
  875. * DM_CTRL = 1'b1;
  876. * pwd_cmp_offset=0x0;
  877. * dcdc_loopctrl_en_rcscale=0x3 or 0x5;
  878. * DCM_set_ctrl=1'b1;
  879. * @endcode
  880. *
  881. * @param base DCDC peripheral base address.
  882. */
  883. void DCDC_BootIntoDCM(DCDC_Type *base);
  884. /*!
  885. * @brief Boots DCDC into CCM(continous conduction mode).
  886. *
  887. * @code
  888. * pwd_zcd=0x1;
  889. * pwd_cmp_offset=0x0;
  890. * dcdc_loopctrl_en_rcscale=0x3;
  891. * @endcode
  892. *
  893. * @param base DCDC peripheral base address.
  894. */
  895. void DCDC_BootIntoCCM(DCDC_Type *base);
  896. /*! @} */
  897. /*!
  898. * @}
  899. */
  900. #endif /* __FSL_DCDC_H__ */