fsl_iee.h 5.2 KB

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  1. /*
  2. * Copyright (c) 2016, Freescale Semiconductor, Inc.
  3. * Copyright 2017-2021 NXP
  4. * All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-3-Clause
  7. */
  8. #ifndef _FSL_IEE_H_
  9. #define _FSL_IEE_H_
  10. #include "fsl_common.h"
  11. /*!
  12. * @addtogroup iee
  13. * @{
  14. */
  15. /*******************************************************************************
  16. * Definitions
  17. ******************************************************************************/
  18. /*! @name Driver version */
  19. /*@{*/
  20. /*! @brief IEE driver version. Version 2.1.1.
  21. *
  22. * Current version: 2.1.1
  23. *
  24. * Change log:
  25. * - Version 2.0.0
  26. * - Initial version
  27. * - Version 2.1.0
  28. * - Add region lock function IEE_LockRegionConfig() and driver clock control
  29. * - Version 2.1.1
  30. * - Fixed MISRA issues.
  31. */
  32. #define FSL_IEE_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
  33. /*@}*/
  34. /*! @brief IEE region. */
  35. typedef enum _iee_region
  36. {
  37. kIEE_Region0 = 0U, /*!< IEE region 0 */
  38. kIEE_Region1 = 1U, /*!< IEE region 1 */
  39. kIEE_Region2 = 2U, /*!< IEE region 2 */
  40. kIEE_Region3 = 3U, /*!< IEE region 3 */
  41. kIEE_Region4 = 4U, /*!< IEE region 4 */
  42. kIEE_Region5 = 5U, /*!< IEE region 5 */
  43. kIEE_Region6 = 6U, /*!< IEE region 6 */
  44. kIEE_Region7 = 7U /*!< IEE region 7 */
  45. } iee_region_t;
  46. /*! @brief IEE AES enablement/bypass. */
  47. typedef enum _iee_aes_bypass
  48. {
  49. kIEE_AesUseMdField = 0U, /*!< AES encryption/decryption enabled */
  50. kIEE_AesBypass = 1U /*!< AES encryption/decryption bypass */
  51. } iee_aes_bypass_t;
  52. /*! @brief IEE AES mode. */
  53. typedef enum _iee_aes_mode
  54. {
  55. kIEE_ModeNone = 0U, /*!< AES NONE mode */
  56. kIEE_ModeAesXTS = 1U, /*!< AES XTS mode */
  57. kIEE_ModeAesCTRWAddress = 2U, /*!< CTR w address binding mode */
  58. kIEE_ModeAesCTRWOAddress = 3U, /*!< AES CTR w/o address binding mode */
  59. kIEE_ModeAesCTRkeystream = 4U /*!< AES CTR keystream only */
  60. } iee_aes_mode_t;
  61. /*! @brief IEE AES key size. */
  62. typedef enum _iee_aes_key_size
  63. {
  64. kIEE_AesCTR128XTS256 = 0U, /*!< AES 128 bits (CTR), 256 bits (XTS) */
  65. kIEE_AesCTR256XTS512 = 1U /*!< AES 256 bits (CTR), 512 bits (XTS) */
  66. } iee_aes_key_size_t;
  67. /*! @brief IEE AES ke number. */
  68. typedef enum _iee_aes_key_num
  69. {
  70. kIEE_AesKey1 = 1U, /*!< AES Key 1 */
  71. kIEE_AesKey2 = 2U /*!< AES Key 2 */
  72. } iee_aes_key_num_t;
  73. /*! @brief IEE configuration structure. */
  74. typedef struct _iee_config
  75. {
  76. iee_aes_bypass_t bypass; /*!< AES encryption/decryption bypass */
  77. iee_aes_mode_t mode; /*!< AES mode */
  78. iee_aes_key_size_t keySize; /*!< size of AES key */
  79. uint32_t pageOffset; /*!< Offset to physical memory location from IEE start address */
  80. } iee_config_t;
  81. /*******************************************************************************
  82. * API
  83. ******************************************************************************/
  84. #if defined(__cplusplus)
  85. extern "C" {
  86. #endif
  87. /*!
  88. * @brief Resets IEE module to factory default values.
  89. *
  90. * This function performs hardware reset of IEE module. Attributes and keys of all regions are cleared.
  91. *
  92. * @param base IEER peripheral address.
  93. */
  94. void IEE_Init(IEE_Type *base);
  95. /*!
  96. * @brief Loads default values to the IEE configuration structure.
  97. *
  98. * Loads default values to the IEE region configuration structure. The default values are as follows.
  99. * @code
  100. * config->bypass = kIEE_AesUseMdField;
  101. * config->mode = kIEE_ModeNone;
  102. * config->keySize = kIEE_AesCTR128XTS256;
  103. * config->pageOffset = 0U;
  104. * @endcode
  105. *
  106. * @param config Configuration for the selected IEE region.
  107. */
  108. void IEE_GetDefaultConfig(iee_config_t *config);
  109. /*!
  110. * @brief Sets the IEE module according to the configuration structure.
  111. *
  112. * This function configures IEE region according to configuration structure.
  113. *
  114. * @param base IEE peripheral address.
  115. * @param region Selection of the IEE region to be configured.
  116. * @param config Configuration for the selected IEE region.
  117. */
  118. void IEE_SetRegionConfig(IEE_Type *base, iee_region_t region, iee_config_t *config);
  119. /*!
  120. * @brief Sets the IEE module key.
  121. *
  122. * This function sets specified AES key for the given region.
  123. *
  124. * @param base IEE peripheral address.
  125. * @param region Selection of the IEE region to be configured.
  126. * @param keyNum Selection of AES KEY1 or KEY2.
  127. * @param key AES key.
  128. * @param keySize Size of AES key.
  129. */
  130. status_t IEE_SetRegionKey(
  131. IEE_Type *base, iee_region_t region, iee_aes_key_num_t keyNum, const uint8_t *key, size_t keySize);
  132. /*!
  133. * @brief Computes IEE offset to be set for specifed memory location.
  134. *
  135. * This function calculates offset that must be set for IEE region to access physical memory location.
  136. *
  137. * @param addressIee Address of IEE peripheral.
  138. * @param addressMemory Address of physical memory location.
  139. */
  140. static inline uint32_t IEE_GetOffset(uint32_t addressIee, uint32_t addressMemory)
  141. {
  142. return (addressMemory - addressIee) >> 12;
  143. }
  144. /*!
  145. * @brief Lock the IEE region configuration.
  146. *
  147. * This function locks IEE region registers for Key, Offset and Attribute.
  148. * Only system reset can clear the Lock bit.
  149. *
  150. * @param base IEE peripheral address.
  151. * @param region Selection of the IEE region to be locked.
  152. */
  153. void IEE_LockRegionConfig(IEE_Type *base, iee_region_t region);
  154. #if defined(__cplusplus)
  155. }
  156. #endif
  157. /*!
  158. *@}
  159. */
  160. #endif /* _FSL_IEE_H_ */