board.c 3.1 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. *2021-06-10 xiaoyu implement rt_hw_us_delay()
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "board.h"
  13. #include "tick.h"
  14. #include "drv_uart.h"
  15. #include "encoding.h"
  16. #include "fpioa.h"
  17. #include "dmac.h"
  18. #include "dmalock.h"
  19. void init_bss(void)
  20. {
  21. unsigned int *dst;
  22. dst = &__bss_start;
  23. while (dst < &__bss_end)
  24. {
  25. *dst++ = 0;
  26. }
  27. }
  28. void primary_cpu_entry(void)
  29. {
  30. extern void entry(void);
  31. /* disable global interrupt */
  32. init_bss();
  33. rt_hw_interrupt_disable();
  34. entry();
  35. }
  36. #include <clint.h>
  37. #include <sysctl.h>
  38. int freq(void)
  39. {
  40. rt_uint64_t value = 0;
  41. value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL0);
  42. rt_kprintf("PLL0: %d\n", value);
  43. value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL1);
  44. rt_kprintf("PLL1: %d\n", value);
  45. value = sysctl_clock_get_freq(SYSCTL_CLOCK_PLL2);
  46. rt_kprintf("PLL2: %d\n", value);
  47. value = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
  48. rt_kprintf("CPU : %d\n", value);
  49. value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0);
  50. rt_kprintf("APB0: %d\n", value);
  51. value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB1);
  52. rt_kprintf("APB1: %d\n", value);
  53. value = sysctl_clock_get_freq(SYSCTL_CLOCK_APB2);
  54. rt_kprintf("APB2: %d\n", value);
  55. value = sysctl_clock_get_freq(SYSCTL_CLOCK_HCLK);
  56. rt_kprintf("HCLK: %d\n", value);
  57. value = clint_get_time();
  58. rt_kprintf("mtime: %d\n", value);
  59. return 0;
  60. }
  61. MSH_CMD_EXPORT(freq, show freq info);
  62. #ifdef RT_USING_SMP
  63. extern int rt_hw_clint_ipi_enable(void);
  64. #endif
  65. void rt_hw_board_init(void)
  66. {
  67. sysctl_pll_set_freq(SYSCTL_PLL0, 800000000UL);
  68. sysctl_pll_set_freq(SYSCTL_PLL1, 400000000UL);
  69. sysctl_pll_set_freq(SYSCTL_PLL2, 45158400UL);
  70. sysctl_clock_set_threshold(SYSCTL_THRESHOLD_APB1, 2);
  71. /* Init FPIOA */
  72. fpioa_init();
  73. /* Dmac init */
  74. dmac_init();
  75. dmalock_init();
  76. /* initalize interrupt */
  77. rt_hw_interrupt_init();
  78. /* initialize hardware interrupt */
  79. rt_hw_uart_init();
  80. rt_hw_tick_init();
  81. #ifdef RT_USING_SMP
  82. rt_hw_clint_ipi_enable();
  83. #endif
  84. #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
  85. /* set console device */
  86. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  87. #endif
  88. #ifdef RT_USING_HEAP
  89. rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END);
  90. /* initialize memory system */
  91. rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
  92. #endif
  93. #ifdef RT_USING_COMPONENTS_INIT
  94. rt_components_board_init();
  95. #endif
  96. }
  97. void rt_hw_cpu_reset(void)
  98. {
  99. sysctl->soft_reset.soft_reset = 1;
  100. while(1);
  101. }
  102. MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
  103. /**
  104. * This function will delay for some us.
  105. *
  106. * @param us the delay time of us
  107. */
  108. void rt_hw_us_delay(rt_uint32_t usec)
  109. {
  110. rt_uint32_t cycle = read_cycle();
  111. rt_uint32_t nop_all = usec * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / 1000000UL;
  112. while (1)
  113. {
  114. if(read_cycle() - cycle >= nop_all)
  115. break;
  116. }
  117. }