serial.c 9.7 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2006-08-23 Bernard first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "lpc214x.h"
  13. #include "board.h"
  14. /* serial hardware register */
  15. #define REG8(d) (*((volatile unsigned char *)(d)))
  16. #define REG32(d) (*((volatile unsigned long *)(d)))
  17. #define UART_RBR(base) REG8(base + 0x00)
  18. #define UART_THR(base) REG8(base + 0x00)
  19. #define UART_IER(base) REG32(base + 0x04)
  20. #define UART_IIR(base) REG32(base + 0x08)
  21. #define UART_FCR(base) REG8(base + 0x08)
  22. #define UART_LCR(base) REG8(base + 0x0C)
  23. #define UART_MCR(base) REG8(base + 0x10)
  24. #define UART_LSR(base) REG8(base + 0x14)
  25. #define UART_MSR(base) REG8(base + 0x18)
  26. #define UART_SCR(base) REG8(base + 0x1C)
  27. #define UART_DLL(base) REG8(base + 0x00)
  28. #define UART_DLM(base) REG8(base + 0x04)
  29. #define UART_ACR(base) REG32(base + 0x20)
  30. #define UART_FDR(base) REG32(base + 0x28)
  31. #define UART_TER(base) REG8(base + 0x30)
  32. /* LPC serial device */
  33. struct rt_lpcserial
  34. {
  35. /* inherit from device */
  36. struct rt_device parent;
  37. rt_uint32_t hw_base;
  38. rt_uint32_t irqno;
  39. rt_uint32_t baudrate;
  40. /* reception field */
  41. rt_uint16_t save_index, read_index;
  42. rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
  43. };
  44. #ifdef RT_USING_UART1
  45. struct rt_lpcserial serial1;
  46. #endif
  47. #ifdef RT_USING_UART2
  48. struct rt_lpcserial serial2;
  49. #endif
  50. void rt_hw_serial_init(void);
  51. #define U0PINS 0x00000005
  52. void rt_hw_uart_isr(struct rt_lpcserial* lpc_serial)
  53. {
  54. rt_uint32_t iir;
  55. RT_ASSERT(lpc_serial != RT_NULL)
  56. RT_UNUSED(iir);
  57. if (UART_LSR(lpc_serial->hw_base) & 0x01)
  58. {
  59. rt_base_t level;
  60. while (UART_LSR(lpc_serial->hw_base) & 0x01)
  61. {
  62. /* disable interrupt */
  63. level = rt_hw_interrupt_disable();
  64. /* read character */
  65. lpc_serial->rx_buffer[lpc_serial->save_index] =
  66. UART_RBR(lpc_serial->hw_base);
  67. lpc_serial->save_index ++;
  68. if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
  69. lpc_serial->save_index = 0;
  70. /* if the next position is read index, discard this 'read char' */
  71. if (lpc_serial->save_index == lpc_serial->read_index)
  72. {
  73. lpc_serial->read_index ++;
  74. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  75. lpc_serial->read_index = 0;
  76. }
  77. /* enable interrupt */
  78. rt_hw_interrupt_enable(level);
  79. }
  80. /* invoke callback */
  81. if(lpc_serial->parent.rx_indicate != RT_NULL)
  82. {
  83. lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
  84. }
  85. }
  86. /* clear interrupt source */
  87. iir = UART_IIR(lpc_serial->hw_base);
  88. /* acknowledge Interrupt */
  89. VICVectAddr = 0;
  90. }
  91. #ifdef RT_USING_UART1
  92. void rt_hw_uart_isr_1(int irqno, void *param)
  93. {
  94. /* get lpc serial device */
  95. rt_hw_uart_isr(&serial1);
  96. }
  97. #endif
  98. #ifdef RT_USING_UART2
  99. void rt_hw_uart_isr_2(int irqno, void *param)
  100. {
  101. /* get lpc serial device */
  102. rt_hw_uart_isr(&serial2);
  103. }
  104. #endif
  105. /**
  106. * @addtogroup LPC214x
  107. */
  108. /*@{*/
  109. static rt_err_t rt_serial_init (rt_device_t dev)
  110. {
  111. return RT_EOK;
  112. }
  113. static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
  114. {
  115. struct rt_lpcserial* lpc_serial;
  116. lpc_serial = (struct rt_lpcserial*) dev;
  117. RT_ASSERT(lpc_serial != RT_NULL);
  118. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  119. {
  120. /* init UART rx interrupt */
  121. UART_IER(lpc_serial->hw_base) = 0x01;
  122. /* install ISR */
  123. if (lpc_serial->irqno == UART0_INT)
  124. {
  125. #ifdef RT_USING_UART1
  126. rt_hw_interrupt_install(lpc_serial->irqno,
  127. rt_hw_uart_isr_1, &serial1, "UART1");
  128. #endif
  129. }
  130. else
  131. {
  132. #ifdef RT_USING_UART2
  133. rt_hw_interrupt_install(lpc_serial->irqno,
  134. rt_hw_uart_isr_2, &serial2, "UART2");
  135. #endif
  136. }
  137. rt_hw_interrupt_umask(lpc_serial->irqno);
  138. }
  139. return RT_EOK;
  140. }
  141. static rt_err_t rt_serial_close(rt_device_t dev)
  142. {
  143. struct rt_lpcserial* lpc_serial;
  144. lpc_serial = (struct rt_lpcserial*) dev;
  145. RT_ASSERT(lpc_serial != RT_NULL);
  146. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  147. {
  148. /* disable UART rx interrupt */
  149. UART_IER(lpc_serial->hw_base) = 0x00;
  150. }
  151. return RT_EOK;
  152. }
  153. static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
  154. {
  155. return RT_EOK;
  156. }
  157. static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
  158. {
  159. rt_uint8_t* ptr;
  160. struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
  161. RT_ASSERT(lpc_serial != RT_NULL);
  162. /* point to buffer */
  163. ptr = (rt_uint8_t*) buffer;
  164. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  165. {
  166. while (size)
  167. {
  168. /* interrupt receive */
  169. rt_base_t level;
  170. /* disable interrupt */
  171. level = rt_hw_interrupt_disable();
  172. if (lpc_serial->read_index != lpc_serial->save_index)
  173. {
  174. *ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
  175. lpc_serial->read_index ++;
  176. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  177. lpc_serial->read_index = 0;
  178. }
  179. else
  180. {
  181. /* no data in rx buffer */
  182. /* enable interrupt */
  183. rt_hw_interrupt_enable(level);
  184. break;
  185. }
  186. /* enable interrupt */
  187. rt_hw_interrupt_enable(level);
  188. ptr ++; size --;
  189. }
  190. return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
  191. }
  192. else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
  193. {
  194. /* not support right now */
  195. RT_ASSERT(0);
  196. }
  197. /* polling mode */
  198. while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
  199. {
  200. /* Read Character */
  201. *ptr = UART_RBR(lpc_serial->hw_base);
  202. ptr ++;
  203. size --;
  204. }
  205. return (rt_size_t)ptr - (rt_size_t)buffer;
  206. }
  207. static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
  208. {
  209. struct rt_lpcserial* lpc_serial;
  210. char *ptr;
  211. lpc_serial = (struct rt_lpcserial*) dev;
  212. if (dev->flag & RT_DEVICE_FLAG_INT_TX)
  213. {
  214. /* not support */
  215. RT_ASSERT(0);
  216. }
  217. else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
  218. {
  219. /* not support */
  220. RT_ASSERT(0);
  221. }
  222. /* polling write */
  223. ptr = (char *)buffer;
  224. if (dev->flag & RT_DEVICE_FLAG_STREAM)
  225. {
  226. /* stream mode */
  227. while (size)
  228. {
  229. if (*ptr == '\n')
  230. {
  231. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  232. UART_THR(lpc_serial->hw_base) = '\r';
  233. }
  234. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  235. UART_THR(lpc_serial->hw_base) = *ptr;
  236. ptr ++;
  237. size --;
  238. }
  239. }
  240. else
  241. {
  242. while (size)
  243. {
  244. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  245. UART_THR(lpc_serial->hw_base) = *ptr;
  246. ptr ++;
  247. size --;
  248. }
  249. }
  250. return (rt_size_t) ptr - (rt_size_t) buffer;
  251. }
  252. void rt_hw_serial_init(void)
  253. {
  254. struct rt_lpcserial* lpc_serial;
  255. #ifdef RT_USING_UART1
  256. lpc_serial = &serial1;
  257. lpc_serial->parent.type = RT_Device_Class_Char;
  258. lpc_serial->hw_base = 0xE000C000;
  259. lpc_serial->baudrate = 115200;
  260. lpc_serial->irqno = UART0_INT;
  261. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  262. lpc_serial->read_index = lpc_serial->save_index = 0;
  263. /* Enable UART0 RxD and TxD pins */
  264. PINSEL0 |= 0x05;
  265. /* 8 bits, no Parity, 1 Stop bit */
  266. UART_LCR(lpc_serial->hw_base) = 0x83;
  267. /* Setup Baudrate */
  268. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  269. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  270. /* DLAB = 0 */
  271. UART_LCR(lpc_serial->hw_base) = 0x03;
  272. lpc_serial->parent.type = RT_Device_Class_Char;
  273. lpc_serial->parent.init = rt_serial_init;
  274. lpc_serial->parent.open = rt_serial_open;
  275. lpc_serial->parent.close = rt_serial_close;
  276. lpc_serial->parent.read = rt_serial_read;
  277. lpc_serial->parent.write = rt_serial_write;
  278. lpc_serial->parent.control = rt_serial_control;
  279. lpc_serial->parent.user_data = RT_NULL;
  280. rt_device_register(&lpc_serial->parent,
  281. "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
  282. #endif
  283. #ifdef RT_USING_UART2
  284. lpc_serial = &serial2;
  285. lpc_serial->parent.type = RT_Device_Class_Char;
  286. lpc_serial->hw_base = 0xE0010000;
  287. lpc_serial->baudrate = 115200;
  288. lpc_serial->irqno = UART1_INT;
  289. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  290. lpc_serial->read_index = lpc_serial->save_index = 0;
  291. /* Enable UART1 RxD and TxD pins */
  292. PINSEL0 |= 0x05 << 16;
  293. /* 8 bits, no Parity, 1 Stop bit */
  294. UART_LCR(lpc_serial->hw_base) = 0x83;
  295. /* Setup Baudrate */
  296. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  297. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  298. /* DLAB = 0 */
  299. UART_LCR(lpc_serial->hw_base) = 0x03;
  300. lpc_serial->parent.type = RT_Device_Class_Char;
  301. lpc_serial->parent.init = rt_serial_init;
  302. lpc_serial->parent.open = rt_serial_open;
  303. lpc_serial->parent.close = rt_serial_close;
  304. lpc_serial->parent.read = rt_serial_read;
  305. lpc_serial->parent.write = rt_serial_write;
  306. lpc_serial->parent.control = rt_serial_control;
  307. lpc_serial->parent.user_data = RT_NULL;
  308. rt_device_register(&lpc_serial->parent,
  309. "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
  310. #endif
  311. }
  312. /*@}*/