lpc_clkpwr.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326
  1. /**********************************************************************
  2. * $Id$ lpc_clkpwr.c 2011-06-02
  3. *//**
  4. * @file lpc_clkpwr.c
  5. * @brief Contains all functions support for Clock and Power Control
  6. * firmware library on LPC
  7. * @version 1.0
  8. * @date 02. June. 2011
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2011, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. * Permission to use, copy, modify, and distribute this software and its
  26. * documentation is hereby granted, under NXP Semiconductors'
  27. * relevant copyright in the software, without fee, provided that it
  28. * is used in conjunction with NXP Semiconductors microcontrollers. This
  29. * copyright, permission, and disclaimer notice must appear in all copies of
  30. * this code.
  31. **********************************************************************/
  32. /* Peripheral group ----------------------------------------------------------- */
  33. /** @addtogroup CLKPWR
  34. * @{
  35. */
  36. #ifdef __BUILD_WITH_EXAMPLE__
  37. #include "lpc_libcfg.h"
  38. #else
  39. #include "lpc_libcfg_default.h"
  40. #endif /* __BUILD_WITH_EXAMPLE__ */
  41. #ifdef _CLKPWR
  42. /* Includes ------------------------------------------------------------------- */
  43. #include "lpc_clkpwr.h"
  44. uint32_t USBFrequency = 0;
  45. /* Public Functions ----------------------------------------------------------- */
  46. /** @addtogroup CLKPWR_Public_Functions
  47. * @{
  48. */
  49. /*********************************************************************//**
  50. * @brief Set value of each Peripheral Clock Selection
  51. * @param[in] ClkType clock type that will be divided, should be:
  52. * - CLKPWR_CLKTYPE_CPU : CPU clock
  53. * - CLKPWR_CLKTYPE_PER : Peripheral clock
  54. * - CLKPWR_CLKTYPE_EMC : EMC clock
  55. * - CLKPWR_CLKTYPE_USB : USB clock
  56. * @param[in] DivVal Value of divider. This value should be set as follows:
  57. * - CPU clock: DivVal must be in range: 0..31
  58. * - Peripheral clock: DivVal must be in range: 0..31
  59. * - EMC clock: DivVal must be:
  60. * + 0: The EMC uses the same clock as the CPU
  61. * + 1: The EMC uses a clock at half the rate of the CPU
  62. * - USB clock: DivVal must be:
  63. * + 0: the divider is turned off, no clock will
  64. * be provided to the USB subsystem
  65. * + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
  66. * + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
  67. * @return none
  68. * Note: Pls assign right DivVal, this function will not check if it is illegal.
  69. **********************************************************************/
  70. void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal)
  71. {
  72. uint32_t tmp;
  73. switch(ClkType)
  74. {
  75. case CLKPWR_CLKTYPE_CPU:
  76. tmp = LPC_SC->CCLKSEL & ~(0x1F);
  77. tmp |= DivVal & 0x1F;
  78. LPC_SC->CCLKSEL = tmp;
  79. SystemCoreClockUpdate(); //Update clock
  80. break;
  81. case CLKPWR_CLKTYPE_PER:
  82. tmp = LPC_SC->PCLKSEL & ~(0x1F);
  83. tmp |= DivVal & 0x1F;
  84. LPC_SC->PCLKSEL = tmp;
  85. SystemCoreClockUpdate(); //Update clock
  86. break;
  87. case CLKPWR_CLKTYPE_EMC:
  88. tmp = LPC_SC->EMCCLKSEL & ~(0x01);
  89. tmp |= DivVal & 0x01;
  90. LPC_SC->EMCCLKSEL = tmp;
  91. SystemCoreClockUpdate(); //Update clock
  92. break;
  93. case CLKPWR_CLKTYPE_USB:
  94. tmp = LPC_SC->USBCLKSEL & ~(0x1F);
  95. tmp |= DivVal & 0x1F;
  96. LPC_SC->USBCLKSEL |= DivVal & 0x1F;
  97. SystemCoreClockUpdate(); //Update clock
  98. break;
  99. default:
  100. while(1);//Error Loop;
  101. }
  102. }
  103. /*********************************************************************//**
  104. * @brief Get current clock value
  105. * @param[in] ClkType clock type that will be divided, should be:
  106. * - CLKPWR_CLKTYPE_CPU : CPU clock
  107. * - CLKPWR_CLKTYPE_PER : Peripheral clock
  108. * - CLKPWR_CLKTYPE_EMC : EMC clock
  109. * - CLKPWR_CLKTYPE_USB : USB clock
  110. **********************************************************************/
  111. uint32_t CLKPWR_GetCLK (uint8_t ClkType)
  112. {
  113. switch(ClkType)
  114. {
  115. case CLKPWR_CLKTYPE_CPU:
  116. return SystemCoreClock;
  117. case CLKPWR_CLKTYPE_PER:
  118. return PeripheralClock;
  119. case CLKPWR_CLKTYPE_EMC:
  120. return EMCClock;
  121. case CLKPWR_CLKTYPE_USB:
  122. return USBClock;
  123. default:
  124. while(1);//error loop
  125. }
  126. }
  127. /*********************************************************************//**
  128. * @brief Configure power supply for each peripheral according to NewState
  129. * @param[in] PPType Type of peripheral used to enable power,
  130. * should be one of the following:
  131. * - CLKPWR_PCONP_PCLCD : LCD
  132. * - CLKPWR_PCONP_PCTIM0 : Timer 0
  133. * - CLKPWR_PCONP_PCTIM1 : Timer 1
  134. * - CLKPWR_PCONP_PCUART0 : UART 0
  135. * - CLKPWR_PCONP_PCUART1 : UART 1
  136. * - CLKPWR_PCONP_PCPWM0 : PWM 0
  137. * - CLKPWR_PCONP_PCPWM1 : PWM 1
  138. * - CLKPWR_PCONP_PCI2C0 : I2C 0
  139. * - CLKPWR_PCONP_PCUART4 : UART4
  140. * - CLKPWR_PCONP_PCLCD : LCD
  141. * - CLKPWR_PCONP_PCTIM0 : Timer 0
  142. * - CLKPWR_PCONP_PCRTC : RTC
  143. * - CLKPWR_PCONP_PCSSP1 : SSP 1
  144. * - CLKPWR_PCONP_PCEMC : EMC
  145. * - CLKPWR_PCONP_PCADC : ADC
  146. * - CLKPWR_PCONP_PCAN1 : CAN 1
  147. * - CLKPWR_PCONP_PCAN2 : CAN 2
  148. * - CLKPWR_PCONP_PCGPIO : GPIO
  149. * - CLKPWR_PCONP_PCMC : MCPWM
  150. * - CLKPWR_PCONP_PCQEI : QEI
  151. * - CLKPWR_PCONP_PCI2C1 : I2C 1
  152. * - CLKPWR_PCONP_PCSSP2 : SSP 2
  153. * - CLKPWR_PCONP_PCSSP0 : SSP 0
  154. * - CLKPWR_PCONP_PCTIM2 : Timer 2
  155. * - CLKPWR_PCONP_PCTIM3 : Timer 3
  156. * - CLKPWR_PCONP_PCUART2 : UART 2
  157. * - CLKPWR_PCONP_PCUART3 : UART 3
  158. * - CLKPWR_PCONP_PCI2C2 : I2C 2
  159. * - CLKPWR_PCONP_PCI2S : I2S
  160. * - CLKPWR_PCONP_PCSDC : SDC
  161. * - CLKPWR_PCONP_PCGPDMA : GPDMA
  162. * - CLKPWR_PCONP_PCENET : Ethernet
  163. * - CLKPWR_PCONP_PCUSB : USB
  164. *
  165. * @param[in] NewState New state of Peripheral Power, should be:
  166. * - ENABLE : Enable power for this peripheral
  167. * - DISABLE : Disable power for this peripheral
  168. *
  169. * @return none
  170. **********************************************************************/
  171. void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
  172. {
  173. if (NewState == ENABLE)
  174. {
  175. LPC_SC->PCONP |= PPType;
  176. }
  177. else if (NewState == DISABLE)
  178. {
  179. LPC_SC->PCONP &= ~PPType;
  180. }
  181. }
  182. #if 0
  183. // nxp21346
  184. /*********************************************************************//**
  185. * @brief Configure hardware reset for each peripheral according to NewState
  186. * @param[in] PPType Type of peripheral used to enable power,
  187. * should be one of the following:
  188. * - CLKPWR_RSTCON0_LCD : LCD
  189. * - CLKPWR_RSTCON0_TIM0 : Timer 0
  190. - CLKPWR_RSTCON0_TIM1 : Timer 1
  191. - CLKPWR_RSTCON0_UART0 : UART 0
  192. - CLKPWR_RSTCON0_UART1 : UART 1
  193. - CLKPWR_RSTCON0_PWM0 : PWM 0
  194. - CLKPWR_RSTCON0_PWM1 : PWM 1
  195. - CLKPWR_RSTCON0_I2C0 : I2C 0
  196. - CLKPWR_RSTCON0_UART4 : UART 4
  197. - CLKPWR_RSTCON0_RTC : RTC
  198. - CLKPWR_RSTCON0_SSP1 : SSP 1
  199. - CLKPWR_RSTCON0_EMC : EMC
  200. - CLKPWR_RSTCON0_ADC : ADC
  201. - CLKPWR_RSTCON0_CAN1 : CAN 1
  202. - CLKPWR_RSTCON0_CAN2 : CAN 2
  203. - CLKPWR_RSTCON0_GPIO : GPIO
  204. - CLKPWR_RSTCON0_MCPWM : MCPWM
  205. - CLKPWR_RSTCON0_QEI : QEI
  206. - CLKPWR_RSTCON0_I2C1 : I2C 1
  207. - CLKPWR_RSTCON0_SSP2 : SSP 2
  208. - CLKPWR_RSTCON0_SSP0 : SSP 0
  209. - CLKPWR_RSTCON0_TIM2 : Timer 2
  210. - CLKPWR_RSTCON0_TIM3 : Timer 3
  211. - CLKPWR_RSTCON0_UART2 : UART 2
  212. - CLKPWR_RSTCON0_UART3 : UART 3
  213. - CLKPWR_RSTCON0_I2C2 : I2C 2
  214. - CLKPWR_RSTCON0_I2S : I2S
  215. - CLKPWR_RSTCON0_SDC : SDC
  216. - CLKPWR_RSTCON0_GPDMA : GPDMA
  217. - CLKPWR_RSTCON0_ENET : Ethernet
  218. - CLKPWR_RSTCON0_USB : USB
  219. *
  220. * @param[in] NewState New state of Peripheral Power, should be:
  221. * - ENABLE : Enable power for this peripheral
  222. * - DISABLE : Disable power for this peripheral
  223. *
  224. * @return none
  225. **********************************************************************/
  226. void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
  227. {
  228. if(PType < 32)
  229. {
  230. if(NewState == ENABLE)
  231. LPC_SC->RSTCON0 |=(1<<PType);
  232. else
  233. LPC_SC->RSTCON0 &=~(1<<PType);
  234. }
  235. else
  236. {
  237. if(NewState == ENABLE)
  238. LPC_SC->RSTCON1 |= (1<<(PType - 31));
  239. else
  240. LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
  241. }
  242. }
  243. // nxp21346
  244. #endif
  245. /*********************************************************************//**
  246. * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
  247. * @param[in] None
  248. * @return None
  249. **********************************************************************/
  250. void CLKPWR_Sleep(void)
  251. {
  252. LPC_SC->PCON = 0x00;
  253. /* Sleep Mode*/
  254. __WFI();
  255. }
  256. /*********************************************************************//**
  257. * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
  258. * @param[in] None
  259. * @return None
  260. **********************************************************************/
  261. void CLKPWR_DeepSleep(void)
  262. {
  263. /* Deep-Sleep Mode, set SLEEPDEEP bit */
  264. SCB->SCR = 0x4;
  265. LPC_SC->PCON = 0x00;
  266. /* Deep Sleep Mode*/
  267. __WFI();
  268. }
  269. /*********************************************************************//**
  270. * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
  271. * @param[in] None
  272. * @return None
  273. **********************************************************************/
  274. void CLKPWR_PowerDown(void)
  275. {
  276. /* Deep-Sleep Mode, set SLEEPDEEP bit */
  277. SCB->SCR = 0x4;
  278. LPC_SC->PCON = 0x01;
  279. /* Power Down Mode*/
  280. __WFI();
  281. }
  282. /*********************************************************************//**
  283. * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
  284. * @param[in] None
  285. * @return None
  286. **********************************************************************/
  287. void CLKPWR_DeepPowerDown(void)
  288. {
  289. /* Deep-Sleep Mode, set SLEEPDEEP bit */
  290. SCB->SCR = 0x4;
  291. LPC_SC->PCON = 0x03;
  292. /* Deep Power Down Mode*/
  293. __WFI();
  294. }
  295. /**
  296. * @}
  297. */
  298. #endif /*_CLKPWR*/
  299. /**
  300. * @}
  301. */
  302. /* --------------------------------- End Of File ------------------------------ */