fsl_swo.c 4.1 KB

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  1. /*
  2. * The Clear BSD License
  3. * Copyright 2018 NXP
  4. * All rights reserved.
  5. *
  6. *
  7. * Redistribution and use in source and binary forms, with or without modification,
  8. * are permitted (subject to the limitations in the disclaimer below) provided
  9. * that the following conditions are met:
  10. *
  11. * o Redistributions of source code must retain the above copyright notice, this list
  12. * of conditions and the following disclaimer.
  13. *
  14. * o Redistributions in binary form must reproduce the above copyright notice, this
  15. * list of conditions and the following disclaimer in the documentation and/or
  16. * other materials provided with the distribution.
  17. *
  18. * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  23. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  24. * ANY EPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  27. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. *
  34. */
  35. #include "fsl_swo.h"
  36. /*******************************************************************************
  37. * Definitions
  38. ******************************************************************************/
  39. /* SWO encoding protocol definition */
  40. #ifndef FSL_DEBUG_CONSOLE_SWO_PROTOCOL
  41. #define FSL_DEBUG_CONSOLE_SWO_PROTOCOL kSWO_ProtocolNrz
  42. #endif
  43. /*******************************************************************************
  44. * Variables
  45. ******************************************************************************/
  46. /*******************************************************************************
  47. * Code
  48. ******************************************************************************/
  49. status_t SWO_Init(uint32_t port, uint32_t baudRate, uint32_t clkSrcFreq)
  50. {
  51. assert(baudRate <= clkSrcFreq);
  52. assert((clkSrcFreq / baudRate) <= TPI_ACPR_PRESCALER_Msk);
  53. assert((TPI->DEVID & (kSWO_ProtocolNrz | kSWO_ProtocolManchester)) != 0U);
  54. uint32_t prescaler = clkSrcFreq / baudRate - 1U;
  55. /* enable the ITM and DWT units */
  56. CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk;
  57. if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) == 0U)
  58. {
  59. return kStatus_Fail;
  60. }
  61. /* Lock access */
  62. ITM->LAR = 0xC5ACCE55U;
  63. /* Disable ITM */
  64. ITM->TER &= ~(1U << port);
  65. ITM->TCR = 0U;
  66. /* select SWO encoding protocol */
  67. TPI->SPPR = FSL_DEBUG_CONSOLE_SWO_PROTOCOL;
  68. /* select asynchronous clock prescaler */
  69. TPI->ACPR = prescaler & 0xFFFFU;
  70. /* allow unprivilege access */
  71. ITM->TPR = 0U;
  72. /* enable ITM */
  73. ITM->TCR =
  74. ITM_TCR_ITMENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_TraceBusID_Msk | ITM_TCR_SWOENA_Msk | ITM_TCR_DWTENA_Msk;
  75. /* enable the port bits */
  76. ITM->TER = 1U << port;
  77. return kStatus_Success;
  78. }
  79. void SWO_Deinit(uint32_t port)
  80. {
  81. /* disable ITM */
  82. ITM->TER &= ~(1U << port);
  83. }
  84. status_t SWO_SendBlocking(uint32_t port, uint8_t *ch, size_t size)
  85. {
  86. assert(ch != NULL);
  87. assert((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0U);
  88. assert((ITM->TER & (1U << port)) != 0U);
  89. uint16_t *strAddr = (uint16_t *)ch;
  90. while (size)
  91. {
  92. /* wait FIFO ready */
  93. while (ITM->PORT[port].u32 == 0U)
  94. {
  95. }
  96. if (size >= 2U)
  97. {
  98. size -= 2U;
  99. ITM->PORT[port].u16 = *strAddr;
  100. }
  101. else
  102. {
  103. size -= 1U;
  104. ITM->PORT[port].u8 = *((uint8_t *)strAddr);
  105. }
  106. strAddr++;
  107. }
  108. return kStatus_Success;
  109. }