ebi_reg.h 14 KB

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  1. /**************************************************************************//**
  2. * @file ebi_reg.h
  3. * @version V1.00
  4. * @brief EBI register definition header file
  5. *
  6. * SPDX-License-Identifier: Apache-2.0
  7. * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
  8. *****************************************************************************/
  9. #ifndef __EBI_REG_H__
  10. #define __EBI_REG_H__
  11. #if defined ( __CC_ARM )
  12. #pragma anon_unions
  13. #endif
  14. /**
  15. @addtogroup REGISTER Control Register
  16. @{
  17. */
  18. /**
  19. @addtogroup EBI External Bus Interface Controller(EBI)
  20. Memory Mapped Structure for EBI Controller
  21. @{ */
  22. typedef struct
  23. {
  24. /**
  25. * @var EBI_T::CTL0
  26. * Offset: 0x00 External Bus Interface Bank0 Control Register
  27. * ---------------------------------------------------------------------------------------------------
  28. * |Bits |Field |Descriptions
  29. * | :----: | :----: | :---- |
  30. * |[0] |EN |EBI Enable Bit
  31. * | | |This bit is the functional enable bit for EBI.
  32. * | | |0 = EBI function Disabled.
  33. * | | |1 = EBI function Enabled.
  34. * |[1] |DW16 |EBI Data Width 16-bit Select
  35. * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
  36. * | | |0 = EBI data width is 8-bit.
  37. * | | |1 = EBI data width is 16-bit.
  38. * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
  39. * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
  40. * | | |0 = Chip select pin (EBI_nCS) is active low.
  41. * | | |1 = Chip select pin (EBI_nCS) is active high.
  42. * |[4] |CACCESS |Continuous Data Access Mode
  43. * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
  44. * | | |0 = Continuous data access mode Disabled.
  45. * | | |1 = Continuous data access mode Enabled.
  46. * |[10:8] |MCLKDIV |External Output Clock Divider
  47. * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
  48. * | | |000 = HCLK/1.
  49. * | | |001 = HCLK/2.
  50. * | | |010 = HCLK/4.
  51. * | | |011 = HCLK/8.
  52. * | | |100 = HCLK/16.
  53. * | | |101 = HCLK/32.
  54. * | | |110 = HCLK/64.
  55. * | | |111 = HCLK/128.
  56. * |[18:16] |TALE |Extend Time Of of ALE
  57. * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
  58. * | | |tALE = (TALE + 1)*EBI_MCLK.
  59. * | | |Note: This field only available in EBI_CTL0 register.
  60. * |[24] |WBUFEN |EBI Write Buffer Enable Bit
  61. * | | |0 = EBI write buffer Disabled.
  62. * | | |1 = EBI write buffer Enabled.
  63. * | | |Note: This bit only available in EBI_CTL0 register.
  64. * @var EBI_T::TCTL0
  65. * Offset: 0x04 External Bus Interface Bank0 Timing Control Register
  66. * ---------------------------------------------------------------------------------------------------
  67. * |Bits |Field |Descriptions
  68. * | :----: | :----: | :---- |
  69. * |[7:3] |TACC |EBI Data Access Time
  70. * | | |TACC define data access time (tACC).
  71. * | | |tACC = (TACC + 1) * EBI_MCLK.
  72. * |[10:8] |TAHD |EBI Data Access Hold Time
  73. * | | |TAHD define data access hold time (tAHD).
  74. * | | |tAHD = (TAHD + 1) * EBI_MCLK.
  75. * |[15:12] |W2X |Idle Cycle After Write
  76. * | | |This field defines the number of W2X idle cycle.
  77. * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
  78. * | | |W2X idle cycle = (W2X * EBI_MCLK).
  79. * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
  80. * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
  81. * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
  82. * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
  83. * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
  84. * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
  85. * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
  86. * |[27:24] |R2R |Idle Cycle Between Read-to-read
  87. * | | |This field defines the number of R2R idle cycle.
  88. * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
  89. * | | |R2R idle cycle = (R2R * EBI_MCLK).
  90. * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
  91. * @var EBI_T::CTL1
  92. * Offset: 0x10 External Bus Interface Bank1 Control Register
  93. * ---------------------------------------------------------------------------------------------------
  94. * |Bits |Field |Descriptions
  95. * | :----: | :----: | :---- |
  96. * |[0] |EN |EBI Enable Bit
  97. * | | |This bit is the functional enable bit for EBI.
  98. * | | |0 = EBI function Disabled.
  99. * | | |1 = EBI function Enabled.
  100. * |[1] |DW16 |EBI Data Width 16-bit Select
  101. * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
  102. * | | |0 = EBI data width is 8-bit.
  103. * | | |1 = EBI data width is 16-bit.
  104. * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
  105. * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
  106. * | | |0 = Chip select pin (EBI_nCS) is active low.
  107. * | | |1 = Chip select pin (EBI_nCS) is active high.
  108. * |[4] |CACCESS |Continuous Data Access Mode
  109. * | | |When con ttinuousenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
  110. * | | |0 = Continuous data access mode Disabled.
  111. * | | |1 = Continuous data access mode Enabled.
  112. * |[10:8] |MCLKDIV |External Output Clock Divider
  113. * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
  114. * | | |000 = HCLK/1.
  115. * | | |001 = HCLK/2.
  116. * | | |010 = HCLK/4.
  117. * | | |011 = HCLK/8.
  118. * | | |100 = HCLK/16.
  119. * | | |101 = HCLK/32.
  120. * | | |110 = HCLK/64.
  121. * | | |111 = HCLK/128.
  122. * |[18:16] |TALE |Extend Time Of of ALE
  123. * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
  124. * | | |tALE = (TALE + 1)*EBI_MCLK.
  125. * | | |Note: This field only available in EBI_CTL0 register.
  126. * |[24] |WBUFEN |EBI Write Buffer Enable Bit
  127. * | | |0 = EBI write buffer Disabled.
  128. * | | |1 = EBI write buffer Enabled.
  129. * | | |Note: This bit only available in EBI_CTL0 register.
  130. * @var EBI_T::TCTL1
  131. * Offset: 0x14 External Bus Interface Bank1 Timing Control Register
  132. * ---------------------------------------------------------------------------------------------------
  133. * |Bits |Field |Descriptions
  134. * | :----: | :----: | :---- |
  135. * |[7:3] |TACC |EBI Data Access Time
  136. * | | |TACC define data access time (tACC).
  137. * | | |tACC = (TACC + 1) * EBI_MCLK.
  138. * |[10:8] |TAHD |EBI Data Access Hold Time
  139. * | | |TAHD define data access hold time (tAHD).
  140. * | | |tAHD = (TAHD + 1) * EBI_MCLK.
  141. * |[15:12] |W2X |Idle Cycle After Write
  142. * | | |This field defines the number of W2X idle cycle.
  143. * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
  144. * | | |W2X idle cycle = (W2X * EBI_MCLK).
  145. * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
  146. * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
  147. * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
  148. * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
  149. * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
  150. * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
  151. * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
  152. * |[27:24] |R2R |Idle Cycle Between Read-to-read
  153. * | | |This field defines the number of R2R idle cycle.
  154. * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
  155. * | | |R2R idle cycle = (R2R * EBI_MCLK).
  156. * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
  157. */
  158. __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
  159. __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
  160. __I uint32_t RESERVE0[2];
  161. __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
  162. __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
  163. } EBI_T;
  164. /**
  165. @addtogroup EBI_CONST EBI Bit Field Definition
  166. Constant Definitions for EBI Controller
  167. @{ */
  168. #define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
  169. #define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
  170. #define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
  171. #define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
  172. #define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
  173. #define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
  174. #define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
  175. #define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
  176. #define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
  177. #define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
  178. #define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
  179. #define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
  180. #define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
  181. #define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
  182. #define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
  183. #define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
  184. #define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
  185. #define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
  186. #define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
  187. #define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
  188. #define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
  189. #define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
  190. #define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
  191. #define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
  192. #define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
  193. #define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
  194. /**@}*/ /* EBI_CONST */
  195. /**@}*/ /* end of EBI register group */
  196. /**@}*/ /* end of REGISTER group */
  197. #if defined ( __CC_ARM )
  198. #pragma no_anon_unions
  199. #endif
  200. #endif /* __EBI_REG_H__ */