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nu_sys.h

nu_sys.h 120 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file     nu_sys.h
    3. 

  3.  * @version  V0.10
    4. 

  4.  * $Revision: 7 $
    5. 

  5.  * $Date: 19/06/10 2:48p $
    6. 

  6.  * @brief    M031 Series SYS Driver Header File
    7. 

  7.  *
    8. 

  8.  * @note
    9. 

  9.  * SPDX-License-Identifier: Apache-2.0
    10. 

  10.  * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
    11. 

  11.  *****************************************************************************/
    12. 

  12. #ifndef __NU_SYS_H__
    13. 

  13. #define __NU_SYS_H__
    14. 

  14. 

  15. #ifdef __cplusplus
    16. 

  16. extern "C"
    17. 

  17. {
    18. 

  18. #endif
    19. 

  19. 

  20. /** @addtogroup Standard_Driver Standard Driver
    21. 

  21.   @{
    22. 

  22. */
    23. 

  23. 

  24. /** @addtogroup SYS_Driver SYS Driver
    25. 

  25.   @{
    26. 

  26. */
    27. 

  27. 

  28. /** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
    29. 

  29.   @{
    30. 

  30. */
    31. 

  31. 

  32. /*---------------------------------------------------------------------------------------------------------*/
    33. 

  33. /*  Module Reset Control Resister constant definitions.                                                    */
    34. 

  34. /*---------------------------------------------------------------------------------------------------------*/
    35. 

  35. #define PDMA_RST    ((0x0<<24)|SYS_IPRST0_PDMARST_Pos)      /*!< PDMA  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    36. 

  36. #define EBI_RST     ((0x0<<24)|SYS_IPRST0_EBIRST_Pos)       /*!< EBI   reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    37. 

  37. #define HDIV_RST    ((0x0<<24)|SYS_IPRST0_HDIVRST_Pos)      /*!< HDIV  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    38. 

  38. #define CRC_RST     ((0x0<<24)|SYS_IPRST0_CRCRST_Pos)       /*!< CRC   reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    39. 

  39. 

  40. #define GPIO_RST    ((0x4<<24)|SYS_IPRST1_GPIORST_Pos)      /*!< GPIO  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    41. 

  41. #define TMR0_RST    ((0x4<<24)|SYS_IPRST1_TMR0RST_Pos)      /*!< TMR0  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    42. 

  42. #define TMR1_RST    ((0x4<<24)|SYS_IPRST1_TMR1RST_Pos)      /*!< TMR1  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    43. 

  43. #define TMR2_RST    ((0x4<<24)|SYS_IPRST1_TMR2RST_Pos)      /*!< TMR2  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    44. 

  44. #define TMR3_RST    ((0x4<<24)|SYS_IPRST1_TMR3RST_Pos)      /*!< TMR3  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    45. 

  45. #define ACMP01_RST  ((0x4<<24)|SYS_IPRST1_ACMP01RST_Pos)    /*!< ACMP  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    46. 

  46. #define I2C0_RST    ((0x4<<24)|SYS_IPRST1_I2C0RST_Pos)      /*!< I2C0  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    47. 

  47. #define I2C1_RST    ((0x4<<24)|SYS_IPRST1_I2C1RST_Pos)      /*!< I2C1  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    48. 

  48. #define QSPI0_RST   ((0x4<<24)|SYS_IPRST1_QSPI0RST_Pos)     /*!< QSPI0 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    49. 

  49. #define SPI0_RST    ((0x4<<24)|SYS_IPRST1_SPI0RST_Pos)      /*!< SPI0  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    50. 

  50. #define UART0_RST   ((0x4<<24)|SYS_IPRST1_UART0RST_Pos)     /*!< UART0 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    51. 

  51. #define UART1_RST   ((0x4<<24)|SYS_IPRST1_UART1RST_Pos)     /*!< UART1 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    52. 

  52. #define UART2_RST   ((0x4<<24)|SYS_IPRST1_UART2RST_Pos)     /*!< UART2 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    53. 

  53. #define UART3_RST   ((0x4<<24)|SYS_IPRST1_UART3RST_Pos)     /*!< UART3 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    54. 

  54. #define UART4_RST   ((0x4<<24)|SYS_IPRST1_UART4RST_Pos)     /*!< UART4 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    55. 

  55. #define UART5_RST   ((0x4<<24)|SYS_IPRST1_UART5RST_Pos)     /*!< UART5 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    56. 

  56. #define UART6_RST   ((0x4<<24)|SYS_IPRST1_UART6RST_Pos)     /*!< UART6 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    57. 

  57. #define UART7_RST   ((0x4<<24)|SYS_IPRST1_UART7RST_Pos)     /*!< UART7 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    58. 

  58. #define USBD_RST    ((0x4<<24)|SYS_IPRST1_USBDRST_Pos)      /*!< USBD  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    59. 

  59. #define ADC_RST     ((0x4<<24)|SYS_IPRST1_ADCRST_Pos)       /*!< ADC   reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    60. 

  60. 

  61. #define USCI0_RST   ((0x8<<24)|SYS_IPRST2_USCI0RST_Pos)     /*!< USCI0 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    62. 

  62. #define USCI1_RST   ((0x8<<24)|SYS_IPRST2_USCI1RST_Pos)     /*!< USCI1 reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    63. 

  63. #define PWM0_RST    ((0x8<<24)|SYS_IPRST2_PWM0RST_Pos)      /*!< PWM0  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    64. 

  64. #define PWM1_RST    ((0x8<<24)|SYS_IPRST2_PWM1RST_Pos)      /*!< PWM1  reset is one of the \ref SYS_ResetModule parameter   \hideinitializer */
    65. 

  65. #define BPWM0_RST   ((0x8<<24)|SYS_IPRST2_BPWM0RST_Pos)     /*!< BPWM0  reset is one of the \ref SYS_ResetModule parameter  \hideinitializer */
    66. 

  66. #define BPWM1_RST   ((0x8<<24)|SYS_IPRST2_BPWM1RST_Pos)     /*!< BPWM1  reset is one of the \ref SYS_ResetModule parameter  \hideinitializer */
    67. 

  67. 

  68. /*---------------------------------------------------------------------------------------------------------*/
    69. 

  69. /*  Brown Out Detector Threshold Voltage Selection constant definitions.                                   */
    70. 

  70. /*---------------------------------------------------------------------------------------------------------*/
    71. 

  71. #define SYS_BODCTL_BOD_RST_EN           (1UL<<SYS_BODCTL_BODRSTEN_Pos)          /*!< Brown-out Reset Enable     \hideinitializer */
    72. 

  72. #define SYS_BODCTL_BOD_INTERRUPT_EN     (0UL<<SYS_BODCTL_BODRSTEN_Pos)          /*!< Brown-out Interrupt Enable \hideinitializer */
    73. 

  73. 

  74. #define SYS_BODCTL_BODVL_2_5V           (0x1UL<<SYS_BODCTL_BODVL_Pos)           /*!< Setting Brown Out Detector Threshold Voltage as 2.5V   \hideinitializer */
    75. 

  75. #define SYS_BODCTL_BODVL_2_0V           (0x0UL<<SYS_BODCTL_BODVL_Pos)           /*!< Setting Brown Out Detector Threshold Voltage as 2.0V   \hideinitializer */
    76. 

  76. 

  77. #define SYS_BODCTL_LVRDGSEL_0HCLK       (0x0UL<<SYS_BODCTL_LVRDGSEL_Pos)        /*!< LVR Output De-glitch Time Without de-glitch function.  \hideinitializer */
    78. 

  78. #define SYS_BODCTL_LVRDGSEL_64HCLK      (0x1UL<<SYS_BODCTL_LVRDGSEL_Pos)        /*!< LVR Output De-glitch Time is selected 64HCLK           \hideinitializer */
    79. 

  79. #define SYS_BODCTL_LVRDGSEL_128HCLK     (0x2UL<<SYS_BODCTL_LVRDGSEL_Pos)        /*!< LVR Output De-glitch Time is selected 128HCLK          \hideinitializer */
    80. 

  80. #define SYS_BODCTL_LVRDGSEL_256HCLK     (0x3UL<<SYS_BODCTL_LVRDGSEL_Pos)        /*!< LVR Output De-glitch Time is selected 256HCLK          \hideinitializer */
    81. 

  81. #define SYS_BODCTL_LVRDGSEL_512HCLK     (0x4UL<<SYS_BODCTL_LVRDGSEL_Pos)        /*!< LVR Output De-glitch Time is selected 512HCLK          \hideinitializer */
    82. 

  82. #define SYS_BODCTL_LVRDGSEL_1024HCLK    (0x5UL<<SYS_BODCTL_LVRDGSEL_Pos)        /*!< LVR Output De-glitch Time is selected 1024HCLK         \hideinitializer */
    83. 

  83. #define SYS_BODCTL_LVRDGSEL_2048HCLK    (0x6UL<<SYS_BODCTL_LVRDGSEL_Pos)        /*!< LVR Output De-glitch Time is selected 2048HCLK         \hideinitializer */
    84. 

  84. #define SYS_BODCTL_LVRDGSEL_4096HCLK    (0x7UL<<SYS_BODCTL_LVRDGSEL_Pos)        /*!< LVR Output De-glitch Time is selected 4096HCLK         \hideinitializer */
    85. 

  85. 

  86. #define SYS_BODCTL_BODDGSEL_0HCLK       (0x0UL<<SYS_BODCTL_BODDGSEL_Pos)        /*!< BOD Output De-glitch Time is sampled by RC10K clock.   \hideinitializer */
    87. 

  87. #define SYS_BODCTL_BODDGSEL_64HCLK      (0x1UL<<SYS_BODCTL_BODDGSEL_Pos)        /*!< BOD Output De-glitch Time is selected 64HCLK           \hideinitializer */
    88. 

  88. #define SYS_BODCTL_BODDGSEL_128HCLK     (0x2UL<<SYS_BODCTL_BODDGSEL_Pos)        /*!< BOD Output De-glitch Time is selected 128HCLK          \hideinitializer */
    89. 

  89. #define SYS_BODCTL_BODDGSEL_256HCLK     (0x3UL<<SYS_BODCTL_BODDGSEL_Pos)        /*!< BOD Output De-glitch Time is selected 256HCLK          \hideinitializer */
    90. 

  90. #define SYS_BODCTL_BODDGSEL_512HCLK     (0x4UL<<SYS_BODCTL_BODDGSEL_Pos)        /*!< BOD Output De-glitch Time is selected 512HCLK          \hideinitializer */
    91. 

  91. #define SYS_BODCTL_BODDGSEL_1024HCLK    (0x5UL<<SYS_BODCTL_BODDGSEL_Pos)        /*!< BOD Output De-glitch Time is selected 1024HCLK         \hideinitializer */
    92. 

  92. #define SYS_BODCTL_BODDGSEL_2048HCLK    (0x6UL<<SYS_BODCTL_BODDGSEL_Pos)        /*!< BOD Output De-glitch Time is selected 2048HCLK         \hideinitializer */
    93. 

  93. #define SYS_BODCTL_BODDGSEL_4096HCLK    (0x7UL<<SYS_BODCTL_BODDGSEL_Pos)        /*!< BOD Output De-glitch Time is selected 4096HCLK         \hideinitializer */
    94. 

  94. 

  95. /*---------------------------------------------------------------------------------------------------------*/
    96. 

  96. /*  Multi-Function constant definitions.                                                                   */
    97. 

  97. /*---------------------------------------------------------------------------------------------------------*/
    98. 

  98. 

  99. /* How to use below #define?
    100. 

  100. 

  101. Example: If user want to set PD.3 as UART0_TXD and PD.2 as UART0_RXD in initial function,
    102. 

  102.          user can issue following command to achieve it.
    103. 

  103. 

  104.          SYS->GPD_MFPL = (SYS->GPD_MFPL & ~SYS_GPD_MFPL_PD2MFP_Msk) | SYS_GPD_MFPL_PD2MFP_UART0_RXD;
    105. 

  105.          SYS->GPD_MFPL = (SYS->GPD_MFPL & ~SYS_GPD_MFPL_PD3MFP_Msk) | SYS_GPD_MFPL_PD3MFP_UART0_TXD;
    106. 

  106. */
    107. 

  107. /* PA.0 MFP */
    108. 

  108. #define SYS_GPA_MFPL_PA0MFP_GPIO         (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO        \hideinitializer */
    109. 

  109. #define SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0  (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for QSPI0_MOSI0 \hideinitializer */
    110. 

  110. #define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI    (0x04UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SPI0_MOSI   \hideinitializer */
    111. 

  111. #define SYS_GPA_MFPL_PA0MFP_UART0_RXD    (0x07UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART0_RXD   \hideinitializer */
    112. 

  112. #define SYS_GPA_MFPL_PA0MFP_UART1_nRTS   (0x08UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_nRTS  \hideinitializer */
    113. 

  113. #define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0    (0x0CUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for BPWM0_CH0   \hideinitializer */
    114. 

  114. #define SYS_GPA_MFPL_PA0MFP_PWM0_CH5     (0x0DUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for PWM0_CH5    \hideinitializer */
    115. 

  115. 

  116. /* PA.1 MFP */
    117. 

  117. #define SYS_GPA_MFPL_PA1MFP_GPIO         (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO        \hideinitializer */
    118. 

  118. #define SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0  (0x03UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for QSPI0_MISO0 \hideinitializer */
    119. 

  119. #define SYS_GPA_MFPL_PA1MFP_SPI0_MISO    (0x04UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SPI0_MISO   \hideinitializer */
    120. 

  120. #define SYS_GPA_MFPL_PA1MFP_UART0_TXD    (0x07UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART0_TXD   \hideinitializer */
    121. 

  121. #define SYS_GPA_MFPL_PA1MFP_UART1_nCTS   (0x08UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_nCTS  \hideinitializer */
    122. 

  122. #define SYS_GPA_MFPL_PA1MFP_USCI1_CLK    (0x0BUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for USCI1_CLK   \hideinitializer */
    123. 

  123. #define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1    (0x0CUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for BPWM0_CH1   \hideinitializer */
    124. 

  124. #define SYS_GPA_MFPL_PA1MFP_PWM0_CH4     (0x0DUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for PWM0_CH4    \hideinitializer */
    125. 

  125. 

  126. /* PA.2 MFP */
    127. 

  127. #define SYS_GPA_MFPL_PA2MFP_GPIO         (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO        \hideinitializer */
    128. 

  128. #define SYS_GPA_MFPL_PA2MFP_QSPI0_CLK    (0x03UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for QSPI0_CLK   \hideinitializer */
    129. 

  129. #define SYS_GPA_MFPL_PA2MFP_SPI0_CLK     (0x04UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SPI0_CLK    \hideinitializer */
    130. 

  130. #define SYS_GPA_MFPL_PA2MFP_UART4_RXD    (0x05UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART4_RXD   \hideinitializer */
    131. 

  131. #define SYS_GPA_MFPL_PA2MFP_I2C0_SMBSUS  (0x07UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C0_SMBSUS \hideinitializer */
    132. 

  132. #define SYS_GPA_MFPL_PA2MFP_UART1_RXD    (0x08UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART1_RXD   \hideinitializer */
    133. 

  133. #define SYS_GPA_MFPL_PA2MFP_I2C1_SDA     (0x09UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C1_SDA    \hideinitializer */
    134. 

  134. #define SYS_GPA_MFPL_PA2MFP_USCI1_DAT0   (0x0BUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for USCI1_DAT0  \hideinitializer */
    135. 

  135. #define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2    (0x0CUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for BPWM0_CH2   \hideinitializer */
    136. 

  136. #define SYS_GPA_MFPL_PA2MFP_PWM0_CH3     (0x0DUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for PWM0_CH3    \hideinitializer */
    137. 

  137. 

  138. /* PA.3 MFP */
    139. 

  139. #define SYS_GPA_MFPL_PA3MFP_GPIO         (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO        \hideinitializer */
    140. 

  140. #define SYS_GPA_MFPL_PA3MFP_QSPI0_SS     (0x03UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for QSPI0_SS    \hideinitializer */
    141. 

  141. #define SYS_GPA_MFPL_PA3MFP_SPI0_SS      (0x04UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SPI0_SS     \hideinitializer */
    142. 

  142. #define SYS_GPA_MFPL_PA3MFP_UART4_TXD    (0x05UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART4_TXD   \hideinitializer */
    143. 

  143. #define SYS_GPA_MFPL_PA3MFP_I2C0_SMBAL   (0x07UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C0_SMBAL  \hideinitializer */
    144. 

  144. #define SYS_GPA_MFPL_PA3MFP_UART1_TXD    (0x08UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART1_TXD   \hideinitializer */
    145. 

  145. #define SYS_GPA_MFPL_PA3MFP_I2C1_SCL     (0x09UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C1_SCL    \hideinitializer */
    146. 

  146. #define SYS_GPA_MFPL_PA3MFP_USCI1_DAT1   (0x0BUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for USCI1_DAT1  \hideinitializer */
    147. 

  147. #define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3    (0x0CUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for BPWM0_CH3   \hideinitializer */
    148. 

  148. #define SYS_GPA_MFPL_PA3MFP_PWM0_CH2     (0x0DUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for PWM0_CH2    \hideinitializer */
    149. 

  149. #define SYS_GPA_MFPL_PA3MFP_CLKO         (0x0EUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPB_MFPL PA3 setting for CLKO        \hideinitializer */
    150. 

  150. #define SYS_GPA_MFPL_PA3MFP_PWM1_BRAKE1  (0x0FUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for PWM1_BRAKE1 \hideinitializer */
    151. 

  151. 

  152. /* PA.4 MFP */
    153. 

  153. #define SYS_GPA_MFPL_PA4MFP_GPIO         (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO           \hideinitializer */
    154. 

  154. #define SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1  (0x03UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for QSPI0_MOSI1    \hideinitializer */
    155. 

  155. #define SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI0_I2SMCLK   \hideinitializer */
    156. 

  156. #define SYS_GPA_MFPL_PA4MFP_UART0_nRTS   (0x07UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART0_nRTS     \hideinitializer */
    157. 

  157. #define SYS_GPA_MFPL_PA4MFP_UART0_RXD    (0x08UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART0_RXD      \hideinitializer */
    158. 

  158. #define SYS_GPA_MFPL_PA4MFP_I2C0_SDA     (0x09UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for I2C0_SDA       \hideinitializer */
    159. 

  159. #define SYS_GPA_MFPL_PA4MFP_UART5_RXD    (0x0BUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART5_RXD      \hideinitializer */
    160. 

  160. #define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4    (0x0CUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for BPWM0_CH4      \hideinitializer */
    161. 

  161. #define SYS_GPA_MFPL_PA4MFP_PWM0_CH1     (0x0DUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for PWM0_CH1       \hideinitializer */
    162. 

  162. 

  163. /* PA.5 MFP */
    164. 

  164. #define SYS_GPA_MFPL_PA5MFP_GPIO         (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO        \hideinitializer */
    165. 

  165. #define SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1  (0x03UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for QSPI0_MISO1 \hideinitializer */
    166. 

  166. #define SYS_GPA_MFPL_PA5MFP_UART0_nCTS   (0x07UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART0_nCTS  \hideinitializer */
    167. 

  167. #define SYS_GPA_MFPL_PA5MFP_UART0_TXD    (0x08UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART0_TXD   \hideinitializer */
    168. 

  168. #define SYS_GPA_MFPL_PA5MFP_I2C0_SCL     (0x09UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for I2C0_SCL    \hideinitializer */
    169. 

  169. #define SYS_GPA_MFPL_PA5MFP_UART5_TXD    (0x0BUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART5_TXD   \hideinitializer */
    170. 

  170. #define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5    (0x0CUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for BPWM0_CH5   \hideinitializer */
    171. 

  171. #define SYS_GPA_MFPL_PA5MFP_PWM0_CH0     (0x0DUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for PWM0_CH0    \hideinitializer */
    172. 

  172. 

  173. /* PA.6 MFP */
    174. 

  174. #define SYS_GPA_MFPL_PA6MFP_GPIO         (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO        \hideinitializer */
    175. 

  175. #define SYS_GPA_MFPL_PA6MFP_EBI_AD6      (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_AD6     \hideinitializer */
    176. 

  176. #define SYS_GPA_MFPL_PA6MFP_UART0_RXD    (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for UART0_RXD   \hideinitializer */
    177. 

  177. #define SYS_GPA_MFPL_PA6MFP_I2C1_SDA     (0x08UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for I2C1_SDA    \hideinitializer */
    178. 

  178. #define SYS_GPA_MFPL_PA6MFP_PWM1_CH5     (0x0BUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for PWM1_CH5    \hideinitializer */
    179. 

  179. #define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3    (0x0CUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for BPWM1_CH3   \hideinitializer */
    180. 

  180. #define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT   (0x0DUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for ACMP1_WLAT  \hideinitializer */
    181. 

  181. #define SYS_GPA_MFPL_PA6MFP_TM3          (0x0EUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for TM3         \hideinitializer */
    182. 

  182. #define SYS_GPA_MFPL_PA6MFP_INT0         (0x0FUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for INT0        \hideinitializer */
    183. 

  183. 

  184. /* PA.7 MFP */
    185. 

  185. #define SYS_GPA_MFPL_PA7MFP_GPIO         (0x00UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO        \hideinitializer */
    186. 

  186. #define SYS_GPA_MFPL_PA7MFP_EBI_AD7      (0x02UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_AD7     \hideinitializer */
    187. 

  187. #define SYS_GPA_MFPL_PA7MFP_UART0_TXD    (0x07UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for UART0_TXD   \hideinitializer */
    188. 

  188. #define SYS_GPA_MFPL_PA7MFP_I2C1_SCL     (0x08UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for I2C1_SCL    \hideinitializer */
    189. 

  189. #define SYS_GPA_MFPL_PA7MFP_PWM1_CH4     (0x0BUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for PWM1_CH4    \hideinitializer */
    190. 

  190. #define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2    (0x0CUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for BPWM1_CH2   \hideinitializer */
    191. 

  191. #define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT   (0x0DUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for ACMP0_WLAT  \hideinitializer */
    192. 

  192. #define SYS_GPA_MFPL_PA7MFP_TM2          (0x0EUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for TM2         \hideinitializer */
    193. 

  193. #define SYS_GPA_MFPL_PA7MFP_INT1         (0x0FUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for INT1        \hideinitializer */
    194. 

  194. 

  195. /* PA.8 MFP */
    196. 

  196. #define SYS_GPA_MFPH_PA8MFP_GPIO         (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO        \hideinitializer */
    197. 

  197. #define SYS_GPA_MFPH_PA8MFP_EBI_ALE      (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for EBI_ALE     \hideinitializer */
    198. 

  198. #define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1   (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for USCI0_CTL1  \hideinitializer */
    199. 

  199. #define SYS_GPA_MFPH_PA8MFP_UART1_RXD    (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for UART1_RXD   \hideinitializer */
    200. 

  200. #define SYS_GPA_MFPH_PA8MFP_UART7_RXD    (0x08UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for UART7_RXD   \hideinitializer */
    201. 

  201. #define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3    (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for BPWM0_CH3   \hideinitializer */
    202. 

  202. #define SYS_GPA_MFPH_PA8MFP_TM3_EXT      (0x0DUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for TM3_EXT     \hideinitializer */
    203. 

  203. #define SYS_GPA_MFPH_PA8MFP_INT4         (0x0FUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for INT4        \hideinitializer */
    204. 

  204. 

  205. /* PA.9 MFP */
    206. 

  206. #define SYS_GPA_MFPH_PA9MFP_GPIO         (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO        \hideinitializer */
    207. 

  207. #define SYS_GPA_MFPH_PA9MFP_EBI_MCLK     (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for EBI_MCLK    \hideinitializer */
    208. 

  208. #define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1   (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for USCI0_DAT1  \hideinitializer */
    209. 

  209. #define SYS_GPA_MFPH_PA9MFP_UART1_TXD    (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for UART1_TXD   \hideinitializer */
    210. 

  210. #define SYS_GPA_MFPH_PA9MFP_UART7_TXD    (0x08UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for UART7_TXD   \hideinitializer */
    211. 

  211. #define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2    (0x09UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for BPWM0_CH2   \hideinitializer */
    212. 

  212. #define SYS_GPA_MFPH_PA9MFP_TM2_EXT      (0x0DUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for TM2_EXT     \hideinitializer */
    213. 

  213. 

  214. /* PA.10 MFP */
    215. 

  215. #define SYS_GPA_MFPH_PA10MFP_GPIO        (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for GPIO       \hideinitializer */
    216. 

  216. #define SYS_GPA_MFPH_PA10MFP_ACMP1_P0    (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for ACMP1_P0   \hideinitializer */
    217. 

  217. #define SYS_GPA_MFPH_PA10MFP_EBI_nWR     (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for EBI_nWR    \hideinitializer */
    218. 

  218. #define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0  (0x06UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for USCI0_DAT0 \hideinitializer */
    219. 

  219. #define SYS_GPA_MFPH_PA10MFP_UART6_RXD   (0x08UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for UART6_RXD  \hideinitializer */
    220. 

  220. #define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1   (0x09UL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for BPWM0_CH1  \hideinitializer */
    221. 

  221. #define SYS_GPA_MFPH_PA10MFP_TM1_EXT     (0x0DUL<<SYS_GPA_MFPH_PA10MFP_Pos)/*!< GPA_MFPH PA10 setting for TM1_EXT    \hideinitializer */
    222. 

  222. 

  223. /* PA.11 MFP */
    224. 

  224. #define SYS_GPA_MFPH_PA11MFP_GPIO        (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for GPIO       \hideinitializer */
    225. 

  225. #define SYS_GPA_MFPH_PA11MFP_ACMP0_P0    (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for ACMP0_P0   \hideinitializer */
    226. 

  226. #define SYS_GPA_MFPH_PA11MFP_EBI_nRD     (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for EBI_nRD    \hideinitializer */
    227. 

  227. #define SYS_GPA_MFPH_PA11MFP_USCI0_CLK   (0x06UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for USCI0_CLK  \hideinitializer */
    228. 

  228. #define SYS_GPA_MFPH_PA11MFP_UART6_TXD   (0x08UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for UART6_TXD  \hideinitializer */
    229. 

  229. #define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0   (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for BPWM0_CH0  \hideinitializer */
    230. 

  230. #define SYS_GPA_MFPH_PA11MFP_TM0_EXT     (0x0DUL<<SYS_GPA_MFPH_PA11MFP_Pos)/*!< GPA_MFPH PA11 setting for TM0_EXT    \hideinitializer */
    231. 

  231. 

  232. /* PA.12 MFP */
    233. 

  233. #define SYS_GPA_MFPH_PA12MFP_GPIO        (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for GPIO       \hideinitializer */
    234. 

  234. #define SYS_GPA_MFPH_PA12MFP_UART4_TXD   (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for UART4_TXD  \hideinitializer */
    235. 

  235. #define SYS_GPA_MFPH_PA12MFP_I2C1_SCL    (0x04UL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for I2C1_SCL   \hideinitializer */
    236. 

  236. #define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2   (0x0BUL<<SYS_GPA_MFPH_PA12MFP_Pos)/*!< GPA_MFPH PA12 setting for BPWM1_CH2  \hideinitializer */
    237. 

  237. 

  238. /* PA.13 MFP */
    239. 

  239. #define SYS_GPA_MFPH_PA13MFP_GPIO        (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for GPIO       \hideinitializer */
    240. 

  240. #define SYS_GPA_MFPH_PA13MFP_UART4_RXD   (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for UART4_RXD  \hideinitializer */
    241. 

  241. #define SYS_GPA_MFPH_PA13MFP_I2C1_SDA    (0x04UL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for I2C1_SDA   \hideinitializer */
    242. 

  242. #define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3   (0x0BUL<<SYS_GPA_MFPH_PA13MFP_Pos)/*!< GPA_MFPH PA13 setting for BPWM1_CH3  \hideinitializer */
    243. 

  243. 

  244. /* PA.14 MFP */
    245. 

  245. #define SYS_GPA_MFPH_PA14MFP_GPIO        (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for GPIO       \hideinitializer */
    246. 

  246. #define SYS_GPA_MFPH_PA14MFP_UART0_TXD   (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for UART0_TXD  \hideinitializer */
    247. 

  247. #define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4   (0x0BUL<<SYS_GPA_MFPH_PA14MFP_Pos)/*!< GPA_MFPH PA14 setting for BPWM1_CH4  \hideinitializer */
    248. 

  248. 

  249. /* PA.15 MFP */
    250. 

  250. #define SYS_GPA_MFPH_PA15MFP_GPIO        (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for GPIO       \hideinitializer */
    251. 

  251. #define SYS_GPA_MFPH_PA15MFP_UART0_RXD   (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for UART0_RXD  \hideinitializer */
    252. 

  252. #define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5   (0x0BUL<<SYS_GPA_MFPH_PA15MFP_Pos)/*!< GPA_MFPH PA15 setting for BPWM1_CH5  \hideinitializer */
    253. 

  253. 

  254. /* PB.0 MFP */
    255. 

  255. #define SYS_GPB_MFPL_PB0MFP_GPIO         (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO           \hideinitializer */
    256. 

  256. #define SYS_GPB_MFPL_PB0MFP_ADC_CH0      (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for ADC_CH0        \hideinitializer */
    257. 

  257. #define SYS_GPB_MFPL_PB0MFP_ADC0_CH0     (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for ADC0_CH0       \hideinitializer */
    258. 

  258. #define SYS_GPB_MFPL_PB0MFP_EBI_ADR9     (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_ADR9       \hideinitializer */
    259. 

  259. #define SYS_GPB_MFPL_PB0MFP_UART2_RXD    (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD      \hideinitializer */
    260. 

  260. #define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_I2SMCLK   \hideinitializer */
    261. 

  261. #define SYS_GPB_MFPL_PB0MFP_I2C1_SDA     (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for I2C1_SDA       \hideinitializer */
    262. 

  262. #define SYS_GPB_MFPL_PB0MFP_QSPI0_MOSI1  (0x0AUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for QSPI0_MOSI1    \hideinitializer */
    263. 

  263. #define SYS_GPB_MFPL_PB0MFP_PWM0_CH5     (0x0BUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for PWM0_CH5       \hideinitializer */
    264. 

  264. #define SYS_GPB_MFPL_PB0MFP_PWM1_CH5     (0x0CUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for PWM1_CH5       \hideinitializer */
    265. 

  265. #define SYS_GPB_MFPL_PB0MFP_PWM0_BRAKE1  (0x0DUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for PWM0_BRAKE1    \hideinitializer */
    266. 

  266. 

  267. /* PB.1 MFP */
    268. 

  268. #define SYS_GPB_MFPL_PB1MFP_GPIO         (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO        \hideinitializer */
    269. 

  269. #define SYS_GPB_MFPL_PB1MFP_ADC_CH1      (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for ADC_CH1     \hideinitializer */
    270. 

  270. #define SYS_GPB_MFPL_PB1MFP_ADC0_CH1     (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for ADC0_CH1    \hideinitializer */
    271. 

  271. #define SYS_GPB_MFPL_PB1MFP_EBI_ADR8     (0x02UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EBI_ADR8    \hideinitializer */
    272. 

  272. #define SYS_GPB_MFPL_PB1MFP_UART2_TXD    (0x07UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for UART2_TXD   \hideinitializer */
    273. 

  273. #define SYS_GPB_MFPL_PB1MFP_USCI1_CLK    (0x08UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for USCI1_CLK   \hideinitializer */
    274. 

  274. #define SYS_GPB_MFPL_PB1MFP_I2C1_SCL     (0x09UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for I2C1_SCL    \hideinitializer */
    275. 

  275. #define SYS_GPB_MFPL_PB1MFP_QSPI0_MISO1  (0x0AUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for QSPI0_MISO1 \hideinitializer */
    276. 

  276. #define SYS_GPB_MFPL_PB1MFP_PWM0_CH4     (0x0BUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for PWM0_CH4    \hideinitializer */
    277. 

  277. #define SYS_GPB_MFPL_PB1MFP_PWM1_CH4     (0x0CUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for PWM1_CH4    \hideinitializer */
    278. 

  278. #define SYS_GPB_MFPL_PB1MFP_PWM0_BRAKE0  (0x0DUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for PWM0_BRAKE0 \hideinitializer */
    279. 

  279. 

  280. /* PB.2 MFP */
    281. 

  281. #define SYS_GPB_MFPL_PB2MFP_GPIO         (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO        \hideinitializer */
    282. 

  282. #define SYS_GPB_MFPL_PB2MFP_ADC_CH2      (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for ADC_CH2     \hideinitializer */
    283. 

  283. #define SYS_GPB_MFPL_PB2MFP_ADC0_CH2     (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for ADC0_CH2    \hideinitializer */
    284. 

  284. #define SYS_GPB_MFPL_PB2MFP_ACMP0_P1     (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for ACMP0_P1    \hideinitializer */
    285. 

  285. #define SYS_GPB_MFPL_PB2MFP_EBI_ADR3     (0x02UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EBI_ADR3    \hideinitializer */
    286. 

  286. #define SYS_GPB_MFPL_PB2MFP_I2C1_SDA     (0x04UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for I2C1_SDA    \hideinitializer */
    287. 

  287. #define SYS_GPB_MFPL_PB2MFP_UART1_RXD    (0x06UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD   \hideinitializer */
    288. 

  288. #define SYS_GPB_MFPL_PB2MFP_UART5_nCTS   (0x07UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART5_nCTS  \hideinitializer */
    289. 

  289. #define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0   (0x08UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for USCI1_DAT0  \hideinitializer */
    290. 

  290. #define SYS_GPB_MFPL_PB2MFP_PWM0_CH3     (0x0BUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for PWM0_CH3    \hideinitializer */
    291. 

  291. #define SYS_GPB_MFPL_PB2MFP_TM3          (0x0EUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for TM3         \hideinitializer */
    292. 

  292. #define SYS_GPB_MFPL_PB2MFP_INT3         (0x0FUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for INT3        \hideinitializer */
    293. 

  293. 

  294. /* PB.3 MFP */
    295. 

  295. #define SYS_GPB_MFPL_PB3MFP_GPIO         (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO        \hideinitializer */
    296. 

  296. #define SYS_GPB_MFPL_PB3MFP_ADC_CH3      (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for ADC_CH3     \hideinitializer */
    297. 

  297. #define SYS_GPB_MFPL_PB3MFP_ADC0_CH3     (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for ADC0_CH3    \hideinitializer */
    298. 

  298. #define SYS_GPB_MFPL_PB3MFP_ACMP0_N      (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for ACMP0_N     \hideinitializer */
    299. 

  299. #define SYS_GPB_MFPL_PB3MFP_EBI_ADR2     (0x02UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EBI_ADR2    \hideinitializer */
    300. 

  300. #define SYS_GPB_MFPL_PB3MFP_I2C1_SCL     (0x04UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for I2C1_SCL    \hideinitializer */
    301. 

  301. #define SYS_GPB_MFPL_PB3MFP_UART1_TXD    (0x06UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD   \hideinitializer */
    302. 

  302. #define SYS_GPB_MFPL_PB3MFP_UART5_nRTS   (0x07UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART5_nRTS  \hideinitializer */
    303. 

  303. #define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1   (0x08UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for USCI1_DAT1  \hideinitializer */
    304. 

  304. #define SYS_GPB_MFPL_PB3MFP_PWM0_CH2     (0x0BUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for PWM0_CH2    \hideinitializer */
    305. 

  305. #define SYS_GPB_MFPL_PB3MFP_PWM0_BRAKE0  (0x0DUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for PWM0_BRAKE0 \hideinitializer */
    306. 

  306. #define SYS_GPB_MFPL_PB3MFP_TM2          (0x0EUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for TM2         \hideinitializer */
    307. 

  307. #define SYS_GPB_MFPL_PB3MFP_INT2         (0x0FUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for INT2        \hideinitializer */
    308. 

  308. 

  309. /* PB.4 MFP */
    310. 

  310. #define SYS_GPB_MFPL_PB4MFP_GPIO         (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO        \hideinitializer */
    311. 

  311. #define SYS_GPB_MFPL_PB4MFP_ADC_CH4      (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ADC_CH4     \hideinitializer */
    312. 

  312. #define SYS_GPB_MFPL_PB4MFP_ADC0_CH4     (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ADC0_CH4    \hideinitializer */
    313. 

  313. #define SYS_GPB_MFPL_PB4MFP_ACMP1_P1     (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ACMP1_P1    \hideinitializer */
    314. 

  314. #define SYS_GPB_MFPL_PB4MFP_EBI_ADR1     (0x02UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_ADR1    \hideinitializer */
    315. 

  315. #define SYS_GPB_MFPL_PB4MFP_I2C0_SDA     (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for I2C0_SDA    \hideinitializer */
    316. 

  316. #define SYS_GPB_MFPL_PB4MFP_UART5_RXD    (0x07UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART5_RXD   \hideinitializer */
    317. 

  317. #define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1   (0x08UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for USCI1_CTL1  \hideinitializer */
    318. 

  318. #define SYS_GPB_MFPL_PB4MFP_PWM0_CH1     (0x0BUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for PWM0_CH1    \hideinitializer */
    319. 

  319. #define SYS_GPB_MFPL_PB4MFP_UART2_RXD    (0x0DUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART2_RXD   \hideinitializer */
    320. 

  320. #define SYS_GPB_MFPL_PB4MFP_TM1          (0x0EUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for TM1         \hideinitializer */
    321. 

  321. #define SYS_GPB_MFPL_PB4MFP_INT1         (0x0FUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for INT1        \hideinitializer */
    322. 

  322. 

  323. /* PB.5 MFP */
    324. 

  324. #define SYS_GPB_MFPL_PB5MFP_GPIO         (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO        \hideinitializer */
    325. 

  325. #define SYS_GPB_MFPL_PB5MFP_ADC_CH5      (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ADC_CH5     \hideinitializer */
    326. 

  326. #define SYS_GPB_MFPL_PB5MFP_ADC0_CH5     (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ADC0_CH5    \hideinitializer */
    327. 

  327. #define SYS_GPB_MFPL_PB5MFP_ACMP1_N      (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ACMP1_N     \hideinitializer */
    328. 

  328. #define SYS_GPB_MFPL_PB5MFP_EBI_ADR0     (0x02UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_ADR0    \hideinitializer */
    329. 

  329. #define SYS_GPB_MFPL_PB5MFP_I2C0_SCL     (0x06UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for I2C0_SCL    \hideinitializer */
    330. 

  330. #define SYS_GPB_MFPL_PB5MFP_UART5_TXD    (0x07UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART5_TXD   \hideinitializer */
    331. 

  331. #define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0   (0x08UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for USCI1_CTL0  \hideinitializer */
    332. 

  332. #define SYS_GPB_MFPL_PB5MFP_PWM0_CH0     (0x0BUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for PWM0_CH0    \hideinitializer */
    333. 

  333. #define SYS_GPB_MFPL_PB5MFP_UART2_TXD    (0x0DUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART2_TXD   \hideinitializer */
    334. 

  334. #define SYS_GPB_MFPL_PB5MFP_TM0          (0x0EUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for TM0         \hideinitializer */
    335. 

  335. #define SYS_GPB_MFPL_PB5MFP_INT0         (0x0FUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for INT0        \hideinitializer */
    336. 

  336. 

  337. /* PB.6 MFP */
    338. 

  338. #define SYS_GPB_MFPL_PB6MFP_GPIO         (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO        \hideinitializer */
    339. 

  339. #define SYS_GPB_MFPL_PB6MFP_ADC_CH6      (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ADC_CH6     \hideinitializer */
    340. 

  340. #define SYS_GPB_MFPL_PB6MFP_ADC0_CH6     (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ADC0_CH6    \hideinitializer */
    341. 

  341. #define SYS_GPB_MFPL_PB6MFP_EBI_nWRH     (0x02UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_nWRH    \hideinitializer */
    342. 

  342. #define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1   (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for USCI1_DAT1  \hideinitializer */
    343. 

  343. #define SYS_GPB_MFPL_PB6MFP_UART1_RXD    (0x06UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for UART1_RXD   \hideinitializer */
    344. 

  344. #define SYS_GPB_MFPL_PB6MFP_EBI_nCS1     (0x08UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_nCS1    \hideinitializer */
    345. 

  345. #define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5    (0x0AUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for BPWM1_CH5   \hideinitializer */
    346. 

  346. #define SYS_GPB_MFPL_PB6MFP_PWM1_BRAKE1  (0x0BUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for PWM1_BRAKE1 \hideinitializer */
    347. 

  347. #define SYS_GPB_MFPL_PB6MFP_PWM1_CH5     (0x0CUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for PWM1_CH5    \hideinitializer */
    348. 

  348. #define SYS_GPB_MFPL_PB6MFP_INT4         (0x0DUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for INT4        \hideinitializer */
    349. 

  349. #define SYS_GPB_MFPL_PB6MFP_ACMP1_O      (0x0FUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ACMP1_O     \hideinitializer */
    350. 

  350. 

  351. /* PB.7 MFP */
    352. 

  352. #define SYS_GPB_MFPL_PB7MFP_GPIO         (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO        \hideinitializer */
    353. 

  353. #define SYS_GPB_MFPL_PB7MFP_ADC_CH7      (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ADC_CH7     \hideinitializer */
    354. 

  354. #define SYS_GPB_MFPL_PB7MFP_ADC0_CH7     (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ADC0_CH7    \hideinitializer */
    355. 

  355. #define SYS_GPB_MFPL_PB7MFP_EBI_nWRL     (0x02UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_nWRL    \hideinitializer */
    356. 

  356. #define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0   (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for USCI1_DAT0  \hideinitializer */
    357. 

  357. #define SYS_GPB_MFPL_PB7MFP_UART1_TXD    (0x06UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for UART1_TXD   \hideinitializer */
    358. 

  358. #define SYS_GPB_MFPL_PB7MFP_EBI_nCS0     (0x08UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_nCS0    \hideinitializer */
    359. 

  359. #define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4    (0x0AUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for BPWM1_CH4   \hideinitializer */
    360. 

  360. #define SYS_GPB_MFPL_PB7MFP_PWM1_BRAKE0  (0x0BUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for PWM1_BRAKE0 \hideinitializer */
    361. 

  361. #define SYS_GPB_MFPL_PB7MFP_PWM1_CH4     (0x0CUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for PWM1_CH4    \hideinitializer */
    362. 

  362. #define SYS_GPB_MFPL_PB7MFP_INT5         (0x0DUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for INT5        \hideinitializer */
    363. 

  363. #define SYS_GPB_MFPL_PB7MFP_ACMP0_O      (0x0FUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ACMP0_O     \hideinitializer */
    364. 

  364. 

  365. /* PB.8 MFP */
    366. 

  366. #define SYS_GPB_MFPH_PB8MFP_GPIO         (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO        \hideinitializer */
    367. 

  367. #define SYS_GPB_MFPH_PB8MFP_ADC_CH8      (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for ADC_CH8     \hideinitializer */
    368. 

  368. #define SYS_GPB_MFPH_PB8MFP_ADC0_CH8     (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for ADC0_CH8    \hideinitializer */
    369. 

  369. #define SYS_GPB_MFPH_PB8MFP_EBI_ADR19    (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EBI_ADR19   \hideinitializer */
    370. 

  370. #define SYS_GPB_MFPH_PB8MFP_USCI1_CLK    (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for USCI1_CLK   \hideinitializer */
    371. 

  371. #define SYS_GPB_MFPH_PB8MFP_UART0_RXD    (0x05UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART0_RXD   \hideinitializer */
    372. 

  372. #define SYS_GPB_MFPH_PB8MFP_UART1_nRTS   (0x06UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART1_nRTS  \hideinitializer */
    373. 

  373. #define SYS_GPB_MFPH_PB8MFP_UART7_RXD    (0x08UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART7_RXD   \hideinitializer */
    374. 

  374. #define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3    (0x0AUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for BPWM1_CH3   \hideinitializer */
    375. 

  375. 

  376. /* PB.9 MFP */
    377. 

  377. #define SYS_GPB_MFPH_PB9MFP_GPIO         (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO        \hideinitializer */
    378. 

  378. #define SYS_GPB_MFPH_PB9MFP_ADC_CH9      (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for ADC_CH9     \hideinitializer */
    379. 

  379. #define SYS_GPB_MFPH_PB9MFP_ADC0_CH9     (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for ADC0_CH9    \hideinitializer */
    380. 

  380. #define SYS_GPB_MFPH_PB9MFP_EBI_ADR18    (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EBI_ADR18   \hideinitializer */
    381. 

  381. #define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1   (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for USCI1_CTL1  \hideinitializer */
    382. 

  382. #define SYS_GPB_MFPH_PB9MFP_UART0_TXD    (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART0_TXD   \hideinitializer */
    383. 

  383. #define SYS_GPB_MFPH_PB9MFP_UART1_nCTS   (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART1_nCTS  \hideinitializer */
    384. 

  384. #define SYS_GPB_MFPH_PB9MFP_UART7_TXD    (0x08UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART7_TXD   \hideinitializer */
    385. 

  385. #define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2    (0x0AUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for BPWM1_CH2   \hideinitializer */
    386. 

  386. 

  387. /* PB.10 MFP */
    388. 

  388. #define SYS_GPB_MFPH_PB10MFP_GPIO        (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for GPIO       \hideinitializer */
    389. 

  389. #define SYS_GPB_MFPH_PB10MFP_ADC_CH10    (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for ADC_CH10   \hideinitializer */
    390. 

  390. #define SYS_GPB_MFPH_PB10MFP_ADC0_CH10   (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for ADC0_CH10  \hideinitializer */
    391. 

  391. #define SYS_GPB_MFPH_PB10MFP_EBI_ADR17   (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for EBI_ADR17  \hideinitializer */
    392. 

  392. #define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0  (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for USCI1_CTL0 \hideinitializer */
    393. 

  393. #define SYS_GPB_MFPH_PB10MFP_UART0_nRTS  (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for UART0_nRTS \hideinitializer */
    394. 

  394. #define SYS_GPB_MFPH_PB10MFP_UART4_RXD   (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for UART4_RXD  \hideinitializer */
    395. 

  395. #define SYS_GPB_MFPH_PB10MFP_I2C1_SDA    (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for I2C1_SDA   \hideinitializer */
    396. 

  396. #define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1   (0x0AUL<<SYS_GPB_MFPH_PB10MFP_Pos)/*!< GPB_MFPH PB10 setting for BPWM1_CH1  \hideinitializer */
    397. 

  397. 

  398. /* PB.11 MFP */
    399. 

  399. #define SYS_GPB_MFPH_PB11MFP_GPIO        (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for GPIO         \hideinitializer */
    400. 

  400. #define SYS_GPB_MFPH_PB11MFP_ADC_CH11    (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for ADC_CH11     \hideinitializer */
    401. 

  401. #define SYS_GPB_MFPH_PB11MFP_ADC0_CH11   (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for ADC0_CH11    \hideinitializer */
    402. 

  402. #define SYS_GPB_MFPH_PB11MFP_EBI_ADR16   (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for EBI_ADR16    \hideinitializer */
    403. 

  403. #define SYS_GPB_MFPH_PB11MFP_UART0_nCTS  (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for UART0_nCTS   \hideinitializer */
    404. 

  404. #define SYS_GPB_MFPH_PB11MFP_UART4_TXD   (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for UART4_TXD    \hideinitializer */
    405. 

  405. #define SYS_GPB_MFPH_PB11MFP_I2C1_SCL    (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for I2C1_SCL     \hideinitializer */
    406. 

  406. #define SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos)/*!< GPB_MFPH PB11 setting for SPI0_I2SMCLK \hideinitializer */
    407. 

  407. #define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0   (0x0AUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for BPWM1_CH0    \hideinitializer */
    408. 

  408. 

  409. /* PB.12 MFP */
    410. 

  410. #define SYS_GPB_MFPH_PB12MFP_GPIO        (0x00UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for GPIO       \hideinitializer */
    411. 

  411. #define SYS_GPB_MFPH_PB12MFP_ADC_CH12    (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for ADC_CH12   \hideinitializer */
    412. 

  412. #define SYS_GPB_MFPH_PB12MFP_ADC0_CH12   (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for ADC0_CH12  \hideinitializer */
    413. 

  413. #define SYS_GPB_MFPH_PB12MFP_ACMP0_P2    (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for ACMP0_P2   \hideinitializer */
    414. 

  414. #define SYS_GPB_MFPH_PB12MFP_ACMP1_P2    (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for ACMP1_P2   \hideinitializer */
    415. 

  415. #define SYS_GPB_MFPH_PB12MFP_EBI_AD15    (0x02UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for EBI_AD15   \hideinitializer */
    416. 

  416. #define SYS_GPB_MFPH_PB12MFP_SPI0_MOSI   (0x04UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for SPI0_MOSI  \hideinitializer */
    417. 

  417. #define SYS_GPB_MFPH_PB12MFP_USCI0_CLK   (0x05UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for USCI0_CLK  \hideinitializer */
    418. 

  418. #define SYS_GPB_MFPH_PB12MFP_UART0_RXD   (0x06UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for UART0_RXD  \hideinitializer */
    419. 

  419. #define SYS_GPB_MFPH_PB12MFP_UART3_nCTS  (0x07UL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for UART3_nCTS \hideinitializer */
    420. 

  420. #define SYS_GPB_MFPH_PB12MFP_PWM1_CH3    (0x0BUL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for PWM1_CH3   \hideinitializer */
    421. 

  421. #define SYS_GPB_MFPH_PB12MFP_BPWM0_CH0   (0x0CUL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for BPWM0_CH0  \hideinitializer */
    422. 

  422. #define SYS_GPB_MFPH_PB12MFP_TM3_EXT     (0x0DUL<<SYS_GPB_MFPH_PB12MFP_Pos)/*!< GPB_MFPH PB12 setting for TM3_EXT    \hideinitializer */
    423. 

  423. 

  424. /* PB.13 MFP */
    425. 

  425. #define SYS_GPB_MFPH_PB13MFP_GPIO        (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for GPIO       \hideinitializer */
    426. 

  426. #define SYS_GPB_MFPH_PB13MFP_ADC_CH13    (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for ADC_CH13   \hideinitializer */
    427. 

  427. #define SYS_GPB_MFPH_PB13MFP_ADC0_CH13   (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for ADC0_CH13  \hideinitializer */
    428. 

  428. #define SYS_GPB_MFPH_PB13MFP_ACMP0_P3    (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for ACMP0_P3   \hideinitializer */
    429. 

  429. #define SYS_GPB_MFPH_PB13MFP_ACMP1_P3    (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for ACMP1_P3   \hideinitializer */
    430. 

  430. #define SYS_GPB_MFPH_PB13MFP_EBI_AD14    (0x02UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for EBI_AD14   \hideinitializer */
    431. 

  431. #define SYS_GPB_MFPH_PB13MFP_SPI0_MISO   (0x04UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for SPI0_MISO  \hideinitializer */
    432. 

  432. #define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0  (0x05UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for USCI0_DAT0 \hideinitializer */
    433. 

  433. #define SYS_GPB_MFPH_PB13MFP_UART0_TXD   (0x06UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for UART0_TXD  \hideinitializer */
    434. 

  434. #define SYS_GPB_MFPH_PB13MFP_UART3_nRTS  (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for UART3_nRTS \hideinitializer */
    435. 

  435. #define SYS_GPB_MFPH_PB13MFP_PWM1_CH2    (0x0BUL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for PWM1_CH2   \hideinitializer */
    436. 

  436. #define SYS_GPB_MFPH_PB13MFP_BPWM0_CH1   (0x0CUL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for BPWM0_CH1  \hideinitializer */
    437. 

  437. #define SYS_GPB_MFPH_PB13MFP_TM2_EXT     (0x0DUL<<SYS_GPB_MFPH_PB13MFP_Pos)/*!< GPB_MFPH PB13 setting for TM2_EXT    \hideinitializer */
    438. 

  438. 

  439. /* PB.14 MFP */
    440. 

  440. #define SYS_GPB_MFPH_PB14MFP_GPIO        (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for GPIO       \hideinitializer */
    441. 

  441. #define SYS_GPB_MFPH_PB14MFP_ADC_CH14    (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for ADC_CH14   \hideinitializer */
    442. 

  442. #define SYS_GPB_MFPH_PB14MFP_ADC0_CH14   (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for ADC0_CH14  \hideinitializer */
    443. 

  443. #define SYS_GPB_MFPH_PB14MFP_EBI_AD13    (0x02UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for EBI_AD13   \hideinitializer */
    444. 

  444. #define SYS_GPB_MFPH_PB14MFP_SPI0_CLK    (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for SPI0_CLK   \hideinitializer */
    445. 

  445. #define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1  (0x05UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for USCI0_DAT1 \hideinitializer */
    446. 

  446. #define SYS_GPB_MFPH_PB14MFP_UART0_nRTS  (0x06UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for UART0_nRTS \hideinitializer */
    447. 

  447. #define SYS_GPB_MFPH_PB14MFP_UART3_RXD   (0x07UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for UART3_RXD  \hideinitializer */
    448. 

  448. #define SYS_GPB_MFPH_PB14MFP_BPWM1_CH5   (0x09UL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for BPWM1_CH5  \hideinitializer */
    449. 

  449. #define SYS_GPB_MFPH_PB14MFP_PWM1_CH1    (0x0BUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for PWM1_CH1   \hideinitializer */
    450. 

  450. #define SYS_GPB_MFPH_PB14MFP_BPWM0_CH2   (0x0CUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for BPWM0_CH2  \hideinitializer */
    451. 

  451. #define SYS_GPB_MFPH_PB14MFP_TM1_EXT     (0x0DUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for TM1_EXT    \hideinitializer */
    452. 

  452. #define SYS_GPB_MFPH_PB14MFP_CLKO        (0x0EUL<<SYS_GPB_MFPH_PB14MFP_Pos)/*!< GPB_MFPH PB14 setting for CLKO       \hideinitializer */
    453. 

  453. 

  454. /* PB.15 MFP */
    455. 

  455. #define SYS_GPB_MFPH_PB15MFP_GPIO        (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for GPIO          \hideinitializer */
    456. 

  456. #define SYS_GPB_MFPH_PB15MFP_ADC_CH15    (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for ADC_CH15      \hideinitializer */
    457. 

  457. #define SYS_GPB_MFPH_PB15MFP_ADC0_CH15   (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for ADC0_CH15     \hideinitializer */
    458. 

  458. #define SYS_GPB_MFPH_PB15MFP_EBI_AD12    (0x02UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for EBI_AD12      \hideinitializer */
    459. 

  459. #define SYS_GPB_MFPH_PB15MFP_SPI0_SS     (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for SPI0_SS       \hideinitializer */
    460. 

  460. #define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1  (0x05UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for USCI0_CTL1    \hideinitializer */
    461. 

  461. #define SYS_GPB_MFPH_PB15MFP_UART0_nCTS  (0x06UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for UART0_nCTS    \hideinitializer */
    462. 

  462. #define SYS_GPB_MFPH_PB15MFP_UART3_TXD   (0x07UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for UART3_TXD     \hideinitializer */
    463. 

  463. #define SYS_GPB_MFPH_PB15MFP_BPWM1_CH4   (0x09UL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for BPWM1_CH4     \hideinitializer */
    464. 

  464. #define SYS_GPB_MFPH_PB15MFP_PWM1_CH0    (0x0BUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for PWM1_CH0      \hideinitializer */
    465. 

  465. #define SYS_GPB_MFPH_PB15MFP_BPWM0_CH3   (0x0CUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for BPWM0_CH3     \hideinitializer */
    466. 

  466. #define SYS_GPB_MFPH_PB15MFP_TM0_EXT     (0x0DUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for TM0_EXT       \hideinitializer */
    467. 

  467. #define SYS_GPB_MFPH_PB15MFP_PWM0_BRAKE1 (0x0FUL<<SYS_GPB_MFPH_PB15MFP_Pos)/*!< GPB_MFPH PB15 setting for PWM0_BRAKE1   \hideinitializer */
    468. 

  468. 

  469. /* PC.0 MFP */
    470. 

  470. #define SYS_GPC_MFPL_PC0MFP_GPIO         (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO        \hideinitializer */
    471. 

  471. #define SYS_GPC_MFPL_PC0MFP_EBI_AD0      (0x02UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_AD0     \hideinitializer */
    472. 

  472. #define SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0  (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for QSPI0_MOSI0 \hideinitializer */
    473. 

  473. #define SYS_GPC_MFPL_PC0MFP_UART2_RXD    (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_RXD   \hideinitializer */
    474. 

  474. #define SYS_GPC_MFPL_PC0MFP_I2C0_SDA     (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2C0_SDA    \hideinitializer */
    475. 

  475. #define SYS_GPC_MFPL_PC0MFP_BPWM1_CH3    (0x0BUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for BPWM1_CH3   \hideinitializer */
    476. 

  476. #define SYS_GPC_MFPL_PC0MFP_PWM1_CH5     (0x0CUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for PWM1_CH5    \hideinitializer */
    477. 

  477. #define SYS_GPC_MFPL_PC0MFP_BPWM0_CH4    (0x0DUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for BPWM0_CH4   \hideinitializer */
    478. 

  478. #define SYS_GPC_MFPL_PC0MFP_ACMP1_O      (0x0EUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for ACMP1_O     \hideinitializer */
    479. 

  479. 

  480. /* PC.1 MFP */
    481. 

  481. #define SYS_GPC_MFPL_PC1MFP_GPIO         (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO        \hideinitializer */
    482. 

  482. #define SYS_GPC_MFPL_PC1MFP_EBI_AD1      (0x02UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD1     \hideinitializer */
    483. 

  483. #define SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0  (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for QSPI0_MISO0 \hideinitializer */
    484. 

  484. #define SYS_GPC_MFPL_PC1MFP_UART2_TXD    (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_TXD   \hideinitializer */
    485. 

  485. #define SYS_GPC_MFPL_PC1MFP_I2C0_SCL     (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2C0_SCL    \hideinitializer */
    486. 

  486. #define SYS_GPC_MFPL_PC1MFP_BPWM1_CH2    (0x0BUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for BPWM1_CH2   \hideinitializer */
    487. 

  487. #define SYS_GPC_MFPL_PC1MFP_PWM1_CH4     (0x0CUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for PWM1_CH4    \hideinitializer */
    488. 

  488. #define SYS_GPC_MFPL_PC1MFP_BPWM0_CH5    (0x0DUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for BPWM0_CH5   \hideinitializer */
    489. 

  489. #define SYS_GPC_MFPL_PC1MFP_ACMP0_O      (0x0EUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for ACMP0_O     \hideinitializer */
    490. 

  490. #define SYS_GPC_MFPL_PC1MFP_ADC_ST       (0x0FUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for ADC_ST      \hideinitializer */
    491. 

  491. #define SYS_GPC_MFPL_PC1MFP_ADC0_ST      (0x0FUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for ADC0_ST     \hideinitializer */
    492. 

  492. 

  493. /* PC.2 MFP */
    494. 

  494. #define SYS_GPC_MFPL_PC2MFP_GPIO         (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO        \hideinitializer */
    495. 

  495. #define SYS_GPC_MFPL_PC2MFP_EBI_AD2      (0x02UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD2     \hideinitializer */
    496. 

  496. #define SYS_GPC_MFPL_PC2MFP_QSPI0_CLK    (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for QSPI0_CLK   \hideinitializer */
    497. 

  497. #define SYS_GPC_MFPL_PC2MFP_UART2_nCTS   (0x08UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART2_nCTS  \hideinitializer */
    498. 

  498. #define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS  (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2C0_SMBSUS \hideinitializer */
    499. 

  499. #define SYS_GPC_MFPL_PC2MFP_UART3_RXD    (0x0BUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART3_RXD   \hideinitializer */
    500. 

  500. #define SYS_GPC_MFPL_PC2MFP_PWM1_CH3     (0x0CUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for PWM1_CH3    \hideinitializer */
    501. 

  501. 

  502. /* PC.3 MFP */
    503. 

  503. #define SYS_GPC_MFPL_PC3MFP_GPIO         (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO        \hideinitializer */
    504. 

  504. #define SYS_GPC_MFPL_PC3MFP_EBI_AD3      (0x02UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD3     \hideinitializer */
    505. 

  505. #define SYS_GPC_MFPL_PC3MFP_QSPI0_SS     (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for QSPI0_SS    \hideinitializer */
    506. 

  506. #define SYS_GPC_MFPL_PC3MFP_UART2_nRTS   (0x08UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART2_nRTS  \hideinitializer */
    507. 

  507. #define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL   (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2C0_SMBAL  \hideinitializer */
    508. 

  508. #define SYS_GPC_MFPL_PC3MFP_UART3_TXD    (0x0BUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART3_TXD   \hideinitializer */
    509. 

  509. #define SYS_GPC_MFPL_PC3MFP_PWM1_CH2     (0x0CUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for PWM1_CH2    \hideinitializer */
    510. 

  510. 

  511. /* PC.4 MFP */
    512. 

  512. #define SYS_GPC_MFPL_PC4MFP_GPIO         (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO        \hideinitializer */
    513. 

  513. #define SYS_GPC_MFPL_PC4MFP_EBI_AD4      (0x02UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD4     \hideinitializer */
    514. 

  514. #define SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1  (0x04UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for QSPI0_MOSI1 \hideinitializer */
    515. 

  515. #define SYS_GPC_MFPL_PC4MFP_UART2_RXD    (0x08UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART2_RXD   \hideinitializer */
    516. 

  516. #define SYS_GPC_MFPL_PC4MFP_I2C1_SDA     (0x09UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2C1_SDA    \hideinitializer */
    517. 

  517. #define SYS_GPC_MFPL_PC4MFP_UART4_RXD    (0x0BUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART4_RXD   \hideinitializer */
    518. 

  518. #define SYS_GPC_MFPL_PC4MFP_PWM1_CH1     (0x0CUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for PWM1_CH1    \hideinitializer */
    519. 

  519. 

  520. /* PC.5 MFP */
    521. 

  521. #define SYS_GPC_MFPL_PC5MFP_GPIO         (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO        \hideinitializer */
    522. 

  522. #define SYS_GPC_MFPL_PC5MFP_EBI_AD5      (0x02UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_AD5     \hideinitializer */
    523. 

  523. #define SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1  (0x04UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for QSPI0_MISO1 \hideinitializer */
    524. 

  524. #define SYS_GPC_MFPL_PC5MFP_UART2_TXD    (0x08UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART2_TXD   \hideinitializer */
    525. 

  525. #define SYS_GPC_MFPL_PC5MFP_I2C1_SCL     (0x09UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for I2C1_SCL    \hideinitializer */
    526. 

  526. #define SYS_GPC_MFPL_PC5MFP_UART4_TXD    (0x0BUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART4_TXD   \hideinitializer */
    527. 

  527. #define SYS_GPC_MFPL_PC5MFP_PWM1_CH0     (0x0CUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for PWM1_CH0    \hideinitializer */
    528. 

  528. 

  529. /* PC.6 MFP */
    530. 

  530. #define SYS_GPC_MFPL_PC6MFP_GPIO         (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO        \hideinitializer */
    531. 

  531. #define SYS_GPC_MFPL_PC6MFP_EBI_AD8      (0x02UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD8     \hideinitializer */
    532. 

  532. #define SYS_GPC_MFPL_PC6MFP_UART4_RXD    (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART4_RXD   \hideinitializer */
    533. 

  533. #define SYS_GPC_MFPL_PC6MFP_UART0_nRTS   (0x07UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART0_nRTS  \hideinitializer */
    534. 

  534. #define SYS_GPC_MFPL_PC6MFP_UART6_RXD    (0x09UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART6_RXD   \hideinitializer */
    535. 

  535. #define SYS_GPC_MFPL_PC6MFP_PWM1_CH3     (0x0BUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for PWM1_CH3    \hideinitializer */
    536. 

  536. #define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1    (0x0CUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for BPWM1_CH1   \hideinitializer */
    537. 

  537. #define SYS_GPC_MFPL_PC6MFP_TM1          (0x0EUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for TM1         \hideinitializer */
    538. 

  538. #define SYS_GPC_MFPL_PC6MFP_INT2         (0x0FUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for INT2        \hideinitializer */
    539. 

  539. 

  540. /* PC.7 MFP */
    541. 

  541. #define SYS_GPC_MFPL_PC7MFP_GPIO         (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO        \hideinitializer */
    542. 

  542. #define SYS_GPC_MFPL_PC7MFP_EBI_AD9      (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD9     \hideinitializer */
    543. 

  543. #define SYS_GPC_MFPL_PC7MFP_UART4_TXD    (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART4_TXD   \hideinitializer */
    544. 

  544. #define SYS_GPC_MFPL_PC7MFP_UART0_nCTS   (0x07UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART0_nCTS  \hideinitializer */
    545. 

  545. #define SYS_GPC_MFPL_PC7MFP_UART6_TXD    (0x09UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART6_TXD   \hideinitializer */
    546. 

  546. #define SYS_GPC_MFPL_PC7MFP_PWM1_CH2     (0x0BUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for PWM1_CH2    \hideinitializer */
    547. 

  547. #define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0    (0x0CUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for BPWM1_CH0   \hideinitializer */
    548. 

  548. #define SYS_GPC_MFPL_PC7MFP_TM0          (0x0EUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for TM0         \hideinitializer */
    549. 

  549. #define SYS_GPC_MFPL_PC7MFP_INT3         (0x0FUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for INT3        \hideinitializer */
    550. 

  550. 

  551. /* PC.8 MFP */
    552. 

  552. #define SYS_GPC_MFPH_PC8MFP_GPIO         (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for GPIO       \hideinitializer */
    553. 

  553. #define SYS_GPC_MFPH_PC8MFP_EBI_ADR16    (0x02UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for EBI_ADR16  \hideinitializer */
    554. 

  554. #define SYS_GPC_MFPH_PC8MFP_I2C0_SDA     (0x04UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for I2C0_SDA   \hideinitializer */
    555. 

  555. #define SYS_GPC_MFPH_PC8MFP_UART4_nCTS   (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for UART4_nCTS \hideinitializer */
    556. 

  556. #define SYS_GPC_MFPH_PC8MFP_UART1_RXD    (0x08UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for UART1_RXD  \hideinitializer */
    557. 

  557. #define SYS_GPC_MFPH_PC8MFP_PWM1_CH1     (0x0BUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for PWM1_CH1   \hideinitializer */
    558. 

  558. #define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4    (0x0CUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for BPWM1_CH4  \hideinitializer */
    559. 

  559. 

  560. /* PC.9 MFP */
    561. 

  561. #define SYS_GPC_MFPH_PC9MFP_GPIO         (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO       \hideinitializer */
    562. 

  562. #define SYS_GPC_MFPH_PC9MFP_EBI_ADR7     (0x02UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EBI_ADR7   \hideinitializer */
    563. 

  563. #define SYS_GPC_MFPH_PC9MFP_UART6_nCTS   (0x05UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for UART6_nCTS \hideinitializer */
    564. 

  564. #define SYS_GPC_MFPH_PC9MFP_UART3_RXD    (0x07UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for UART3_RXD  \hideinitializer */
    565. 

  565. #define SYS_GPC_MFPH_PC9MFP_PWM1_CH3     (0x0CUL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for PWM1_CH3   \hideinitializer */
    566. 

  566. 

  567. /* PC.10 MFP */
    568. 

  568. #define SYS_GPC_MFPH_PC10MFP_GPIO        (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for GPIO          \hideinitializer */
    569. 

  569. #define SYS_GPC_MFPH_PC10MFP_EBI_ADR6    (0x02UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for EBI_ADR6      \hideinitializer */
    570. 

  570. #define SYS_GPC_MFPH_PC10MFP_UART6_nRTS  (0x05UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for UART6_nRTS    \hideinitializer */
    571. 

  571. #define SYS_GPC_MFPH_PC10MFP_UART3_TXD   (0x07UL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for UART3_TXD     \hideinitializer */
    572. 

  572. #define SYS_GPC_MFPH_PC10MFP_PWM1_CH2    (0x0CUL<<SYS_GPC_MFPH_PC10MFP_Pos)/*!< GPC_MFPH PC10 setting for PWM1_CH2      \hideinitializer */
    573. 

  573. 

  574. /* PC.11 MFP */
    575. 

  575. #define SYS_GPC_MFPH_PC11MFP_GPIO        (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for GPIO      \hideinitializer */
    576. 

  576. #define SYS_GPC_MFPH_PC11MFP_EBI_ADR5    (0x02UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for EBI_ADR5  \hideinitializer */
    577. 

  577. #define SYS_GPC_MFPH_PC11MFP_UART0_RXD   (0x03UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for UART0_RXD \hideinitializer */
    578. 

  578. #define SYS_GPC_MFPH_PC11MFP_I2C0_SDA    (0x04UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for I2C0_SDA  \hideinitializer */
    579. 

  579. #define SYS_GPC_MFPH_PC11MFP_UART6_RXD   (0x05UL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for UART6_RXD \hideinitializer */
    580. 

  580. #define SYS_GPC_MFPH_PC11MFP_PWM1_CH1    (0x0CUL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for PWM1_CH1  \hideinitializer */
    581. 

  581. #define SYS_GPC_MFPH_PC11MFP_ACMP1_O     (0x0EUL<<SYS_GPC_MFPH_PC11MFP_Pos)/*!< GPC_MFPH PC11 setting for ACMP1_O   \hideinitializer */
    582. 

  582. 

  583. /* PC.12 MFP */
    584. 

  584. #define SYS_GPC_MFPH_PC12MFP_GPIO        (0x00UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for GPIO      \hideinitializer */
    585. 

  585. #define SYS_GPC_MFPH_PC12MFP_EBI_ADR4    (0x02UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for EBI_ADR4  \hideinitializer */
    586. 

  586. #define SYS_GPC_MFPH_PC12MFP_UART0_TXD   (0x03UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for UART0_TXD \hideinitializer */
    587. 

  587. #define SYS_GPC_MFPH_PC12MFP_I2C0_SCL    (0x04UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for I2C0_SCL  \hideinitializer */
    588. 

  588. #define SYS_GPC_MFPH_PC12MFP_UART6_TXD   (0x05UL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for UART6_TXD \hideinitializer */
    589. 

  589. #define SYS_GPC_MFPH_PC12MFP_PWM1_CH0    (0x0CUL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for PWM1_CH0  \hideinitializer */
    590. 

  590. #define SYS_GPC_MFPH_PC12MFP_ACMP0_O     (0x0EUL<<SYS_GPC_MFPH_PC12MFP_Pos)/*!< GPC_MFPH PC12 setting for ACMP0_O   \hideinitializer */
    591. 

  591. 

  592. /* PC.13 MFP */
    593. 

  593. #define SYS_GPC_MFPH_PC13MFP_GPIO        (0x00UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for GPIO          \hideinitializer */
    594. 

  594. #define SYS_GPC_MFPH_PC13MFP_EBI_ADR10   (0x02UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for EBI_ADR10     \hideinitializer */
    595. 

  595. #define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0  (0x06UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for USCI0_CTL0    \hideinitializer */
    596. 

  596. #define SYS_GPC_MFPH_PC13MFP_UART2_TXD   (0x07UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for UART2_TXD     \hideinitializer */
    597. 

  597. #define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4   (0x09UL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for BPWM0_CH4     \hideinitializer */
    598. 

  598. #define SYS_GPC_MFPH_PC13MFP_CLKO        (0x0DUL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for CLKO          \hideinitializer */
    599. 

  599. #define SYS_GPC_MFPH_PC13MFP_ADC_ST      (0x0EUL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for ADC_ST        \hideinitializer */
    600. 

  600. #define SYS_GPC_MFPH_PC13MFP_ADC0_ST     (0x0EUL<<SYS_GPC_MFPH_PC13MFP_Pos)/*!< GPC_MFPH PC13 setting for ADC0_ST       \hideinitializer */
    601. 

  601. 

  602. /* PC.14 MFP */
    603. 

  603. #define SYS_GPC_MFPH_PC14MFP_GPIO        (0x00UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for GPIO         \hideinitializer */
    604. 

  604. #define SYS_GPC_MFPH_PC14MFP_EBI_AD11    (0x02UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for EBI_AD11     \hideinitializer */
    605. 

  605. #define SYS_GPC_MFPH_PC14MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPC_MFPH_PC14MFP_Pos)/*!< GPC_MFPH PC14 setting for SPI0_I2SMCLK \hideinitializer */
    606. 

  606. #define SYS_GPC_MFPH_PC14MFP_USCI0_CTL0  (0x05UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for USCI0_CTL0   \hideinitializer */
    607. 

  607. #define SYS_GPC_MFPH_PC14MFP_QSPI0_CLK   (0x06UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for QSPI0_CLK    \hideinitializer */
    608. 

  608. #define SYS_GPC_MFPH_PC14MFP_TM1         (0x0DUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for TM1          \hideinitializer */
    609. 

  609. 

  610. /* PC.15 MFP */
    611. 

  611. 

  612. /* PD.0 MFP */
    613. 

  613. #define SYS_GPD_MFPL_PD0MFP_GPIO         (0x00UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO        \hideinitializer */
    614. 

  614. #define SYS_GPD_MFPL_PD0MFP_EBI_AD13     (0x02UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EBI_AD13    \hideinitializer */
    615. 

  615. #define SYS_GPD_MFPL_PD0MFP_USCI0_CLK    (0x03UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for USCI0_CLK   \hideinitializer */
    616. 

  616. #define SYS_GPD_MFPL_PD0MFP_SPI0_MOSI    (0x04UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI0_MOSI   \hideinitializer */
    617. 

  617. #define SYS_GPD_MFPL_PD0MFP_UART3_RXD    (0x05UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for UART3_RXD   \hideinitializer */
    618. 

  618. #define SYS_GPD_MFPL_PD0MFP_TM2          (0x0EUL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for TM2         \hideinitializer */
    619. 

  619. 

  620. /* PD.1 MFP */
    621. 

  621. #define SYS_GPD_MFPL_PD1MFP_GPIO         (0x00UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO        \hideinitializer */
    622. 

  622. #define SYS_GPD_MFPL_PD1MFP_EBI_AD12     (0x02UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_AD12    \hideinitializer */
    623. 

  623. #define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0   (0x03UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for USCI0_DAT0  \hideinitializer */
    624. 

  624. #define SYS_GPD_MFPL_PD1MFP_SPI0_MISO    (0x04UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SPI0_MISO   \hideinitializer */
    625. 

  625. #define SYS_GPD_MFPL_PD1MFP_UART3_TXD    (0x05UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for UART3_TXD   \hideinitializer */
    626. 

  626. 

  627. /* PD.2 MFP */
    628. 

  628. #define SYS_GPD_MFPL_PD2MFP_GPIO         (0x00UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO        \hideinitializer */
    629. 

  629. #define SYS_GPD_MFPL_PD2MFP_EBI_AD11     (0x02UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_AD11    \hideinitializer */
    630. 

  630. #define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1   (0x03UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for USCI0_DAT1  \hideinitializer */
    631. 

  631. #define SYS_GPD_MFPL_PD2MFP_SPI0_CLK     (0x04UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for SPI0_CLK    \hideinitializer */
    632. 

  632. #define SYS_GPD_MFPL_PD2MFP_UART3_nCTS   (0x05UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for UART3_nCTS  \hideinitializer */
    633. 

  633. #define SYS_GPD_MFPL_PD2MFP_UART0_RXD    (0x09UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for UART0_RXD   \hideinitializer */
    634. 

  634. 

  635. /* PD.3 MFP */
    636. 

  636. #define SYS_GPD_MFPL_PD3MFP_GPIO         (0x00UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO        \hideinitializer */
    637. 

  637. #define SYS_GPD_MFPL_PD3MFP_EBI_AD10     (0x02UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_AD10    \hideinitializer */
    638. 

  638. #define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1   (0x03UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for USCI0_CTL1  \hideinitializer */
    639. 

  639. #define SYS_GPD_MFPL_PD3MFP_SPI0_SS      (0x04UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SPI0_SS     \hideinitializer */
    640. 

  640. #define SYS_GPD_MFPL_PD3MFP_UART3_nRTS   (0x05UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for UART3_nRTS  \hideinitializer */
    641. 

  641. #define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0   (0x06UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for USCI1_CTL0  \hideinitializer */
    642. 

  642. #define SYS_GPD_MFPL_PD3MFP_UART0_TXD    (0x09UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for UART0_TXD   \hideinitializer */
    643. 

  643. 

  644. /* PD.4 MFP */
    645. 

  645. #define SYS_GPD_MFPL_PD4MFP_GPIO         (0x00UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO       \hideinitializer */
    646. 

  646. #define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0   (0x03UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USCI0_CTL0 \hideinitializer */
    647. 

  647. #define SYS_GPD_MFPL_PD4MFP_I2C1_SDA     (0x04UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for I2C1_SDA   \hideinitializer */
    648. 

  648. #define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1   (0x06UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USCI1_CTL1 \hideinitializer */
    649. 

  649. 

  650. /* PD.5 MFP */
    651. 

  651. #define SYS_GPD_MFPL_PD5MFP_GPIO         (0x00UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO       \hideinitializer */
    652. 

  652. #define SYS_GPD_MFPL_PD5MFP_I2C1_SCL     (0x04UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for I2C1_SCL   \hideinitializer */
    653. 

  653. #define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0   (0x06UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for USCI1_DAT0 \hideinitializer */
    654. 

  654. 

  655. /* PD.6 MFP */
    656. 

  656. #define SYS_GPD_MFPL_PD6MFP_GPIO         (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO       \hideinitializer */
    657. 

  657. #define SYS_GPD_MFPL_PD6MFP_UART1_RXD    (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART1_RXD  \hideinitializer */
    658. 

  658. #define SYS_GPD_MFPL_PD6MFP_I2C0_SDA     (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for I2C0_SDA   \hideinitializer */
    659. 

  659. #define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1   (0x06UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for USCI1_DAT1 \hideinitializer */
    660. 

  660. 

  661. /* PD.7 MFP */
    662. 

  662. #define SYS_GPD_MFPL_PD7MFP_GPIO         (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO       \hideinitializer */
    663. 

  663. #define SYS_GPD_MFPL_PD7MFP_UART1_TXD    (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for UART1_TXD  \hideinitializer */
    664. 

  664. #define SYS_GPD_MFPL_PD7MFP_I2C0_SCL     (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for I2C0_SCL   \hideinitializer */
    665. 

  665. #define SYS_GPD_MFPL_PD7MFP_USCI1_CLK    (0x06UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for USCI1_CLK  \hideinitializer */
    666. 

  666. 

  667. /* PD.8 MFP */
    668. 

  668. #define SYS_GPD_MFPH_PD8MFP_GPIO         (0x00UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO       \hideinitializer */
    669. 

  669. #define SYS_GPD_MFPH_PD8MFP_EBI_AD6      (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_AD6    \hideinitializer */
    670. 

  670. #define SYS_GPD_MFPH_PD8MFP_UART2_nRTS   (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for UART2_nRTS \hideinitializer */
    671. 

  671. #define SYS_GPD_MFPH_PD8MFP_UART7_RXD    (0x05UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for UART7_RXD  \hideinitializer */
    672. 

  672. 

  673. /* PD.9 MFP */
    674. 

  674. #define SYS_GPD_MFPH_PD9MFP_GPIO         (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO       \hideinitializer */
    675. 

  675. #define SYS_GPD_MFPH_PD9MFP_EBI_AD7      (0x02UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EBI_AD7    \hideinitializer */
    676. 

  676. #define SYS_GPD_MFPH_PD9MFP_UART2_nCTS   (0x04UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for UART2_nCTS \hideinitializer */
    677. 

  677. #define SYS_GPD_MFPH_PD9MFP_UART7_TXD    (0x05UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for UART7_TXD  \hideinitializer */
    678. 

  678. 

  679. /* PD.10 MFP */
    680. 

  680. #define SYS_GPD_MFPH_PD10MFP_GPIO        (0x00UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for GPIO      \hideinitializer */
    681. 

  681. #define SYS_GPD_MFPH_PD10MFP_EBI_nCS2    (0x02UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for EBI_nCS2  \hideinitializer */
    682. 

  682. #define SYS_GPD_MFPH_PD10MFP_UART1_RXD   (0x03UL<<SYS_GPD_MFPH_PD10MFP_Pos)/*!< GPD_MFPH PD10 setting for UART1_RXD \hideinitializer */
    683. 

  683. 

  684. /* PD.11 MFP */
    685. 

  685. #define SYS_GPD_MFPH_PD11MFP_GPIO        (0x00UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for GPIO      \hideinitializer */
    686. 

  686. #define SYS_GPD_MFPH_PD11MFP_EBI_nCS1    (0x02UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for EBI_nCS1  \hideinitializer */
    687. 

  687. #define SYS_GPD_MFPH_PD11MFP_UART1_TXD   (0x03UL<<SYS_GPD_MFPH_PD11MFP_Pos)/*!< GPD_MFPH PD11 setting for UART1_TXD \hideinitializer */
    688. 

  688. 

  689. /* PD.12 MFP */
    690. 

  690. #define SYS_GPD_MFPH_PD12MFP_GPIO        (0x00UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for GPIO      \hideinitializer */
    691. 

  691. #define SYS_GPD_MFPH_PD12MFP_EBI_nCS0    (0x02UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for EBI_nCS0  \hideinitializer */
    692. 

  692. #define SYS_GPD_MFPH_PD12MFP_UART2_RXD   (0x07UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for UART2_RXD \hideinitializer */
    693. 

  693. #define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5   (0x09UL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for BPWM0_CH5 \hideinitializer */
    694. 

  694. #define SYS_GPD_MFPH_PD12MFP_CLKO        (0x0DUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for CLKO      \hideinitializer */
    695. 

  695. #define SYS_GPD_MFPH_PD12MFP_ADC_ST      (0x0EUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for ADC_ST    \hideinitializer */
    696. 

  696. #define SYS_GPD_MFPH_PD12MFP_ADC0_ST     (0x0EUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for ADC0_ST   \hideinitializer */
    697. 

  697. #define SYS_GPD_MFPH_PD12MFP_INT5        (0x0FUL<<SYS_GPD_MFPH_PD12MFP_Pos)/*!< GPD_MFPH PD12 setting for INT5      \hideinitializer */
    698. 

  698. 

  699. /* PD.13 MFP */
    700. 

  700. #define SYS_GPD_MFPH_PD13MFP_GPIO         (0x00UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for GPIO         \hideinitializer */
    701. 

  701. #define SYS_GPD_MFPH_PD13MFP_EBI_AD10     (0x02UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for EBI_AD10     \hideinitializer */
    702. 

  702. #define SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK (0x04UL<<SYS_GPD_MFPH_PD13MFP_Pos)/*!< GPD_MFPH PD13 setting for SPI0_I2SMCLK \hideinitializer */
    703. 

  703. 

  704. /* PD.14 MFP */
    705. 

  705. #define SYS_GPD_MFPH_PD14MFP_GPIO         (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for GPIO         \hideinitializer */
    706. 

  706. #define SYS_GPD_MFPH_PD14MFP_EBI_nCS0     (0x02UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for EBI_nCS0     \hideinitializer */
    707. 

  707. #define SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for SPI0_I2SMCLK \hideinitializer */
    708. 

  708. #define SYS_GPD_MFPH_PD14MFP_USCI0_CTL0   (0x08UL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for USCI0_CTL0   \hideinitializer */
    709. 

  709. #define SYS_GPD_MFPH_PD14MFP_PWM0_CH4     (0x0BUL<<SYS_GPD_MFPH_PD14MFP_Pos)/*!< GPD_MFPH PD14 setting for PWM0_CH4     \hideinitializer */
    710. 

  710. 

  711. /* PD.15 MFP */
    712. 

  712. #define SYS_GPD_MFPH_PD15MFP_GPIO        (0x00UL<<SYS_GPD_MFPH_PD15MFP_Pos)/*!< GPD_MFPH PD15 setting for GPIO      \hideinitializer */
    713. 

  713. #define SYS_GPD_MFPH_PD15MFP_PWM0_CH5    (0x0CUL<<SYS_GPD_MFPH_PD15MFP_Pos)/*!< GPD_MFPH PD15 setting for PWM0_CH5  \hideinitializer */
    714. 

  714. #define SYS_GPD_MFPH_PD15MFP_TM3         (0x0EUL<<SYS_GPD_MFPH_PD15MFP_Pos)/*!< GPD_MFPH PD15 setting for TM3       \hideinitializer */
    715. 

  715. #define SYS_GPD_MFPH_PD15MFP_INT1        (0x0FUL<<SYS_GPD_MFPH_PD15MFP_Pos)/*!< GPD_MFPH PD15 setting for INT1      \hideinitializer */
    716. 

  716. 

  717. /* PE.0 MFP */
    718. 

  718. #define SYS_GPE_MFPL_PE0MFP_GPIO         (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO           \hideinitializer */
    719. 

  719. #define SYS_GPE_MFPL_PE0MFP_EBI_AD11     (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for EBI_AD11       \hideinitializer */
    720. 

  720. #define SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0  (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for QSPI0_MOSI0    \hideinitializer */
    721. 

  721. #define SYS_GPE_MFPL_PE0MFP_UART3_RXD    (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for UART3_RXD      \hideinitializer */
    722. 

  722. #define SYS_GPE_MFPL_PE0MFP_I2C1_SDA     (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2C1_SDA       \hideinitializer */
    723. 

  723. #define SYS_GPE_MFPL_PE0MFP_UART4_nRTS   (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for UART4_nRTS     \hideinitializer */
    724. 

  724. 

  725. /* PE.1 MFP */
    726. 

  726. #define SYS_GPE_MFPL_PE1MFP_GPIO         (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO           \hideinitializer */
    727. 

  727. #define SYS_GPE_MFPL_PE1MFP_EBI_AD10     (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for EBI_AD10       \hideinitializer */
    728. 

  728. #define SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0  (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for QSPI0_MISO0    \hideinitializer */
    729. 

  729. #define SYS_GPE_MFPL_PE1MFP_UART3_TXD    (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART3_TXD      \hideinitializer */
    730. 

  730. #define SYS_GPE_MFPL_PE1MFP_I2C1_SCL     (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for I2C1_SCL       \hideinitializer */
    731. 

  731. #define SYS_GPE_MFPL_PE1MFP_UART4_nCTS   (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART4_nCTS     \hideinitializer */
    732. 

  732. 

  733. /* PE.2 MFP */
    734. 

  734. #define SYS_GPE_MFPL_PE2MFP_GPIO         (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO       \hideinitializer */
    735. 

  735. #define SYS_GPE_MFPL_PE2MFP_EBI_ALE      (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for EBI_ALE    \hideinitializer */
    736. 

  736. #define SYS_GPE_MFPL_PE2MFP_USCI0_CLK    (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for USCI0_CLK  \hideinitializer */
    737. 

  737. #define SYS_GPE_MFPL_PE2MFP_UART6_nCTS   (0x08UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for UART6_nCTS \hideinitializer */
    738. 

  738. #define SYS_GPE_MFPL_PE2MFP_UART7_RXD    (0x09UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for UART7_RXD  \hideinitializer */
    739. 

  739. #define SYS_GPE_MFPL_PE2MFP_PWM0_CH5     (0x0CUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for PWM0_CH5   \hideinitializer */
    740. 

  740. #define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0    (0x0DUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for BPWM0_CH0  \hideinitializer */
    741. 

  741. 

  742. /* PE.3 MFP */
    743. 

  743. #define SYS_GPE_MFPL_PE3MFP_GPIO         (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO       \hideinitializer */
    744. 

  744. #define SYS_GPE_MFPL_PE3MFP_EBI_MCLK     (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for EBI_MCLK   \hideinitializer */
    745. 

  745. #define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0   (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for USCI0_DAT0 \hideinitializer */
    746. 

  746. #define SYS_GPE_MFPL_PE3MFP_UART6_nRTS   (0x08UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for UART6_nRTS \hideinitializer */
    747. 

  747. #define SYS_GPE_MFPL_PE3MFP_UART7_TXD    (0x09UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for UART7_TXD  \hideinitializer */
    748. 

  748. #define SYS_GPE_MFPL_PE3MFP_PWM0_CH4     (0x0CUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for PWM0_CH4   \hideinitializer */
    749. 

  749. #define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1    (0x0DUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for BPWM0_CH1  \hideinitializer */
    750. 

  750. 

  751. /* PE.4 MFP */
    752. 

  752. #define SYS_GPE_MFPL_PE4MFP_GPIO         (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO       \hideinitializer */
    753. 

  753. #define SYS_GPE_MFPL_PE4MFP_EBI_nWR      (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EBI_nWR    \hideinitializer */
    754. 

  754. #define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1   (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for USCI0_DAT1 \hideinitializer */
    755. 

  755. #define SYS_GPE_MFPL_PE4MFP_UART6_RXD    (0x08UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for UART6_RXD  \hideinitializer */
    756. 

  756. #define SYS_GPE_MFPL_PE4MFP_UART7_nCTS   (0x09UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for UART7_nCTS \hideinitializer */
    757. 

  757. #define SYS_GPE_MFPL_PE4MFP_PWM0_CH3     (0x0CUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for PWM0_CH3   \hideinitializer */
    758. 

  758. #define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2    (0x0DUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for BPWM0_CH2  \hideinitializer */
    759. 

  759. 

  760. /* PE.5 MFP */
    761. 

  761. #define SYS_GPE_MFPL_PE5MFP_GPIO         (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO       \hideinitializer */
    762. 

  762. #define SYS_GPE_MFPL_PE5MFP_EBI_nRD      (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EBI_nRD    \hideinitializer */
    763. 

  763. #define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1   (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for USCI0_CTL1 \hideinitializer */
    764. 

  764. #define SYS_GPE_MFPL_PE5MFP_UART6_TXD    (0x08UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for UART6_TXD  \hideinitializer */
    765. 

  765. #define SYS_GPE_MFPL_PE5MFP_UART7_nRTS   (0x09UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for UART7_nRTS \hideinitializer */
    766. 

  766. #define SYS_GPE_MFPL_PE5MFP_PWM0_CH2     (0x0CUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for PWM0_CH2   \hideinitializer */
    767. 

  767. #define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3    (0x0DUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for BPWM0_CH3  \hideinitializer */
    768. 

  768. 

  769. /* PE.6 MFP */
    770. 

  770. #define SYS_GPE_MFPL_PE6MFP_GPIO         (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO       \hideinitializer */
    771. 

  771. #define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0   (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for USCI0_CTL0 \hideinitializer */
    772. 

  772. #define SYS_GPE_MFPL_PE6MFP_UART5_RXD    (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for UART5_RXD  \hideinitializer */
    773. 

  773. #define SYS_GPE_MFPL_PE6MFP_PWM0_CH1     (0x0CUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for PWM0_CH1   \hideinitializer */
    774. 

  774. #define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4    (0x0DUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for BPWM0_CH4  \hideinitializer */
    775. 

  775. 

  776. /* PE.7 MFP */
    777. 

  777. #define SYS_GPE_MFPL_PE7MFP_GPIO         (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO       \hideinitializer */
    778. 

  778. #define SYS_GPE_MFPL_PE7MFP_UART5_TXD    (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for UART5_TXD  \hideinitializer */
    779. 

  779. #define SYS_GPE_MFPL_PE7MFP_PWM0_CH0     (0x0CUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for PWM0_CH0   \hideinitializer */
    780. 

  780. #define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5    (0x0DUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for BPWM0_CH5  \hideinitializer */
    781. 

  781. 

  782. /* PE.8 MFP */
    783. 

  783. #define SYS_GPE_MFPH_PE8MFP_GPIO         (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO           \hideinitializer */
    784. 

  784. #define SYS_GPE_MFPH_PE8MFP_EBI_ADR10    (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EBI_ADR10      \hideinitializer */
    785. 

  785. #define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1   (0x06UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for USCI1_CTL1     \hideinitializer */
    786. 

  786. #define SYS_GPE_MFPH_PE8MFP_UART2_TXD    (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for UART2_TXD      \hideinitializer */
    787. 

  787. #define SYS_GPE_MFPH_PE8MFP_PWM0_CH0     (0x0AUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for PWM0_CH0       \hideinitializer */
    788. 

  788. #define SYS_GPE_MFPH_PE8MFP_PWM0_BRAKE0  (0x0BUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for PWM0_BRAKE0    \hideinitializer */
    789. 

  789. 

  790. /* PE.9 MFP */
    791. 

  791. #define SYS_GPE_MFPH_PE9MFP_GPIO         (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO           \hideinitializer */
    792. 

  792. #define SYS_GPE_MFPH_PE9MFP_EBI_ADR11    (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EBI_ADR11      \hideinitializer */
    793. 

  793. #define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0   (0x06UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for USCI1_CTL0     \hideinitializer */
    794. 

  794. #define SYS_GPE_MFPH_PE9MFP_UART2_RXD    (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for UART2_RXD      \hideinitializer */
    795. 

  795. #define SYS_GPE_MFPH_PE9MFP_PWM0_CH1     (0x0AUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for PWM0_CH1       \hideinitializer */
    796. 

  796. #define SYS_GPE_MFPH_PE9MFP_PWM0_BRAKE1  (0x0BUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for PWM0_BRAKE1    \hideinitializer */
    797. 

  797. 

  798. /* PE.10 MFP */
    799. 

  799. #define SYS_GPE_MFPH_PE10MFP_GPIO        (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for GPIO          \hideinitializer */
    800. 

  800. #define SYS_GPE_MFPH_PE10MFP_EBI_ADR12   (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for EBI_ADR12     \hideinitializer */
    801. 

  801. #define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0  (0x06UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for USCI1_DAT0    \hideinitializer */
    802. 

  802. #define SYS_GPE_MFPH_PE10MFP_UART3_TXD   (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for UART3_TXD     \hideinitializer */
    803. 

  803. #define SYS_GPE_MFPH_PE10MFP_PWM0_CH2    (0x0AUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for PWM0_CH2      \hideinitializer */
    804. 

  804. #define SYS_GPE_MFPH_PE10MFP_PWM1_BRAKE0 (0x0BUL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for PWM1_BRAKE0    \hideinitializer */
    805. 

  805. 

  806. /* PE.11 MFP */
    807. 

  807. #define SYS_GPE_MFPH_PE11MFP_GPIO        (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for GPIO          \hideinitializer */
    808. 

  808. #define SYS_GPE_MFPH_PE11MFP_EBI_ADR13   (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EBI_ADR13     \hideinitializer */
    809. 

  809. #define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1  (0x06UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for USCI1_DAT1    \hideinitializer */
    810. 

  810. #define SYS_GPE_MFPH_PE11MFP_UART3_RXD   (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for UART3_RXD     \hideinitializer */
    811. 

  811. #define SYS_GPE_MFPH_PE11MFP_UART1_nCTS  (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for UART1_nCTS    \hideinitializer */
    812. 

  812. #define SYS_GPE_MFPH_PE11MFP_PWM0_CH3    (0x0AUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for PWM0_CH3      \hideinitializer */
    813. 

  813. #define SYS_GPE_MFPH_PE11MFP_PWM1_BRAKE1 (0x0BUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for PWM1_BRAKE1   \hideinitializer */
    814. 

  814. 

  815. /* PE.12 MFP */
    816. 

  816. #define SYS_GPE_MFPH_PE12MFP_GPIO        (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for GPIO          \hideinitializer */
    817. 

  817. #define SYS_GPE_MFPH_PE12MFP_EBI_ADR14   (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for EBI_ADR14     \hideinitializer */
    818. 

  818. #define SYS_GPE_MFPH_PE12MFP_USCI1_CLK   (0x06UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for USCI1_CLK     \hideinitializer */
    819. 

  819. #define SYS_GPE_MFPH_PE12MFP_UART1_nRTS  (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for UART1_nRTS    \hideinitializer */
    820. 

  820. #define SYS_GPE_MFPH_PE12MFP_PWM0_CH4    (0x0AUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for PWM0_CH4      \hideinitializer */
    821. 

  821. 

  822. /* PE.13 MFP */
    823. 

  823. #define SYS_GPE_MFPH_PE13MFP_GPIO        (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for GPIO          \hideinitializer */
    824. 

  824. #define SYS_GPE_MFPH_PE13MFP_EBI_ADR15   (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for EBI_ADR15     \hideinitializer */
    825. 

  825. #define SYS_GPE_MFPH_PE13MFP_I2C0_SCL    (0x04UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for I2C0_SCL      \hideinitializer */
    826. 

  826. #define SYS_GPE_MFPH_PE13MFP_UART4_nRTS  (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for UART4_nRTS    \hideinitializer */
    827. 

  827. #define SYS_GPE_MFPH_PE13MFP_UART1_TXD   (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for UART1_TXD     \hideinitializer */
    828. 

  828. #define SYS_GPE_MFPH_PE13MFP_PWM0_CH5    (0x0AUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for PWM0_CH5      \hideinitializer */
    829. 

  829. #define SYS_GPE_MFPH_PE13MFP_PWM1_CH0    (0x0BUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for PWM1_CH0      \hideinitializer */
    830. 

  830. #define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5   (0x0CUL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for BPWM1_CH5     \hideinitializer */
    831. 

  831. 

  832. /* PE.14 MFP */
    833. 

  833. #define SYS_GPE_MFPH_PE14MFP_GPIO        (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for GPIO      \hideinitializer */
    834. 

  834. #define SYS_GPE_MFPH_PE14MFP_EBI_AD8     (0x02UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for EBI_AD8   \hideinitializer */
    835. 

  835. #define SYS_GPE_MFPH_PE14MFP_UART2_TXD   (0x03UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for UART2_TXD \hideinitializer */
    836. 

  836. #define SYS_GPE_MFPH_PE14MFP_UART6_TXD   (0x06UL<<SYS_GPE_MFPH_PE14MFP_Pos)/*!< GPE_MFPH PE14 setting for UART6_TXD \hideinitializer */
    837. 

  837. 

  838. /* PE.15 MFP */
    839. 

  839. #define SYS_GPE_MFPH_PE15MFP_GPIO        (0x00UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for GPIO      \hideinitializer */
    840. 

  840. #define SYS_GPE_MFPH_PE15MFP_EBI_AD9     (0x02UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for EBI_AD9   \hideinitializer */
    841. 

  841. #define SYS_GPE_MFPH_PE15MFP_UART2_RXD   (0x03UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for UART2_RXD \hideinitializer */
    842. 

  842. #define SYS_GPE_MFPH_PE15MFP_UART6_RXD   (0x06UL<<SYS_GPE_MFPH_PE15MFP_Pos)/*!< GPE_MFPH PE15 setting for UART6_RXD \hideinitializer */
    843. 

  843. 

  844. /* PF.0 MFP */
    845. 

  845. #define SYS_GPF_MFPL_PF0MFP_GPIO         (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO        \hideinitializer */
    846. 

  846. #define SYS_GPF_MFPL_PF0MFP_UART1_TXD    (0x02UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for UART1_TXD   \hideinitializer */
    847. 

  847. #define SYS_GPF_MFPL_PF0MFP_I2C1_SCL     (0x03UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for I2C1_SCL    \hideinitializer */
    848. 

  848. #define SYS_GPF_MFPL_PF0MFP_UART0_TXD    (0x04UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for UART0_TXD   \hideinitializer */
    849. 

  849. #define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0    (0x0CUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for BPWM1_CH0   \hideinitializer */
    850. 

  850. #define SYS_GPF_MFPL_PF0MFP_BPWM0_CH5    (0x0DUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for BPWM0_CH5   \hideinitializer */
    851. 

  851. #define SYS_GPF_MFPL_PF0MFP_ICE_DAT      (0x0EUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for ICE_DAT     \hideinitializer */
    852. 

  852. 

  853. /* PF.1 MFP */
    854. 

  854. #define SYS_GPF_MFPL_PF1MFP_GPIO         (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO        \hideinitializer */
    855. 

  855. #define SYS_GPF_MFPL_PF1MFP_UART1_RXD    (0x02UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for UART1_RXD   \hideinitializer */
    856. 

  856. #define SYS_GPF_MFPL_PF1MFP_I2C1_SDA     (0x03UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for I2C1_SDA    \hideinitializer */
    857. 

  857. #define SYS_GPF_MFPL_PF1MFP_UART0_RXD    (0x04UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for UART0_RXD   \hideinitializer */
    858. 

  858. #define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1    (0x0CUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for BPWM1_CH1   \hideinitializer */
    859. 

  859. #define SYS_GPF_MFPL_PF1MFP_BPWM0_CH4    (0x0DUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for BPWM0_CH4   \hideinitializer */
    860. 

  860. #define SYS_GPF_MFPL_PF1MFP_ICE_CLK      (0x0EUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for ICE_CLK     \hideinitializer */
    861. 

  861. 

  862. /* PF.2 MFP */
    863. 

  863. #define SYS_GPF_MFPL_PF2MFP_GPIO         (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO        \hideinitializer */
    864. 

  864. #define SYS_GPF_MFPL_PF2MFP_EBI_nCS1     (0x02UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for EBI_nCS1    \hideinitializer */
    865. 

  865. #define SYS_GPF_MFPL_PF2MFP_UART0_RXD    (0x03UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for UART0_RXD   \hideinitializer */
    866. 

  866. #define SYS_GPF_MFPL_PF2MFP_I2C0_SDA     (0x04UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for I2C0_SDA    \hideinitializer */
    867. 

  867. #define SYS_GPF_MFPL_PF2MFP_QSPI0_CLK    (0x05UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for QSPI0_CLK   \hideinitializer */
    868. 

  868. #define SYS_GPF_MFPL_PF2MFP_XT1_OUT      (0x0AUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for XT1_OUT     \hideinitializer */
    869. 

  869. #define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1    (0x0BUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for BPWM1_CH1   \hideinitializer */
    870. 

  870. #define SYS_GPF_MFPL_PF2MFP_USCI1_CTL1   (0x0CUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for USCI1_CTL1  \hideinitializer */
    871. 

  871. 

  872. /* PF.3 MFP */
    873. 

  873. #define SYS_GPF_MFPL_PF3MFP_GPIO         (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO        \hideinitializer */
    874. 

  874. #define SYS_GPF_MFPL_PF3MFP_EBI_nCS0     (0x02UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for EBI_nCS0    \hideinitializer */
    875. 

  875. #define SYS_GPF_MFPL_PF3MFP_UART0_TXD    (0x03UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for UART0_TXD   \hideinitializer */
    876. 

  876. #define SYS_GPF_MFPL_PF3MFP_I2C0_SCL     (0x04UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for I2C0_SCL    \hideinitializer */
    877. 

  877. #define SYS_GPF_MFPL_PF3MFP_XT1_IN       (0x0AUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for XT1_IN      \hideinitializer */
    878. 

  878. #define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0    (0x0BUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for BPWM1_CH0   \hideinitializer */
    879. 

  879. #define SYS_GPF_MFPL_PF3MFP_USCI1_CTL0   (0x0CUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for USCI1_CTL0  \hideinitializer */
    880. 

  880. 

  881. /* PF.4 MFP */
    882. 

  882. #define SYS_GPF_MFPL_PF4MFP_GPIO         (0x00UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO        \hideinitializer */
    883. 

  883. #define SYS_GPF_MFPL_PF4MFP_UART2_TXD    (0x02UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for UART2_TXD   \hideinitializer */
    884. 

  884. #define SYS_GPF_MFPL_PF4MFP_QSPI0_MOSI1  (0x03UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for QSPI0_MOSI1 \hideinitializer */
    885. 

  885. #define SYS_GPF_MFPL_PF4MFP_UART2_nRTS   (0x04UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for UART2_nRTS  \hideinitializer */
    886. 

  886. #define SYS_GPF_MFPL_PF4MFP_PWM0_CH1     (0x07UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for PWM0_CH1    \hideinitializer */
    887. 

  887. #define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5    (0x08UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for BPWM0_CH5   \hideinitializer */
    888. 

  888. #define SYS_GPF_MFPL_PF4MFP_X32_OUT      (0x0AUL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for X32_OUT     \hideinitializer */
    889. 

  889. 

  890. /* PF.5 MFP */
    891. 

  891. #define SYS_GPF_MFPL_PF5MFP_GPIO         (0x00UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO        \hideinitializer */
    892. 

  892. #define SYS_GPF_MFPL_PF5MFP_UART2_RXD    (0x02UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for UART2_RXD   \hideinitializer */
    893. 

  893. #define SYS_GPF_MFPL_PF5MFP_QSPI0_MISO1  (0x03UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for QSPI0_MISO1 \hideinitializer */
    894. 

  894. #define SYS_GPF_MFPL_PF5MFP_UART2_nCTS   (0x04UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for UART2_nCTS  \hideinitializer */
    895. 

  895. #define SYS_GPF_MFPL_PF5MFP_PWM0_CH0     (0x07UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for PWM0_CH0    \hideinitializer */
    896. 

  896. #define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4    (0x08UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for BPWM0_CH4   \hideinitializer */
    897. 

  897. #define SYS_GPF_MFPL_PF5MFP_X32_IN       (0x0AUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for X32_IN      \hideinitializer */
    898. 

  898. #define SYS_GPF_MFPL_PF5MFP_ADC_ST       (0x0BUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for ADC_ST      \hideinitializer */
    899. 

  899. #define SYS_GPF_MFPL_PF5MFP_ADC0_ST      (0x0BUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for ADC0_ST     \hideinitializer */
    900. 

  900. 

  901. /* PF.6 MFP */
    902. 

  902. #define SYS_GPF_MFPL_PF6MFP_GPIO         (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO        \hideinitializer */
    903. 

  903. #define SYS_GPF_MFPL_PF6MFP_EBI_ADR19    (0x02UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EBI_ADR19   \hideinitializer */
    904. 

  904. #define SYS_GPF_MFPL_PF6MFP_SPI0_MOSI    (0x05UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SPI0_MOSI   \hideinitializer */
    905. 

  905. #define SYS_GPF_MFPL_PF6MFP_UART4_RXD    (0x06UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for UART4_RXD   \hideinitializer */
    906. 

  906. #define SYS_GPF_MFPL_PF6MFP_EBI_nCS0     (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EBI_nCS0    \hideinitializer */
    907. 

  907. 

  908. /* PF.7 MFP */
    909. 

  909. #define SYS_GPF_MFPL_PF7MFP_GPIO         (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO       \hideinitializer */
    910. 

  910. #define SYS_GPF_MFPL_PF7MFP_EBI_ADR18    (0x02UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for EBI_ADR18  \hideinitializer */
    911. 

  911. #define SYS_GPF_MFPL_PF7MFP_SPI0_MISO    (0x05UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for SPI0_MISO  \hideinitializer */
    912. 

  912. #define SYS_GPF_MFPL_PF7MFP_UART4_TXD    (0x06UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for UART4_TXD  \hideinitializer */
    913. 

  913. 

  914. /* PF.8 MFP */
    915. 

  915. #define SYS_GPF_MFPH_PF8MFP_GPIO         (0x00UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for GPIO       \hideinitializer */
    916. 

  916. #define SYS_GPF_MFPH_PF8MFP_EBI_ADR17    (0x02UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for EBI_ADR17  \hideinitializer */
    917. 

  917. #define SYS_GPF_MFPH_PF8MFP_SPI0_CLK     (0x05UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for SPI0_CLK   \hideinitializer */
    918. 

  918. #define SYS_GPF_MFPH_PF8MFP_UART5_nCTS   (0x06UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for UART5_nCTS \hideinitializer */
    919. 

  919. 

  920. /* PF.9 MFP */
    921. 

  921. #define SYS_GPF_MFPH_PF9MFP_GPIO         (0x00UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for GPIO       \hideinitializer */
    922. 

  922. #define SYS_GPF_MFPH_PF9MFP_EBI_ADR16    (0x02UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for EBI_ADR16  \hideinitializer */
    923. 

  923. #define SYS_GPF_MFPH_PF9MFP_SPI0_SS      (0x05UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for SPI0_SS    \hideinitializer */
    924. 

  924. #define SYS_GPF_MFPH_PF9MFP_UART5_nRTS   (0x06UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for UART5_nRTS \hideinitializer */
    925. 

  925. 

  926. /* PF.10 MFP */
    927. 

  927. #define SYS_GPF_MFPH_PF10MFP_GPIO         (0x00UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for GPIO         \hideinitializer */
    928. 

  928. #define SYS_GPF_MFPH_PF10MFP_EBI_ADR15    (0x02UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for EBI_ADR15    \hideinitializer */
    929. 

  929. #define SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for SPI0_I2SMCLK \hideinitializer */
    930. 

  930. #define SYS_GPF_MFPH_PF10MFP_UART5_RXD    (0x06UL<<SYS_GPF_MFPH_PF10MFP_Pos)/*!< GPF_MFPH PF10 setting for UART5_RXD    \hideinitializer */
    931. 

  931. 

  932. /* PF.11 MFP */
    933. 

  933. #define SYS_GPF_MFPH_PF11MFP_GPIO        (0x00UL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for GPIO      \hideinitializer */
    934. 

  934. #define SYS_GPF_MFPH_PF11MFP_EBI_ADR14   (0x02UL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for EBI_ADR14 \hideinitializer */
    935. 

  935. #define SYS_GPF_MFPH_PF11MFP_UART5_TXD   (0x06UL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for UART5_TXD \hideinitializer */
    936. 

  936. #define SYS_GPF_MFPH_PF11MFP_TM3         (0x0DUL<<SYS_GPF_MFPH_PF11MFP_Pos)/*!< GPF_MFPH PF11 setting for TM3       \hideinitializer */
    937. 

  937. 

  938. /* PF.12 MFP */
    939. 

  939. 

  940. /* PF.13 MFP */
    941. 

  941. 

  942. /* PF.14 MFP \hideinitializer */
    943. 

  943. #define SYS_GPF_MFPH_PF14MFP_GPIO        (0x00UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for GPIO        \hideinitializer */
    944. 

  944. #define SYS_GPF_MFPH_PF14MFP_PWM1_BRAKE0 (0x09UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for PWM1_BRAKE0 \hideinitializer */
    945. 

  945. #define SYS_GPF_MFPH_PF14MFP_PWM0_BRAKE0 (0x0AUL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for PWM0_BRAKE0 \hideinitializer */
    946. 

  946. #define SYS_GPF_MFPH_PF14MFP_PWM0_CH4    (0x0CUL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for PWM0_CH4    \hideinitializer */
    947. 

  947. #define SYS_GPF_MFPH_PF14MFP_CLKO        (0x0DUL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for CLKO        \hideinitializer */
    948. 

  948. #define SYS_GPF_MFPH_PF14MFP_TM3         (0x0EUL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for TM3         \hideinitializer */
    949. 

  949. #define SYS_GPF_MFPH_PF14MFP_INT5        (0x0FUL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for INT5        \hideinitializer */
    950. 

  950. 

  951. /* PF.15 MFP */
    952. 

  952. #define SYS_GPF_MFPH_PF15MFP_GPIO        (0x00UL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for GPIO        \hideinitializer */
    953. 

  953. #define SYS_GPF_MFPH_PF15MFP_PWM0_BRAKE0 (0x0BUL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for PWM0_BRAKE0 \hideinitializer */
    954. 

  954. #define SYS_GPF_MFPH_PF15MFP_PWM0_CH1    (0x0CUL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for PWM0_CH1    \hideinitializer */
    955. 

  955. #define SYS_GPF_MFPH_PF15MFP_TM2         (0x0DUL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for TM2         \hideinitializer */
    956. 

  956. #define SYS_GPF_MFPH_PF15MFP_CLKO        (0x0EUL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for CLKO        \hideinitializer */
    957. 

  957. #define SYS_GPF_MFPH_PF15MFP_INT4        (0x0FUL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for INT4        \hideinitializer */
    958. 

  958. 

  959. /* PG.0 MFP */
    960. 

  960. 

  961. /* PG.1 MFP */
    962. 

  962. 

  963. /* PG.2 MFP */
    964. 

  964. #define SYS_GPG_MFPL_PG2MFP_GPIO         (0x00UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for GPIO       \hideinitializer */
    965. 

  965. #define SYS_GPG_MFPL_PG2MFP_EBI_ADR11    (0x02UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for EBI_ADR11  \hideinitializer */
    966. 

  966. #define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL   (0x04UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for I2C0_SMBAL \hideinitializer */
    967. 

  967. #define SYS_GPG_MFPL_PG2MFP_I2C1_SCL     (0x05UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for I2C1_SCL   \hideinitializer */
    968. 

  968. #define SYS_GPG_MFPL_PG2MFP_TM0          (0x0DUL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for TM0        \hideinitializer */
    969. 

  969. 

  970. /* PG.3 MFP */
    971. 

  971. #define SYS_GPG_MFPL_PG3MFP_GPIO         (0x00UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for GPIO       \hideinitializer */
    972. 

  972. #define SYS_GPG_MFPL_PG3MFP_EBI_ADR12    (0x02UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for EBI_ADR12  \hideinitializer */
    973. 

  973. #define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS  (0x04UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2C0_SMBSUS \hideinitializer */
    974. 

  974. #define SYS_GPG_MFPL_PG3MFP_I2C1_SDA     (0x05UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2C1_SDA   \hideinitializer */
    975. 

  975. #define SYS_GPG_MFPL_PG3MFP_TM1          (0x0DUL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for TM1        \hideinitializer */
    976. 

  976. 

  977. /* PG.4 MFP */
    978. 

  978. #define SYS_GPG_MFPL_PG4MFP_GPIO         (0x00UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for GPIO       \hideinitializer */
    979. 

  979. #define SYS_GPG_MFPL_PG4MFP_EBI_ADR13    (0x02UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for EBI_ADR13  \hideinitializer */
    980. 

  980. #define SYS_GPG_MFPL_PG4MFP_TM2          (0x0DUL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for TM2        \hideinitializer */
    981. 

  981. 

  982. /* PG.5 MFP */
    983. 

  983. 

  984. /* PG.6 MFP */
    985. 

  985. 

  986. /* PG.7 MFP */
    987. 

  987. 

  988. /* PG.8 MFP */
    989. 

  989. 

  990. /* PG.9 MFP */
    991. 

  991. #define SYS_GPG_MFPH_PG9MFP_GPIO         (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for GPIO       \hideinitializer */
    992. 

  992. #define SYS_GPG_MFPH_PG9MFP_EBI_AD0      (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for EBI_AD0    \hideinitializer */
    993. 

  993. #define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5    (0x0CUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for BPWM0_CH5  \hideinitializer */
    994. 

  994. 

  995. /* PG.10 MFP */
    996. 

  996. #define SYS_GPG_MFPH_PG10MFP_GPIO        (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for GPIO      \hideinitializer */
    997. 

  997. #define SYS_GPG_MFPH_PG10MFP_EBI_AD1     (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for EBI_AD1   \hideinitializer */
    998. 

  998. #define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4   (0x0CUL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for BPWM0_CH4 \hideinitializer */
    999. 

  999. 

  1000. /* PG.11 MFP */
    1001. 

  1001. #define SYS_GPG_MFPH_PG11MFP_GPIO        (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for GPIO      \hideinitializer */
    1002. 

  1002. #define SYS_GPG_MFPH_PG11MFP_EBI_AD2     (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for EBI_AD2   \hideinitializer */
    1003. 

  1003. #define SYS_GPG_MFPH_PG11MFP_UART7_TXD   (0x06UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for UART7_TXD \hideinitializer */
    1004. 

  1004. #define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3   (0x0CUL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for BPWM0_CH3 \hideinitializer */
    1005. 

  1005. 

  1006. /* PG.12 MFP */
    1007. 

  1007. #define SYS_GPG_MFPH_PG12MFP_GPIO        (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for GPIO      \hideinitializer */
    1008. 

  1008. #define SYS_GPG_MFPH_PG12MFP_EBI_AD3     (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for EBI_AD3   \hideinitializer */
    1009. 

  1009. #define SYS_GPG_MFPH_PG12MFP_UART7_RXD   (0x06UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for UART7_RXD \hideinitializer */
    1010. 

  1010. #define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2   (0x0CUL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for BPWM0_CH2 \hideinitializer */
    1011. 

  1011. 

  1012. /* PG.13 MFP */
    1013. 

  1013. #define SYS_GPG_MFPH_PG13MFP_GPIO        (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for GPIO      \hideinitializer */
    1014. 

  1014. #define SYS_GPG_MFPH_PG13MFP_EBI_AD4     (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for EBI_AD4   \hideinitializer */
    1015. 

  1015. #define SYS_GPG_MFPH_PG13MFP_UART6_TXD   (0x06UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for UART6_TXD \hideinitializer */
    1016. 

  1016. #define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1   (0x0CUL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for BPWM0_CH1 \hideinitializer */
    1017. 

  1017. 

  1018. /* PG.14 MFP */
    1019. 

  1019. #define SYS_GPG_MFPH_PG14MFP_GPIO        (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for GPIO      \hideinitializer */
    1020. 

  1020. #define SYS_GPG_MFPH_PG14MFP_EBI_AD5     (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for EBI_AD5   \hideinitializer */
    1021. 

  1021. #define SYS_GPG_MFPH_PG14MFP_UART6_RXD   (0x06UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for UART6_RXD \hideinitializer */
    1022. 

  1022. #define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0   (0x0CUL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for BPWM0_CH0 \hideinitializer */
    1023. 

  1023. 

  1024. /* PG.15 MFP */
    1025. 

  1025. #define SYS_GPG_MFPH_PG15MFP_GPIO        (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for GPIO      \hideinitializer */
    1026. 

  1026. #define SYS_GPG_MFPH_PG15MFP_CLKO        (0x0EUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for CLKO      \hideinitializer */
    1027. 

  1027. #define SYS_GPG_MFPH_PG15MFP_ADC_ST      (0x0FUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for ADC_ST    \hideinitializer */
    1028. 

  1028. #define SYS_GPG_MFPH_PG15MFP_ADC0_ST     (0x0FUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for ADC0_ST   \hideinitializer */
    1029. 

  1029. 

  1030. /* PH.0 MFP */
    1031. 

  1031. 

  1032. /* PH.1 MFP */
    1033. 

  1033. 

  1034. /* PH.2 MFP */
    1035. 

  1035. 

  1036. /* PH.3 MFP */
    1037. 

  1037. 

  1038. /* PH.4 MFP */
    1039. 

  1039. #define SYS_GPH_MFPL_PH4MFP_GPIO         (0x00UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for GPIO       \hideinitializer */
    1040. 

  1040. #define SYS_GPH_MFPL_PH4MFP_EBI_ADR3     (0x02UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for EBI_ADR3   \hideinitializer */
    1041. 

  1041. #define SYS_GPH_MFPL_PH4MFP_UART7_nRTS   (0x04UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for UART7_nRTS \hideinitializer */
    1042. 

  1042. #define SYS_GPH_MFPL_PH4MFP_UART6_TXD    (0x05UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for UART6_TXD  \hideinitializer */
    1043. 

  1043. 

  1044. /* PH.5 MFP */
    1045. 

  1045. #define SYS_GPH_MFPL_PH5MFP_GPIO         (0x00UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for GPIO       \hideinitializer */
    1046. 

  1046. #define SYS_GPH_MFPL_PH5MFP_EBI_ADR2     (0x02UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for EBI_ADR2   \hideinitializer */
    1047. 

  1047. #define SYS_GPH_MFPL_PH5MFP_UART7_nCTS   (0x04UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for UART7_nCTS \hideinitializer */
    1048. 

  1048. #define SYS_GPH_MFPL_PH5MFP_UART6_RXD    (0x05UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for UART6_RXD  \hideinitializer */
    1049. 

  1049. 

  1050. /* PH.6 MFP */
    1051. 

  1051. #define SYS_GPH_MFPL_PH6MFP_GPIO         (0x00UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for GPIO       \hideinitializer */
    1052. 

  1052. #define SYS_GPH_MFPL_PH6MFP_EBI_ADR1     (0x02UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for EBI_ADR1   \hideinitializer */
    1053. 

  1053. #define SYS_GPH_MFPL_PH6MFP_UART7_TXD    (0x04UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for UART7_TXD  \hideinitializer */
    1054. 

  1054. 

  1055. /* PH.7 MFP */
    1056. 

  1056. #define SYS_GPH_MFPL_PH7MFP_GPIO         (0x00UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for GPIO       \hideinitializer */
    1057. 

  1057. #define SYS_GPH_MFPL_PH7MFP_EBI_ADR0     (0x02UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for EBI_ADR0   \hideinitializer */
    1058. 

  1058. #define SYS_GPH_MFPL_PH7MFP_UART7_RXD    (0x04UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for UART7_RXD  \hideinitializer */
    1059. 

  1059. 

  1060. /* PH.8 MFP */
    1061. 

  1061. #define SYS_GPH_MFPH_PH8MFP_GPIO         (0x00UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for GPIO       \hideinitializer */
    1062. 

  1062. #define SYS_GPH_MFPH_PH8MFP_EBI_AD12     (0x02UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for EBI_AD12   \hideinitializer */
    1063. 

  1063. #define SYS_GPH_MFPH_PH8MFP_QSPI0_CLK    (0x03UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for QSPI0_CLK  \hideinitializer */
    1064. 

  1064. #define SYS_GPH_MFPH_PH8MFP_UART3_nRTS   (0x07UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for UART3_nRTS \hideinitializer */
    1065. 

  1065. #define SYS_GPH_MFPH_PH8MFP_UART1_TXD    (0x0AUL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for UART1_TXD  \hideinitializer */
    1066. 

  1066. 

  1067. /* PH.9 MFP */
    1068. 

  1068. #define SYS_GPH_MFPH_PH9MFP_GPIO         (0x00UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for GPIO       \hideinitializer */
    1069. 

  1069. #define SYS_GPH_MFPH_PH9MFP_EBI_AD13     (0x02UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for EBI_AD13   \hideinitializer */
    1070. 

  1070. #define SYS_GPH_MFPH_PH9MFP_QSPI0_SS     (0x03UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for QSPI0_SS   \hideinitializer */
    1071. 

  1071. #define SYS_GPH_MFPH_PH9MFP_UART3_nCTS   (0x07UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for UART3_nCTS \hideinitializer */
    1072. 

  1072. #define SYS_GPH_MFPH_PH9MFP_UART1_RXD    (0x0AUL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for UART1_RXD  \hideinitializer */
    1073. 

  1073. 

  1074. /* PH.10 MFP */
    1075. 

  1075. #define SYS_GPH_MFPH_PH10MFP_GPIO        (0x00UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for GPIO          \hideinitializer */
    1076. 

  1076. #define SYS_GPH_MFPH_PH10MFP_EBI_AD14    (0x02UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for EBI_AD14      \hideinitializer */
    1077. 

  1077. #define SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 (0x03UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for QSPI0_MISO1   \hideinitializer */
    1078. 

  1078. #define SYS_GPH_MFPH_PH10MFP_UART4_TXD   (0x07UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for UART4_TXD     \hideinitializer */
    1079. 

  1079. #define SYS_GPH_MFPH_PH10MFP_UART0_TXD   (0x08UL<<SYS_GPH_MFPH_PH10MFP_Pos)/*!< GPH_MFPH PH10 setting for UART0_TXD     \hideinitializer */
    1080. 

  1080. 

  1081. /* PH.11 MFP */
    1082. 

  1082. #define SYS_GPH_MFPH_PH11MFP_GPIO        (0x00UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for GPIO          \hideinitializer */
    1083. 

  1083. #define SYS_GPH_MFPH_PH11MFP_EBI_AD15    (0x02UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for EBI_AD15      \hideinitializer */
    1084. 

  1084. #define SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 (0x03UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for QSPI0_MOSI1   \hideinitializer */
    1085. 

  1085. #define SYS_GPH_MFPH_PH11MFP_UART4_RXD   (0x07UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for UART4_RXD     \hideinitializer */
    1086. 

  1086. #define SYS_GPH_MFPH_PH11MFP_UART0_RXD   (0x08UL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for UART0_RXD     \hideinitializer */
    1087. 

  1087. #define SYS_GPH_MFPH_PH11MFP_PWM0_CH5    (0x0BUL<<SYS_GPH_MFPH_PH11MFP_Pos)/*!< GPH_MFPH PH11 setting for PWM0_CH5      \hideinitializer */
    1088. 

  1088. 

  1089. /* PH.12 MFP */
    1090. 

  1090. 

  1091. /* PH.13 MFP */
    1092. 

  1092. 

  1093. /* PH.14 MFP */
    1094. 

  1094. 

  1095. /* PH.15 MFP */
    1096. 

  1096. 

  1097. 

  1098. /*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
    1099. 

  1099. 

  1100. /** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
    1101. 

  1101.   @{
    1102. 

  1102. */
    1103. 

  1103. 

  1104. 

  1105. /**
    1106. 

  1106.   * @brief      Clear Brown-out detector interrupt flag
    1107. 

  1107.   * @param      None
    1108. 

  1108.   * @return     None
    1109. 

  1109.   * @details    This macro clear Brown-out detector interrupt flag.
    1110. 

  1110.   * \hideinitializer
    1111. 

  1111.   */
    1112. 

  1112. #define SYS_CLEAR_BOD_INT_FLAG()        (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
    1113. 

  1113. 

  1114. /**
    1115. 

  1115.   * @brief      Set Brown-out detector function to normal mode
    1116. 

  1116.   * @param      None
    1117. 

  1117.   * @return     None
    1118. 

  1118.   * @details    This macro set Brown-out detector to normal mode.
    1119. 

  1119.   *             The register write-protection function should be disabled before using this macro.
    1120. 

  1120.   * \hideinitializer
    1121. 

  1121.   */
    1122. 

  1122. #define SYS_CLEAR_BOD_LPM()             (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
    1123. 

  1123. 

  1124. /**
    1125. 

  1125.   * @brief      Disable Brown-out detector function
    1126. 

  1126.   * @param      None
    1127. 

  1127.   * @return     None
    1128. 

  1128.   * @details    This macro disable Brown-out detector function.
    1129. 

  1129.   *             The register write-protection function should be disabled before using this macro.
    1130. 

  1130.   * \hideinitializer
    1131. 

  1131.   */
    1132. 

  1132. #define SYS_DISABLE_BOD()               (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
    1133. 

  1133. 

  1134. /**
    1135. 

  1135.   * @brief      Enable Brown-out detector function
    1136. 

  1136.   * @param      None
    1137. 

  1137.   * @return     None
    1138. 

  1138.   * @details    This macro enable Brown-out detector function.
    1139. 

  1139.   *             The register write-protection function should be disabled before using this macro.
    1140. 

  1140.   * \hideinitializer
    1141. 

  1141.   */
    1142. 

  1142. #define SYS_ENABLE_BOD()                (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
    1143. 

  1143. 

  1144. /**
    1145. 

  1145.   * @brief      Get Brown-out detector interrupt flag
    1146. 

  1146.   * @param      None
    1147. 

  1147.   * @retval     0   Brown-out detect interrupt flag is not set.
    1148. 

  1148.   * @retval     >=1 Brown-out detect interrupt flag is set.
    1149. 

  1149.   * @details    This macro get Brown-out detector interrupt flag.
    1150. 

  1150.   * \hideinitializer
    1151. 

  1151.   */
    1152. 

  1152. #define SYS_GET_BOD_INT_FLAG()          (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
    1153. 

  1153. 

  1154. /**
    1155. 

  1155.   * @brief      Get Brown-out detector status
    1156. 

  1156.   * @param      None
    1157. 

  1157.   * @retval     0   System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
    1158. 

  1158.   * @retval     >=1 System voltage is lower than BOD threshold voltage setting.
    1159. 

  1159.   * @details    This macro get Brown-out detector output status.
    1160. 

  1160.   *             If the BOD function is disabled, this function always return 0.
    1161. 

  1161.   * \hideinitializer
    1162. 

  1162.   */
    1163. 

  1163. #define SYS_GET_BOD_OUTPUT()            (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
    1164. 

  1164. 

  1165. /**
    1166. 

  1166.   * @brief      Disable Brown-out detector reset function
    1167. 

  1167.   * @param      None
    1168. 

  1168.   * @return     None
    1169. 

  1169.   * @details    This macro disable Brown-out detector reset function.
    1170. 

  1170.   *             The register write-protection function should be disabled before using this macro.
    1171. 

  1171.   * \hideinitializer
    1172. 

  1172.   */
    1173. 

  1173. #define SYS_DISABLE_BOD_RST()           (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
    1174. 

  1174. 

  1175. /**
    1176. 

  1176.   * @brief      Enable Brown-out detector reset function
    1177. 

  1177.   * @param      None
    1178. 

  1178.   * @return     None
    1179. 

  1179.   * @details    This macro enable Brown-out detect reset function.
    1180. 

  1180.   *             The register write-protection function should be disabled before using this macro.
    1181. 

  1181.   * \hideinitializer
    1182. 

  1182.   */
    1183. 

  1183. #define SYS_ENABLE_BOD_RST()            (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
    1184. 

  1184. 

  1185. /**
    1186. 

  1186.   * @brief      Set Brown-out detector function low power mode
    1187. 

  1187.   * @param      None
    1188. 

  1188.   * @return     None
    1189. 

  1189.   * @details    This macro set Brown-out detector to low power mode.
    1190. 

  1190.   *             The register write-protection function should be disabled before using this macro.
    1191. 

  1191.   * \hideinitializer
    1192. 

  1192.   */
    1193. 

  1193. #define SYS_SET_BOD_LPM()               (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
    1194. 

  1194. 

  1195. /**
    1196. 

  1196.   * @brief      Set Brown-out detector voltage level
    1197. 

  1197.   * @param[in]  u32Level is Brown-out voltage level. Including :
    1198. 

  1198.   *             - \ref SYS_BODCTL_BODVL_2_5V
    1199. 

  1199.   *             - \ref SYS_BODCTL_BODVL_2_0V
    1200. 

  1200.   * @return     None
    1201. 

  1201.   * @details    This macro set Brown-out detector voltage level.
    1202. 

  1202.   *             The write-protection function should be disabled before using this macro.
    1203. 

  1203.   * \hideinitializer
    1204. 

  1204.   */
    1205. 

  1205. #define SYS_SET_BOD_LEVEL(u32Level)     (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
    1206. 

  1206. 

  1207. /**
    1208. 

  1208.   * @brief      Get reset source is from Brown-out detector reset
    1209. 

  1209.   * @param      None
    1210. 

  1210.   * @retval     0   Previous reset source is not from Brown-out detector reset
    1211. 

  1211.   * @retval     >=1 Previous reset source is from Brown-out detector reset
    1212. 

  1212.   * @details    This macro get previous reset source is from Brown-out detect reset or not.
    1213. 

  1213.   * \hideinitializer
    1214. 

  1214.   */
    1215. 

  1215. #define SYS_IS_BOD_RST()                (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
    1216. 

  1216. 

  1217. /**
    1218. 

  1218.   * @brief      Get reset source is from CPU reset
    1219. 

  1219.   * @param      None
    1220. 

  1220.   * @retval     0   Previous reset source is not from CPU reset
    1221. 

  1221.   * @retval     >=1 Previous reset source is from CPU reset
    1222. 

  1222.   * @details    This macro get previous reset source is from CPU reset.
    1223. 

  1223.   * \hideinitializer
    1224. 

  1224.   */
    1225. 

  1225. #define SYS_IS_CPU_RST()                (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
    1226. 

  1226. 

  1227. /**
    1228. 

  1228.   * @brief      Get reset source is from LVR Reset
    1229. 

  1229.   * @param      None
    1230. 

  1230.   * @retval     0   Previous reset source is not from Low-Voltage-Reset
    1231. 

  1231.   * @retval     >=1 Previous reset source is from Low-Voltage-Reset
    1232. 

  1232.   * @details    This macro get previous reset source is from Low-Voltage-Reset.
    1233. 

  1233.   * \hideinitializer
    1234. 

  1234.   */
    1235. 

  1235. #define SYS_IS_LVR_RST()                (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
    1236. 

  1236. 

  1237. /**
    1238. 

  1238.   * @brief      Get reset source is from Power-on Reset
    1239. 

  1239.   * @param      None
    1240. 

  1240.   * @retval     0   Previous reset source is not from Power-on Reset
    1241. 

  1241.   * @retval     >=1 Previous reset source is from Power-on Reset
    1242. 

  1242.   * @details    This macro get previous reset source is from Power-on Reset.
    1243. 

  1243.   * \hideinitializer
    1244. 

  1244.   */
    1245. 

  1245. #define SYS_IS_POR_RST()                (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
    1246. 

  1246. 

  1247. /**
    1248. 

  1248.   * @brief      Get reset source is from reset pin reset
    1249. 

  1249.   * @param      None
    1250. 

  1250.   * @retval     0   Previous reset source is not from reset pin reset
    1251. 

  1251.   * @retval     >=1 Previous reset source is from reset pin reset
    1252. 

  1252.   * @details    This macro get previous reset source is from reset pin reset.
    1253. 

  1253.   * \hideinitializer
    1254. 

  1254.   */
    1255. 

  1255. #define SYS_IS_RSTPIN_RST()             (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
    1256. 

  1256. 

  1257. /**
    1258. 

  1258.   * @brief      Get reset source is from system reset
    1259. 

  1259.   * @param      None
    1260. 

  1260.   * @retval     0   Previous reset source is not from system reset
    1261. 

  1261.   * @retval     >=1 Previous reset source is from system reset
    1262. 

  1262.   * @details    This macro get previous reset source is from system reset.
    1263. 

  1263.   * \hideinitializer
    1264. 

  1264.   */
    1265. 

  1265. #define SYS_IS_SYSTEM_RST()             (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
    1266. 

  1266. 

  1267. /**
    1268. 

  1268.   * @brief      Get reset source is from watchdog timer or window watchdog timer reset
    1269. 

  1269.   * @param      None
    1270. 

  1270.   * @retval     0   Previous reset source is not from watchdog timer or window watchdog timer reset
    1271. 

  1271.   * @retval     >=1 Previous reset source is from watchdog timer or window watchdog timer reset
    1272. 

  1272.   * @details    This macro get previous reset source is from watchdog timer or window watchdog timer reset.
    1273. 

  1273.   * \hideinitializer
    1274. 

  1274.   */
    1275. 

  1275. #define SYS_IS_WDT_RST()                (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
    1276. 

  1276. 

  1277. /**
    1278. 

  1278.   * @brief      Disable Low-Voltage-Reset function
    1279. 

  1279.   * @param      None
    1280. 

  1280.   * @return     None
    1281. 

  1281.   * @details    This macro disable Low-Voltage-Reset function.
    1282. 

  1282.   *             The register write-protection function should be disabled before using this macro.
    1283. 

  1283.   * \hideinitializer
    1284. 

  1284.   */
    1285. 

  1285. #define SYS_DISABLE_LVR()               (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
    1286. 

  1286. 

  1287. /**
    1288. 

  1288.   * @brief      Enable Low-Voltage-Reset function
    1289. 

  1289.   * @param      None
    1290. 

  1290.   * @return     None
    1291. 

  1291.   * @details    This macro enable Low-Voltage-Reset function.
    1292. 

  1292.   *             The register write-protection function should be disabled before using this macro.
    1293. 

  1293.   * \hideinitializer
    1294. 

  1294.   */
    1295. 

  1295. #define SYS_ENABLE_LVR()                (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
    1296. 

  1296. 

  1297. /**
    1298. 

  1298.   * @brief      Disable Power-on Reset function
    1299. 

  1299.   * @param      None
    1300. 

  1300.   * @return     None
    1301. 

  1301.   * @details    This macro disable Power-on Reset function.
    1302. 

  1302.   *             The register write-protection function should be disabled before using this macro.
    1303. 

  1303.   * \hideinitializer
    1304. 

  1304.   */
    1305. 

  1305. #define SYS_DISABLE_POR()               (SYS->PORCTL = 0x5AA5)
    1306. 

  1306. 

  1307. /**
    1308. 

  1308.   * @brief      Enable Power-on Reset function
    1309. 

  1309.   * @param      None
    1310. 

  1310.   * @return     None
    1311. 

  1311.   * @details    This macro enable Power-on Reset function.
    1312. 

  1312.   *             The register write-protection function should be disabled before using this macro.
    1313. 

  1313.   * \hideinitializer
    1314. 

  1314.   */
    1315. 

  1315. #define SYS_ENABLE_POR()                (SYS->PORCTL = 0)
    1316. 

  1316. 

  1317. /**
    1318. 

  1318.   * @brief      Clear reset source flag
    1319. 

  1319.   * @param[in]  u32RstSrc is reset source. Including :
    1320. 

  1320.   *             - \ref SYS_RSTSTS_PORF_Msk
    1321. 

  1321.   *             - \ref SYS_RSTSTS_PINRF_Msk
    1322. 

  1322.   *             - \ref SYS_RSTSTS_WDTRF_Msk
    1323. 

  1323.   *             - \ref SYS_RSTSTS_LVRF_Msk
    1324. 

  1324.   *             - \ref SYS_RSTSTS_BODRF_Msk
    1325. 

  1325.   *             - \ref SYS_RSTSTS_SYSRF_Msk
    1326. 

  1326.   *             - \ref SYS_RSTSTS_CPURF_Msk
    1327. 

  1327.   *             - \ref SYS_RSTSTS_CPULKRF_Msk
    1328. 

  1328.   * @return     None
    1329. 

  1329.   * @details    This macro clear reset source flag.
    1330. 

  1330.   * \hideinitializer
    1331. 

  1331.   */
    1332. 

  1332. #define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
    1333. 

  1333. 

  1334. 

  1335. /**
    1336. 

  1336.   * @brief      Disable register write-protection function
    1337. 

  1337.   * @param      None
    1338. 

  1338.   * @return     None
    1339. 

  1339.   * @details    This function disable register write-protection function.
    1340. 

  1340.   *             To unlock the protected register to allow write access.
    1341. 

  1341.   * \hideinitializer
    1342. 

  1342.   */
    1343. 

  1343. __STATIC_INLINE void SYS_UnlockReg(void)
    1344. 

  1344. {
    1345. 

  1345.     do {
    1346. 

  1346.         SYS->REGLCTL = 0x59;
    1347. 

  1347.         SYS->REGLCTL = 0x16;
    1348. 

  1348.         SYS->REGLCTL = 0x88;
    1349. 

  1349.     } while (SYS->REGLCTL == 0);
    1350. 

  1350. }
    1351. 

  1351. 

  1352. /**
    1353. 

  1353.   * @brief      Enable register write-protection function
    1354. 

  1354.   * @param      None
    1355. 

  1355.   * @return     None
    1356. 

  1356.   * @details    This function is used to enable register write-protection function.
    1357. 

  1357.   *             To lock the protected register to forbid write access.
    1358. 

  1358.   * \hideinitializer
    1359. 

  1359.   */
    1360. 

  1360. __STATIC_INLINE void SYS_LockReg(void)
    1361. 

  1361. {
    1362. 

  1362.     SYS->REGLCTL = 0;
    1363. 

  1363. }
    1364. 

  1364. 

  1365. 

  1366. void SYS_ClearResetSrc(uint32_t u32Src);
    1367. 

  1367. uint32_t SYS_GetBODStatus(void);
    1368. 

  1368. uint32_t SYS_GetResetSrc(void);
    1369. 

  1369. uint32_t SYS_IsRegLocked(void);
    1370. 

  1370. uint32_t SYS_ReadPDID(void);
    1371. 

  1371. void SYS_ResetChip(void);
    1372. 

  1372. void SYS_ResetCPU(void);
    1373. 

  1373. void SYS_ResetModule(uint32_t u32ModuleIndex);
    1374. 

  1374. void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
    1375. 

  1375. void SYS_DisableBOD(void);
    1376. 

  1376. 

  1377. 

  1378. /*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
    1379. 

  1379. 

  1380. /*@}*/ /* end of group SYS_Driver */
    1381. 

  1381. 

  1382. /*@}*/ /* end of group Standard_Driver */
    1383. 

  1383. 

  1384. 

  1385. #ifdef __cplusplus
    1386. 

  1386. }
    1387. 

  1387. #endif
    1388. 

  1388. 

  1389. #endif /* __NU_SYS_H__ */
    1390. 

  1390. 

  1391. /*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
    1392.