drv_spii2s.c 17 KB

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  1. /**************************************************************************//**
  2. *
  3. * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: Apache-2.0
  6. *
  7. * Change Logs:
  8. * Date Author Notes
  9. * 2021-02-22 klcheng First version
  10. *
  11. ******************************************************************************/
  12. #include <rtconfig.h>
  13. #if defined(BSP_USING_SPII2S)
  14. #include <rtdevice.h>
  15. #include <drv_pdma.h>
  16. #include <drv_i2s.h>
  17. /* Private define ---------------------------------------------------------------*/
  18. #define DBG_ENABLE
  19. #define DBG_LEVEL DBG_LOG
  20. #define DBG_SECTION_NAME "spii2s"
  21. #define DBG_COLOR
  22. #include <rtdbg.h>
  23. enum
  24. {
  25. SPII2S_START = -1,
  26. #if defined(BSP_USING_SPII2S0)
  27. SPII2S0_IDX,
  28. #endif
  29. SPII2S_CNT
  30. };
  31. /* Private functions ------------------------------------------------------------*/
  32. static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps);
  33. static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps);
  34. static rt_err_t nu_spii2s_init(struct rt_audio_device *audio);
  35. static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream);
  36. static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream);
  37. static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info);
  38. /* Public functions -------------------------------------------------------------*/
  39. rt_err_t nu_spii2s_acodec_register(struct rt_audio_device *audio, nu_acodec_ops_t);
  40. /* Private variables ------------------------------------------------------------*/
  41. static struct nu_i2s g_nu_spii2s_arr [] =
  42. {
  43. #if defined(BSP_USING_SPII2S0)
  44. {
  45. .name = "spii2s0",
  46. .i2s_base = (SPI_T *)SPI0, //Avoid warning
  47. .i2s_rst = SPI0_RST,
  48. .i2s_dais = {
  49. [NU_I2S_DAI_PLAYBACK] = {
  50. .pdma_perp = PDMA_SPI0_TX,
  51. },
  52. [NU_I2S_DAI_CAPTURE] = {
  53. .pdma_perp = PDMA_SPI0_RX,
  54. }
  55. }
  56. },
  57. #endif
  58. };
  59. static void nu_pdma_spii2s_rx_cb(void *pvUserData, uint32_t u32EventFilter)
  60. {
  61. nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData;
  62. nu_i2s_dai_t psNuSPII2sDai;
  63. RT_ASSERT(psNuSPII2s != RT_NULL);
  64. psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE];
  65. if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
  66. {
  67. // Report a buffer ready.
  68. rt_uint8_t *pbuf_old = &psNuSPII2sDai->fifo[psNuSPII2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ;
  69. psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
  70. /* Report upper layer. */
  71. rt_audio_rx_done(&psNuSPII2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE);
  72. }
  73. }
  74. static void nu_pdma_spii2s_tx_cb(void *pvUserData, uint32_t u32EventFilter)
  75. {
  76. nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData;
  77. nu_i2s_dai_t psNuSPII2sDai;
  78. RT_ASSERT(psNuSPII2s != RT_NULL);
  79. psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
  80. if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
  81. {
  82. rt_audio_tx_complete(&psNuSPII2s->audio);
  83. psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
  84. }
  85. }
  86. static rt_err_t nu_spii2s_pdma_sc_config(nu_i2s_t psNuSPII2s, E_NU_I2S_DAI dai)
  87. {
  88. rt_err_t result = RT_EOK;
  89. SPI_T *spii2s_base;
  90. nu_i2s_dai_t psNuSPII2sDai;
  91. int i;
  92. uint32_t u32Src, u32Dst;
  93. nu_pdma_cb_handler_t pfm_pdma_cb;
  94. RT_ASSERT(psNuSPII2s != RT_NULL);
  95. /* Get base address of spii2s register */
  96. spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
  97. psNuSPII2sDai = &psNuSPII2s->i2s_dais[dai];
  98. switch ((int)dai)
  99. {
  100. case NU_I2S_DAI_PLAYBACK:
  101. pfm_pdma_cb = nu_pdma_spii2s_tx_cb;
  102. u32Src = (uint32_t)&psNuSPII2sDai->fifo[0];
  103. u32Dst = (uint32_t)&spii2s_base->TX;
  104. break;
  105. case NU_I2S_DAI_CAPTURE:
  106. pfm_pdma_cb = nu_pdma_spii2s_rx_cb;
  107. u32Src = (uint32_t)&spii2s_base->RX;
  108. u32Dst = (uint32_t)&psNuSPII2sDai->fifo[0];
  109. break;
  110. default:
  111. return -RT_EINVAL;
  112. }
  113. result = nu_pdma_callback_register(psNuSPII2sDai->pdma_chanid,
  114. pfm_pdma_cb,
  115. (void *)psNuSPII2s,
  116. NU_PDMA_EVENT_TRANSFER_DONE);
  117. RT_ASSERT(result == RT_EOK);
  118. for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++)
  119. {
  120. /* Setup dma descriptor entry */
  121. result = nu_pdma_desc_setup(psNuSPII2sDai->pdma_chanid, // Channel ID
  122. psNuSPII2sDai->pdma_descs[i], // this descriptor
  123. 32, // 32-bits
  124. (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO
  125. (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory
  126. (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count
  127. psNuSPII2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER]); // Next descriptor
  128. RT_ASSERT(result == RT_EOK);
  129. }
  130. /* Assign head descriptor */
  131. result = nu_pdma_sg_transfer(psNuSPII2sDai->pdma_chanid, psNuSPII2sDai->pdma_descs[0], 0);
  132. RT_ASSERT(result == RT_EOK);
  133. return result;
  134. }
  135. static rt_bool_t nu_spii2s_capacity_check(struct rt_audio_configure *pconfig)
  136. {
  137. switch (pconfig->samplebits)
  138. {
  139. case 8:
  140. case 16:
  141. /* case 24: PDMA constrain */
  142. case 32:
  143. break;
  144. default:
  145. goto exit_nu_spii2s_capacity_check;
  146. }
  147. switch (pconfig->channels)
  148. {
  149. case 1:
  150. case 2:
  151. break;
  152. default:
  153. goto exit_nu_spii2s_capacity_check;
  154. }
  155. return RT_TRUE;
  156. exit_nu_spii2s_capacity_check:
  157. return RT_FALSE;
  158. }
  159. static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configure *pconfig)
  160. {
  161. rt_err_t result = RT_EOK;
  162. nu_acodec_ops_t pNuACodecOps;
  163. SPI_T *spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
  164. RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL);
  165. pNuACodecOps = psNuSPII2s->AcodecOps;
  166. /* Open SPII2S */
  167. if (nu_spii2s_capacity_check(pconfig) == RT_TRUE)
  168. {
  169. /* Reset audio codec */
  170. if (pNuACodecOps->nu_acodec_reset)
  171. result = pNuACodecOps->nu_acodec_reset();
  172. if (result != RT_EOK)
  173. goto exit_nu_spii2s_dai_setup;
  174. /* Setup audio codec */
  175. if (pNuACodecOps->nu_acodec_init)
  176. result = pNuACodecOps->nu_acodec_init();
  177. if (!pNuACodecOps->nu_acodec_init || result != RT_EOK)
  178. goto exit_nu_spii2s_dai_setup;
  179. /* Setup acodec samplerate/samplebit/channel */
  180. if (pNuACodecOps->nu_acodec_dsp_control)
  181. result = pNuACodecOps->nu_acodec_dsp_control(pconfig);
  182. if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK)
  183. goto exit_nu_spii2s_dai_setup;
  184. SPII2S_Open(spii2s_base,
  185. (psNuSPII2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? SPII2S_MODE_SLAVE : SPII2S_MODE_MASTER,
  186. pconfig->samplerate,
  187. (((pconfig->samplebits / 8) - 1) << SPI_I2SCTL_WDWIDTH_Pos),
  188. (pconfig->channels == 1) ? SPII2S_MONO : SPII2S_STEREO,
  189. SPII2S_FORMAT_I2S);
  190. LOG_I("Open SPII2S.");
  191. /* Set MCLK and enable MCLK */
  192. /* The target MCLK is related to audio codec setting. */
  193. SPII2S_EnableMCLK(spii2s_base, 12000000);
  194. /* Set un-mute */
  195. if (pNuACodecOps->nu_acodec_mixer_control)
  196. pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE);
  197. }
  198. else
  199. result = -RT_EINVAL;
  200. exit_nu_spii2s_dai_setup:
  201. return result;
  202. }
  203. static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
  204. {
  205. rt_err_t result = RT_EOK;
  206. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  207. nu_acodec_ops_t pNuACodecOps;
  208. RT_ASSERT(audio != RT_NULL);
  209. RT_ASSERT(caps != RT_NULL);
  210. RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL);
  211. pNuACodecOps = psNuSPII2s->AcodecOps;
  212. switch (caps->main_type)
  213. {
  214. case AUDIO_TYPE_QUERY:
  215. switch (caps->sub_type)
  216. {
  217. case AUDIO_TYPE_QUERY:
  218. caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
  219. break;
  220. default:
  221. result = -RT_ERROR;
  222. break;
  223. } // switch (caps->sub_type)
  224. break;
  225. case AUDIO_TYPE_MIXER:
  226. if (pNuACodecOps->nu_acodec_mixer_query)
  227. {
  228. switch (caps->sub_type)
  229. {
  230. case AUDIO_MIXER_QUERY:
  231. return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask);
  232. default:
  233. return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value);
  234. } // switch (caps->sub_type)
  235. } // if (pNuACodecOps->nu_acodec_mixer_query)
  236. result = -RT_ERROR;
  237. break;
  238. case AUDIO_TYPE_INPUT:
  239. case AUDIO_TYPE_OUTPUT:
  240. switch (caps->sub_type)
  241. {
  242. case AUDIO_DSP_PARAM:
  243. caps->udata.config.channels = psNuSPII2s->config.channels;
  244. caps->udata.config.samplebits = psNuSPII2s->config.samplebits;
  245. caps->udata.config.samplerate = psNuSPII2s->config.samplerate;
  246. break;
  247. case AUDIO_DSP_SAMPLERATE:
  248. caps->udata.config.samplerate = psNuSPII2s->config.samplerate;
  249. break;
  250. case AUDIO_DSP_CHANNELS:
  251. caps->udata.config.channels = psNuSPII2s->config.channels;
  252. break;
  253. case AUDIO_DSP_SAMPLEBITS:
  254. caps->udata.config.samplebits = psNuSPII2s->config.samplebits;
  255. break;
  256. default:
  257. result = -RT_ERROR;
  258. break;
  259. } // switch (caps->sub_type)
  260. break;
  261. default:
  262. result = -RT_ERROR;
  263. break;
  264. } // switch (caps->main_type)
  265. return result;
  266. }
  267. static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
  268. {
  269. rt_err_t result = RT_EOK;
  270. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  271. nu_acodec_ops_t pNuACodecOps;
  272. int stream = -1;
  273. RT_ASSERT(audio != RT_NULL);
  274. RT_ASSERT(caps != RT_NULL);
  275. RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL);
  276. pNuACodecOps = psNuSPII2s->AcodecOps;
  277. switch (caps->main_type)
  278. {
  279. case AUDIO_TYPE_MIXER:
  280. if (psNuSPII2s->AcodecOps->nu_acodec_mixer_control)
  281. psNuSPII2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value);
  282. break;
  283. case AUDIO_TYPE_INPUT:
  284. stream = AUDIO_STREAM_RECORD;
  285. case AUDIO_TYPE_OUTPUT:
  286. {
  287. rt_bool_t bNeedReset = RT_FALSE;
  288. if (stream < 0)
  289. stream = AUDIO_STREAM_REPLAY;
  290. switch (caps->sub_type)
  291. {
  292. case AUDIO_DSP_PARAM:
  293. if (rt_memcmp(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0)
  294. {
  295. rt_memcpy(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure));
  296. bNeedReset = RT_TRUE;
  297. }
  298. break;
  299. case AUDIO_DSP_SAMPLEBITS:
  300. if (psNuSPII2s->config.samplerate != caps->udata.config.samplebits)
  301. {
  302. psNuSPII2s->config.samplerate = caps->udata.config.samplebits;
  303. bNeedReset = RT_TRUE;
  304. }
  305. break;
  306. case AUDIO_DSP_CHANNELS:
  307. if (psNuSPII2s->config.channels != caps->udata.config.channels)
  308. {
  309. pNuACodecOps->config.channels = caps->udata.config.channels;
  310. bNeedReset = RT_TRUE;
  311. }
  312. break;
  313. case AUDIO_DSP_SAMPLERATE:
  314. if (psNuSPII2s->config.samplerate != caps->udata.config.samplerate)
  315. {
  316. psNuSPII2s->config.samplerate = caps->udata.config.samplerate;
  317. bNeedReset = RT_TRUE;
  318. }
  319. break;
  320. default:
  321. result = -RT_ERROR;
  322. break;
  323. } // switch (caps->sub_type)
  324. if (bNeedReset)
  325. {
  326. return nu_spii2s_start(audio, stream);
  327. }
  328. }
  329. break;
  330. default:
  331. result = -RT_ERROR;
  332. break;
  333. } // switch (caps->main_type)
  334. return result;
  335. }
  336. static rt_err_t nu_spii2s_init(struct rt_audio_device *audio)
  337. {
  338. rt_err_t result = RT_EOK;
  339. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  340. RT_ASSERT(audio != RT_NULL);
  341. /* Reset this module */
  342. SYS_ResetModule(psNuSPII2s->i2s_rst);
  343. return -(result);
  344. }
  345. static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream)
  346. {
  347. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  348. SPI_T *spii2s_base;
  349. RT_ASSERT(audio != RT_NULL);
  350. spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
  351. /* Restart all: SPII2S and codec. */
  352. nu_spii2s_stop(audio, stream);
  353. if (nu_spii2s_dai_setup(psNuSPII2s, &psNuSPII2s->config) != RT_EOK)
  354. return -RT_ERROR;
  355. switch (stream)
  356. {
  357. case AUDIO_STREAM_REPLAY:
  358. {
  359. nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_PLAYBACK);
  360. /* Start TX DMA */
  361. SPII2S_ENABLE_TXDMA(spii2s_base);
  362. /* Enable I2S Tx function */
  363. SPII2S_ENABLE_TX(spii2s_base);
  364. LOG_I("Start replay.");
  365. }
  366. break;
  367. case AUDIO_STREAM_RECORD:
  368. {
  369. nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_CAPTURE);
  370. /* Start RX DMA */
  371. SPII2S_ENABLE_RXDMA(spii2s_base);
  372. /* Enable I2S Rx function */
  373. SPII2S_ENABLE_RX(spii2s_base);
  374. LOG_I("Start record.");
  375. }
  376. break;
  377. default:
  378. return -RT_ERROR;
  379. }
  380. return RT_EOK;
  381. }
  382. static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream)
  383. {
  384. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  385. nu_i2s_dai_t psNuSPII2sDai = RT_NULL;
  386. SPI_T *spii2s_base;
  387. RT_ASSERT(audio != RT_NULL);
  388. spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
  389. switch (stream)
  390. {
  391. case AUDIO_STREAM_REPLAY:
  392. psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
  393. // Disable TX
  394. SPII2S_DISABLE_TXDMA(spii2s_base);
  395. SPII2S_DISABLE_TX(spii2s_base);
  396. LOG_I("Stop replay.");
  397. break;
  398. case AUDIO_STREAM_RECORD:
  399. psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE];
  400. // Disable RX
  401. SPII2S_DISABLE_RXDMA(spii2s_base);
  402. SPII2S_DISABLE_RX(spii2s_base);
  403. LOG_I("Stop record.");
  404. break;
  405. default:
  406. return -RT_EINVAL;
  407. }
  408. /* Stop DMA transfer. */
  409. nu_pdma_channel_terminate(psNuSPII2sDai->pdma_chanid);
  410. /* Close SPII2S */
  411. if (!(spii2s_base->I2SCTL & (SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_RXEN_Msk)))
  412. {
  413. SPII2S_DisableMCLK(spii2s_base);
  414. SPII2S_Close(spii2s_base);
  415. LOG_I("Close SPII2S.");
  416. }
  417. /* Silence */
  418. rt_memset((void *)psNuSPII2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE);
  419. psNuSPII2sDai->fifo_block_idx = 0;
  420. return RT_EOK;
  421. }
  422. static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
  423. {
  424. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  425. RT_ASSERT(audio != RT_NULL);
  426. RT_ASSERT(info != RT_NULL);
  427. info->buffer = (rt_uint8_t *)psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ;
  428. info->total_size = NU_I2S_DMA_FIFO_SIZE;
  429. info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE;
  430. info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER;
  431. return;
  432. }
  433. static struct rt_audio_ops nu_spii2s_audio_ops =
  434. {
  435. .getcaps = nu_spii2s_getcaps,
  436. .configure = nu_spii2s_configure,
  437. .init = nu_spii2s_init,
  438. .start = nu_spii2s_start,
  439. .stop = nu_spii2s_stop,
  440. .transmit = RT_NULL,
  441. .buffer_info = nu_spii2s_buffer_info
  442. };
  443. static rt_err_t nu_hw_spii2s_pdma_allocate(nu_i2s_dai_t psNuSPII2sDai)
  444. {
  445. /* Allocate I2S nu_dma channel */
  446. if ((psNuSPII2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuSPII2sDai->pdma_perp)) < 0)
  447. {
  448. goto nu_hw_spii2s_pdma_allocate;
  449. }
  450. return RT_EOK;
  451. nu_hw_spii2s_pdma_allocate:
  452. return -(RT_ERROR);
  453. }
  454. int rt_hw_spii2s_init(void)
  455. {
  456. int j = 0;
  457. nu_i2s_dai_t psNuSPII2sDai;
  458. for (j = (SPII2S_START + 1); j < SPII2S_CNT; j++)
  459. {
  460. int i = 0;
  461. for (i = 0; i < NU_I2S_DAI_CNT; i++)
  462. {
  463. uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE);
  464. psNuSPII2sDai = &g_nu_spii2s_arr[j].i2s_dais[i];
  465. psNuSPII2sDai->fifo = pu8ptr;
  466. rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE);
  467. RT_ASSERT(psNuSPII2sDai->fifo != RT_NULL);
  468. psNuSPII2sDai->pdma_chanid = -1;
  469. psNuSPII2sDai->fifo_block_idx = 0;
  470. RT_ASSERT(nu_hw_spii2s_pdma_allocate(psNuSPII2sDai) == RT_EOK);
  471. RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuSPII2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK);
  472. }
  473. /* Register ops of audio device */
  474. g_nu_spii2s_arr[j].audio.ops = &nu_spii2s_audio_ops;
  475. /* Register device, RW: it is with replay and record functions. */
  476. rt_audio_register(&g_nu_spii2s_arr[j].audio, g_nu_spii2s_arr[j].name, RT_DEVICE_FLAG_RDWR, &g_nu_spii2s_arr[j]);
  477. }
  478. return RT_EOK;
  479. }
  480. INIT_DEVICE_EXPORT(rt_hw_spii2s_init);
  481. #endif //#if defined(BSP_USING_SPII2S)