ebi_reg.h 30 KB

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  1. /**************************************************************************//**
  2. * @file ebi_reg.h
  3. * @version V1.00
  4. * @brief EBI register definition header file
  5. *
  6. * SPDX-License-Identifier: Apache-2.0
  7. * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
  8. *****************************************************************************/
  9. #ifndef __EBI_REG_H__
  10. #define __EBI_REG_H__
  11. #if defined ( __CC_ARM )
  12. #pragma anon_unions
  13. #endif
  14. /**
  15. @addtogroup REGISTER Control Register
  16. @{
  17. */
  18. /**
  19. @addtogroup EBI External Bus Interface Controller(EBI)
  20. Memory Mapped Structure for EBI Controller
  21. @{ */
  22. typedef struct
  23. {
  24. /**
  25. * @var EBI_T::CTL0
  26. * Offset: 0x00 External Bus Interface Bank0 Control Register
  27. * ---------------------------------------------------------------------------------------------------
  28. * |Bits |Field |Descriptions
  29. * | :----: | :----: | :---- |
  30. * |[0] |EN |EBI Enable Bit
  31. * | | |This bit is the functional enable bit for EBI.
  32. * | | |0 = EBI function Disabled.
  33. * | | |1 = EBI function Enabled.
  34. * |[1] |DW16 |EBI Data Width 16-bit Select
  35. * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
  36. * | | |0 = EBI data width is 8-bit.
  37. * | | |1 = EBI data width is 16-bit.
  38. * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
  39. * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
  40. * | | |0 = Chip select pin (EBI_nCS) is active low.
  41. * | | |1 = Chip select pin (EBI_nCS) is active high.
  42. * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
  43. * | | |0 = Address/Data Bus Separating Mode Disabled.
  44. * | | |1 = Address/Data Bus Separating Mode Enabled.
  45. * |[4] |CACCESS |Continuous Data Access Mode
  46. * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
  47. * | | |0 = Continuous data access mode Disabled.
  48. * | | |1 = Continuous data access mode Enabled.
  49. * |[10:8] |MCLKDIV |External Output Clock Divider
  50. * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
  51. * | | |000 = HCLK/1.
  52. * | | |001 = HCLK/2.
  53. * | | |010 = HCLK/4.
  54. * | | |011 = HCLK/8.
  55. * | | |100 = HCLK/16.
  56. * | | |101 = HCLK/32.
  57. * | | |110 = HCLK/64.
  58. * | | |111 = HCLK/128.
  59. * |[18:16] |TALE |Extend Time of ALE
  60. * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
  61. * | | |tALE = (TALE+1)*EBI_MCLK.
  62. * | | |Note: This field only available in EBI_CTL0 register
  63. * |[24] |WBUFEN |EBI Write Buffer Enable Bit
  64. * | | |0 = EBI write buffer Disabled.
  65. * | | |1 = EBI write buffer Enabled.
  66. * | | |Note: This bit only available in EBI_CTL0 register
  67. * @var EBI_T::TCTL0
  68. * Offset: 0x04 External Bus Interface Bank0 Timing Control Register
  69. * ---------------------------------------------------------------------------------------------------
  70. * |Bits |Field |Descriptions
  71. * | :----: | :----: | :---- |
  72. * |[7:3] |TACC |EBI Data Access Time
  73. * | | |TACC define data access time (tACC).
  74. * | | |tACC = (TACC +1) * EBI_MCLK.
  75. * |[10:8] |TAHD |EBI Data Access Hold Time
  76. * | | |TAHD define data access hold time (tAHD).
  77. * | | |tAHD = (TAHD +1) * EBI_MCLK.
  78. * |[15:12] |W2X |Idle Cycle After Write
  79. * | | |This field defines the number of W2X idle cycle.
  80. * | | |W2X idle cycle = (W2X * EBI_MCLK).
  81. * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
  82. * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
  83. * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
  84. * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
  85. * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
  86. * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
  87. * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
  88. * |[27:24] |R2R |Idle Cycle Between Read-to-read
  89. * | | |This field defines the number of R2R idle cycle.
  90. * | | |R2R idle cycle = (R2R * EBI_MCLK).
  91. * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
  92. * @var EBI_T::CTL1
  93. * Offset: 0x10 External Bus Interface Bank1 Control Register
  94. * ---------------------------------------------------------------------------------------------------
  95. * |Bits |Field |Descriptions
  96. * | :----: | :----: | :---- |
  97. * |[0] |EN |EBI Enable Bit
  98. * | | |This bit is the functional enable bit for EBI.
  99. * | | |0 = EBI function Disabled.
  100. * | | |1 = EBI function Enabled.
  101. * |[1] |DW16 |EBI Data Width 16-bit Select
  102. * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
  103. * | | |0 = EBI data width is 8-bit.
  104. * | | |1 = EBI data width is 16-bit.
  105. * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
  106. * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
  107. * | | |0 = Chip select pin (EBI_nCS) is active low.
  108. * | | |1 = Chip select pin (EBI_nCS) is active high.
  109. * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
  110. * | | |0 = Address/Data Bus Separating Mode Disabled.
  111. * | | |1 = Address/Data Bus Separating Mode Enabled.
  112. * |[4] |CACCESS |Continuous Data Access Mode
  113. * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
  114. * | | |0 = Continuous data access mode Disabled.
  115. * | | |1 = Continuous data access mode Enabled.
  116. * |[10:8] |MCLKDIV |External Output Clock Divider
  117. * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
  118. * | | |000 = HCLK/1.
  119. * | | |001 = HCLK/2.
  120. * | | |010 = HCLK/4.
  121. * | | |011 = HCLK/8.
  122. * | | |100 = HCLK/16.
  123. * | | |101 = HCLK/32.
  124. * | | |110 = HCLK/64.
  125. * | | |111 = HCLK/128.
  126. * |[18:16] |TALE |Extend Time of ALE
  127. * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
  128. * | | |tALE = (TALE+1)*EBI_MCLK.
  129. * | | |Note: This field only available in EBI_CTL0 register
  130. * |[24] |WBUFEN |EBI Write Buffer Enable Bit
  131. * | | |0 = EBI write buffer Disabled.
  132. * | | |1 = EBI write buffer Enabled.
  133. * | | |Note: This bit only available in EBI_CTL0 register
  134. * @var EBI_T::TCTL1
  135. * Offset: 0x14 External Bus Interface Bank1 Timing Control Register
  136. * ---------------------------------------------------------------------------------------------------
  137. * |Bits |Field |Descriptions
  138. * | :----: | :----: | :---- |
  139. * |[7:3] |TACC |EBI Data Access Time
  140. * | | |TACC define data access time (tACC).
  141. * | | |tACC = (TACC +1) * EBI_MCLK.
  142. * |[10:8] |TAHD |EBI Data Access Hold Time
  143. * | | |TAHD define data access hold time (tAHD).
  144. * | | |tAHD = (TAHD +1) * EBI_MCLK.
  145. * |[15:12] |W2X |Idle Cycle After Write
  146. * | | |This field defines the number of W2X idle cycle.
  147. * | | |W2X idle cycle = (W2X * EBI_MCLK).
  148. * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
  149. * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
  150. * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
  151. * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
  152. * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
  153. * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
  154. * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
  155. * |[27:24] |R2R |Idle Cycle Between Read-to-read
  156. * | | |This field defines the number of R2R idle cycle.
  157. * | | |R2R idle cycle = (R2R * EBI_MCLK).
  158. * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
  159. * @var EBI_T::CTL2
  160. * Offset: 0x20 External Bus Interface Bank2 Control Register
  161. * ---------------------------------------------------------------------------------------------------
  162. * |Bits |Field |Descriptions
  163. * | :----: | :----: | :---- |
  164. * |[0] |EN |EBI Enable Bit
  165. * | | |This bit is the functional enable bit for EBI.
  166. * | | |0 = EBI function Disabled.
  167. * | | |1 = EBI function Enabled.
  168. * |[1] |DW16 |EBI Data Width 16-bit Select
  169. * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
  170. * | | |0 = EBI data width is 8-bit.
  171. * | | |1 = EBI data width is 16-bit.
  172. * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
  173. * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
  174. * | | |0 = Chip select pin (EBI_nCS) is active low.
  175. * | | |1 = Chip select pin (EBI_nCS) is active high.
  176. * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
  177. * | | |0 = Address/Data Bus Separating Mode Disabled.
  178. * | | |1 = Address/Data Bus Separating Mode Enabled.
  179. * |[4] |CACCESS |Continuous Data Access Mode
  180. * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
  181. * | | |0 = Continuous data access mode Disabled.
  182. * | | |1 = Continuous data access mode Enabled.
  183. * |[10:8] |MCLKDIV |External Output Clock Divider
  184. * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
  185. * | | |000 = HCLK/1.
  186. * | | |001 = HCLK/2.
  187. * | | |010 = HCLK/4.
  188. * | | |011 = HCLK/8.
  189. * | | |100 = HCLK/16.
  190. * | | |101 = HCLK/32.
  191. * | | |110 = HCLK/64.
  192. * | | |111 = HCLK/128.
  193. * |[18:16] |TALE |Extend Time of ALE
  194. * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
  195. * | | |tALE = (TALE+1)*EBI_MCLK.
  196. * | | |Note: This field only available in EBI_CTL0 register
  197. * |[24] |WBUFEN |EBI Write Buffer Enable Bit
  198. * | | |0 = EBI write buffer Disabled.
  199. * | | |1 = EBI write buffer Enabled.
  200. * | | |Note: This bit only available in EBI_CTL0 register
  201. * @var EBI_T::TCTL2
  202. * Offset: 0x24 External Bus Interface Bank2 Timing Control Register
  203. * ---------------------------------------------------------------------------------------------------
  204. * |Bits |Field |Descriptions
  205. * | :----: | :----: | :---- |
  206. * |[7:3] |TACC |EBI Data Access Time
  207. * | | |TACC define data access time (tACC).
  208. * | | |tACC = (TACC +1) * EBI_MCLK.
  209. * |[10:8] |TAHD |EBI Data Access Hold Time
  210. * | | |TAHD define data access hold time (tAHD).
  211. * | | |tAHD = (TAHD +1) * EBI_MCLK.
  212. * |[15:12] |W2X |Idle Cycle After Write
  213. * | | |This field defines the number of W2X idle cycle.
  214. * | | |W2X idle cycle = (W2X * EBI_MCLK).
  215. * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
  216. * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
  217. * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
  218. * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
  219. * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
  220. * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
  221. * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
  222. * |[27:24] |R2R |Idle Cycle Between Read-to-read
  223. * | | |This field defines the number of R2R idle cycle.
  224. * | | |R2R idle cycle = (R2R * EBI_MCLK).
  225. * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
  226. */
  227. __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
  228. __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
  229. /// @cond HIDDEN_SYMBOLS
  230. __I uint32_t RESERVE0[2];
  231. /// @endcond //HIDDEN_SYMBOLS
  232. __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
  233. __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
  234. /// @cond HIDDEN_SYMBOLS
  235. __I uint32_t RESERVE1[2];
  236. /// @endcond //HIDDEN_SYMBOLS
  237. __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
  238. __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
  239. } EBI_T;
  240. /**
  241. @addtogroup EBI_CONST EBI Bit Field Definition
  242. Constant Definitions for EBI Controller
  243. @{ */
  244. #define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */
  245. #define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */
  246. #define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */
  247. #define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */
  248. #define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */
  249. #define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */
  250. #define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */
  251. #define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */
  252. #define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */
  253. #define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */
  254. #define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */
  255. #define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */
  256. #define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */
  257. #define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */
  258. #define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */
  259. #define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */
  260. #define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */
  261. #define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */
  262. #define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */
  263. #define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */
  264. #define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */
  265. #define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */
  266. #define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */
  267. #define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */
  268. #define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */
  269. #define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */
  270. #define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */
  271. #define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */
  272. #define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
  273. #define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
  274. #define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
  275. #define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
  276. #define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
  277. #define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
  278. #define EBI_CTL0_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */
  279. #define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */
  280. #define EBI_CTL0_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
  281. #define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
  282. #define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
  283. #define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
  284. #define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
  285. #define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
  286. #define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
  287. #define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
  288. #define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
  289. #define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
  290. #define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
  291. #define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
  292. #define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
  293. #define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
  294. #define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
  295. #define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
  296. #define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
  297. #define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
  298. #define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
  299. #define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
  300. #define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */
  301. #define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */
  302. #define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */
  303. #define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */
  304. #define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */
  305. #define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */
  306. #define EBI_CTL1_ADSEPEN_Pos (3) /*!< EBI_T::CTL1: ADSEPEN Position */
  307. #define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) /*!< EBI_T::CTL1: ADSEPEN Mask */
  308. #define EBI_CTL1_CACCESS_Pos (4) /*!< EBI_T::CTL1: CACCESS Position */
  309. #define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) /*!< EBI_T::CTL1: CACCESS Mask */
  310. #define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */
  311. #define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */
  312. #define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */
  313. #define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */
  314. #define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */
  315. #define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */
  316. #define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */
  317. #define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */
  318. #define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */
  319. #define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */
  320. #define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */
  321. #define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */
  322. #define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */
  323. #define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */
  324. #define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */
  325. #define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */
  326. #define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */
  327. #define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */
  328. #define EBI_CTL2_EN_Pos (0) /*!< EBI_T::CTL2: EN Position */
  329. #define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) /*!< EBI_T::CTL2: EN Mask */
  330. #define EBI_CTL2_DW16_Pos (1) /*!< EBI_T::CTL2: DW16 Position */
  331. #define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) /*!< EBI_T::CTL2: DW16 Mask */
  332. #define EBI_CTL2_CSPOLINV_Pos (2) /*!< EBI_T::CTL2: CSPOLINV Position */
  333. #define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) /*!< EBI_T::CTL2: CSPOLINV Mask */
  334. #define EBI_CTL2_ADSEPEN_Pos (3) /*!< EBI_T::CTL2: ADSEPEN Position */
  335. #define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) /*!< EBI_T::CTL2: ADSEPEN Mask */
  336. #define EBI_CTL2_CACCESS_Pos (4) /*!< EBI_T::CTL2: CACCESS Position */
  337. #define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) /*!< EBI_T::CTL2: CACCESS Mask */
  338. #define EBI_CTL2_MCLKDIV_Pos (8) /*!< EBI_T::CTL2: MCLKDIV Position */
  339. #define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) /*!< EBI_T::CTL2: MCLKDIV Mask */
  340. #define EBI_CTL2_TALE_Pos (16) /*!< EBI_T::CTL2: TALE Position */
  341. #define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) /*!< EBI_T::CTL2: TALE Mask */
  342. #define EBI_CTL2_WBUFEN_Pos (24) /*!< EBI_T::CTL2: WBUFEN Position */
  343. #define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) /*!< EBI_T::CTL2: WBUFEN Mask */
  344. #define EBI_TCTL2_TACC_Pos (3) /*!< EBI_T::TCTL2: TACC Position */
  345. #define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) /*!< EBI_T::TCTL2: TACC Mask */
  346. #define EBI_TCTL2_TAHD_Pos (8) /*!< EBI_T::TCTL2: TAHD Position */
  347. #define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) /*!< EBI_T::TCTL2: TAHD Mask */
  348. #define EBI_TCTL2_W2X_Pos (12) /*!< EBI_T::TCTL2: W2X Position */
  349. #define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) /*!< EBI_T::TCTL2: W2X Mask */
  350. #define EBI_TCTL2_RAHDOFF_Pos (22) /*!< EBI_T::TCTL2: RAHDOFF Position */
  351. #define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) /*!< EBI_T::TCTL2: RAHDOFF Mask */
  352. #define EBI_TCTL2_WAHDOFF_Pos (23) /*!< EBI_T::TCTL2: WAHDOFF Position */
  353. #define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) /*!< EBI_T::TCTL2: WAHDOFF Mask */
  354. #define EBI_TCTL2_R2R_Pos (24) /*!< EBI_T::TCTL2: R2R Position */
  355. #define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) /*!< EBI_T::TCTL2: R2R Mask */
  356. /**@}*/ /* EBI_CONST */
  357. /**@}*/ /* end of EBI register group */
  358. /**@}*/ /* end of REGISTER group */
  359. #if defined ( __CC_ARM )
  360. #pragma no_anon_unions
  361. #endif
  362. #endif /* __EBI_REG_H__ */