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nu_sys.h

nu_sys.h 181 KB
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
  1. /**************************************************************************//**
    2. 

  2.  * @file     SYS.h
    3. 

  3.  * @version  V3.0
    4. 

  4.  * @brief    M480 Series SYS Driver Header File
    5. 

  5.  *
    6. 

  6.  * SPDX-License-Identifier: Apache-2.0
    7. 

  7.  * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
    8. 

  8.  ******************************************************************************/
    9. 

  9. 

  10. #ifndef __NU_SYS_H__
    11. 

  11. #define __NU_SYS_H__
    12. 

  12. 

  13. #ifdef __cplusplus
    14. 

  14. extern "C"
    15. 

  15. {
    16. 

  16. #endif
    17. 

  17. 

  18. 

  19. /** @addtogroup Standard_Driver Standard Driver
    20. 

  20.   @{
    21. 

  21. */
    22. 

  22. 

  23. /** @addtogroup SYS_Driver SYS Driver
    24. 

  24.   @{
    25. 

  25. */
    26. 

  26. 

  27. /** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
    28. 

  28.   @{
    29. 

  29. */
    30. 

  30. 

  31. 

  32. /*---------------------------------------------------------------------------------------------------------*/
    33. 

  33. /*  Module Reset Control Resister constant definitions.                                                    */
    34. 

  34. /*---------------------------------------------------------------------------------------------------------*/
    35. 

  35. #define PDMA_RST            ((0UL<<24) | SYS_IPRST0_PDMARST_Pos)        /*!< Reset PDMA \hideinitializer*/
    36. 

  36. #define EBI_RST             ((0UL<<24) | SYS_IPRST0_EBIRST_Pos)         /*!< Reset EBI \hideinitializer*/
    37. 

  37. #define EMAC_RST            ((0UL<<24) | SYS_IPRST0_EMACRST_Pos)        /*!< Reset EMAC \hideinitializer */
    38. 

  38. #define SDH0_RST            ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos)        /*!< Reset SDH0 \hideinitializer */
    39. 

  39. #define CRC_RST             ((0UL<<24) | SYS_IPRST0_CRCRST_Pos)         /*!< Reset CRC \hideinitializer */
    40. 

  40. #define CCAP_RST            ((0UL<<24) | SYS_IPRST0_CCAPRST_Pos)        /*!< Reset ICAP \hideinitializer */
    41. 

  41. #define HSUSBD_RST          ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos)      /*!< Reset HSUSBD \hideinitializer */
    42. 

  42. #define CRPT_RST            ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos)        /*!< Reset CRPT \hideinitializer */
    43. 

  43. #define SPIM_RST            ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos)        /*!< Reset SPIM \hideinitializer */
    44. 

  44. #define USBH_RST            ((0UL<<24) | SYS_IPRST0_USBHRST_Pos)        /*!< Reset USBH \hideinitializer */
    45. 

  45. #define SDH1_RST            ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos)        /*!< Reset SDH1 \hideinitializer */
    46. 

  46. 

  47. #define GPIO_RST            ((4UL<<24) | SYS_IPRST1_GPIORST_Pos)        /*!< Reset GPIO \hideinitializer */
    48. 

  48. #define TMR0_RST            ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos)        /*!< Reset TMR0 \hideinitializer */
    49. 

  49. #define TMR1_RST            ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos)        /*!< Reset TMR1 \hideinitializer */
    50. 

  50. #define TMR2_RST            ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos)        /*!< Reset TMR2 \hideinitializer */
    51. 

  51. #define TMR3_RST            ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos)        /*!< Reset TMR3 \hideinitializer */
    52. 

  52. #define ACMP01_RST          ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos)      /*!< Reset ACMP01 \hideinitializer */
    53. 

  53. #define I2C0_RST            ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos)        /*!< Reset I2C0 \hideinitializer */
    54. 

  54. #define I2C1_RST            ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos)        /*!< Reset I2C1 \hideinitializer */
    55. 

  55. #define I2C2_RST            ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos)        /*!< Reset I2C2 \hideinitializer */
    56. 

  56. #define QSPI0_RST           ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos)       /*!< Reset QSPI0 \hideinitializer */
    57. 

  57. #define SPI0_RST            ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos)        /*!< Reset SPI0 \hideinitializer */
    58. 

  58. #define SPI1_RST            ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos)        /*!< Reset SPI1 \hideinitializer */
    59. 

  59. #define SPI2_RST            ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos)        /*!< Reset SPI2 \hideinitializer */
    60. 

  60. #define UART0_RST           ((4UL<<24) | SYS_IPRST1_UART0RST_Pos)       /*!< Reset UART0 \hideinitializer */
    61. 

  61. #define UART1_RST           ((4UL<<24) | SYS_IPRST1_UART1RST_Pos)       /*!< Reset UART1 \hideinitializer */
    62. 

  62. #define UART2_RST           ((4UL<<24) | SYS_IPRST1_UART2RST_Pos)       /*!< Reset UART2 \hideinitializer */
    63. 

  63. #define UART3_RST           ((4UL<<24) | SYS_IPRST1_UART3RST_Pos)       /*!< Reset UART3 \hideinitializer */
    64. 

  64. #define UART4_RST           ((4UL<<24) | SYS_IPRST1_UART4RST_Pos)       /*!< Reset UART4 \hideinitializer */
    65. 

  65. #define UART5_RST           ((4UL<<24) | SYS_IPRST1_UART5RST_Pos)       /*!< Reset UART5 \hideinitializer */
    66. 

  66. #define UART6_RST           ((4UL<<24) | SYS_IPRST1_UART6RST_Pos)       /*!< Reset UART6 \hideinitializer */
    67. 

  67. #define UART7_RST           ((4UL<<24) | SYS_IPRST1_UART7RST_Pos)       /*!< Reset UART7 \hideinitializer */
    68. 

  68. #define CAN0_RST            ((4UL<<24) | SYS_IPRST1_CAN0RST_Pos)        /*!< Reset CAN0 \hideinitializer */
    69. 

  69. #define CAN1_RST            ((4UL<<24) | SYS_IPRST1_CAN1RST_Pos)        /*!< Reset CAN1 \hideinitializer */
    70. 

  70. #define OTG_RST             ((4UL<<24) | SYS_IPRST1_OTGRST_Pos)         /*!< Reset OTG \hideinitializer */
    71. 

  71. #define USBD_RST            ((4UL<<24) | SYS_IPRST1_USBDRST_Pos)        /*!< Reset USBD \hideinitializer */
    72. 

  72. #define EADC_RST            ((4UL<<24) | SYS_IPRST1_EADCRST_Pos)        /*!< Reset EADC \hideinitializer */
    73. 

  73. #define I2S0_RST            ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos)        /*!< Reset I2S0 \hideinitializer */
    74. 

  74. #define HSOTG_RST           ((4UL<<24) | SYS_IPRST1_HSOTGRST_Pos)       /*!< Reset HSOTG \hideinitializer */
    75. 

  75. #define TRNG_RST            ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos)        /*!< Reset TRNG \hideinitializer */
    76. 

  76. 

  77. #define SC0_RST             ((8UL<<24) | SYS_IPRST2_SC0RST_Pos)         /*!< Reset SC0 \hideinitializer */
    78. 

  78. #define SC1_RST             ((8UL<<24) | SYS_IPRST2_SC1RST_Pos)         /*!< Reset SC1 \hideinitializer */
    79. 

  79. #define SC2_RST             ((8UL<<24) | SYS_IPRST2_SC2RST_Pos)         /*!< Reset SC2 \hideinitializer */
    80. 

  80. #define QSPI1_RST           ((8UL<<24) | SYS_IPRST2_QSPI1RST_Pos)       /*!< Reset QSPI1 \hideinitializer */
    81. 

  81. #define SPI3_RST            ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos)        /*!< Reset SPI3 \hideinitializer */
    82. 

  82. #define USCI0_RST           ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos)       /*!< Reset USCI0 \hideinitializer */
    83. 

  83. #define USCI1_RST           ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos)       /*!< Reset USCI1 \hideinitializer */
    84. 

  84. #define DAC_RST             ((8UL<<24) | SYS_IPRST2_DACRST_Pos)         /*!< Reset DAC \hideinitializer */
    85. 

  85. #define EPWM0_RST           ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos)       /*!< Reset EPWM0 \hideinitializer */
    86. 

  86. #define EPWM1_RST           ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos)       /*!< Reset EPWM1 \hideinitializer */
    87. 

  87. #define BPWM0_RST           ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos)       /*!< Reset BPWM0 \hideinitializer */
    88. 

  88. #define BPWM1_RST           ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos)       /*!< Reset BPWM1 \hideinitializer */
    89. 

  89. #define QEI0_RST            ((8UL<<24) | SYS_IPRST2_QEI0RST_Pos)        /*!< Reset QEI0 \hideinitializer */
    90. 

  90. #define QEI1_RST            ((8UL<<24) | SYS_IPRST2_QEI1RST_Pos)        /*!< Reset QEI1 \hideinitializer */
    91. 

  91. #define ECAP0_RST           ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos)       /*!< Reset ECAP0 \hideinitializer */
    92. 

  92. #define ECAP1_RST           ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos)       /*!< Reset ECAP1 \hideinitializer */
    93. 

  93. #define CAN2_RST            ((8UL<<24) | SYS_IPRST2_CAN2RST_Pos)        /*!< Reset CAN2 \hideinitializer */
    94. 

  94. #define OPA_RST             ((8UL<<24) | SYS_IPRST2_OPARST_Pos)         /*!< Reset OPA \hideinitializer */
    95. 

  95. #define EADC1_RST           ((8UL<<24) | SYS_IPRST2_EADC1RST_Pos)       /*!< Reset EADC1 \hideinitializer */
    96. 

  96. 

  97. /*---------------------------------------------------------------------------------------------------------*/
    98. 

  98. /*  Brown Out Detector Threshold Voltage Selection constant definitions.                                   */
    99. 

  99. /*---------------------------------------------------------------------------------------------------------*/
    100. 

  100. #define SYS_BODCTL_BOD_RST_EN           (1UL << SYS_BODCTL_BODRSTEN_Pos)    /*!< Brown-out Reset Enable \hideinitializer */
    101. 

  101. #define SYS_BODCTL_BOD_INTERRUPT_EN     (0UL << SYS_BODCTL_BODRSTEN_Pos)    /*!< Brown-out Interrupt Enable \hideinitializer */
    102. 

  102. #define SYS_BODCTL_BODVL_3_0V           (7UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */
    103. 

  103. #define SYS_BODCTL_BODVL_2_8V           (6UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */
    104. 

  104. #define SYS_BODCTL_BODVL_2_6V           (5UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */
    105. 

  105. #define SYS_BODCTL_BODVL_2_4V           (4UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */
    106. 

  106. #define SYS_BODCTL_BODVL_2_2V           (3UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */
    107. 

  107. #define SYS_BODCTL_BODVL_2_0V           (2UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */
    108. 

  108. #define SYS_BODCTL_BODVL_1_8V           (1UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */
    109. 

  109. #define SYS_BODCTL_BODVL_1_6V           (0UL << SYS_BODCTL_BODVL_Pos)       /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */
    110. 

  110. 

  111. 

  112. /*---------------------------------------------------------------------------------------------------------*/
    113. 

  113. /*  VREFCTL constant definitions. (Write-Protection Register)                                              */
    114. 

  114. /*---------------------------------------------------------------------------------------------------------*/
    115. 

  115. #define SYS_VREFCTL_VREF_PIN        (0x0UL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = Vref pin \hideinitializer */
    116. 

  116. #define SYS_VREFCTL_VREF_1_6V       (0x3UL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = 1.6V \hideinitializer */
    117. 

  117. #define SYS_VREFCTL_VREF_2_0V       (0x7UL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = 2.0V \hideinitializer */
    118. 

  118. #define SYS_VREFCTL_VREF_2_5V       (0xBUL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = 2.5V \hideinitializer */
    119. 

  119. #define SYS_VREFCTL_VREF_3_0V       (0xFUL << SYS_VREFCTL_VREFCTL_Pos)    /*!< Vref = 3.0V \hideinitializer */
    120. 

  120. #define SYS_VREFCTL_VREF_AVDD       (0x10UL << SYS_VREFCTL_VREFCTL_Pos)   /*!< Vref = AVDD \hideinitializer */
    121. 

  121. 

  122. 

  123. /*---------------------------------------------------------------------------------------------------------*/
    124. 

  124. /*  USBPHY constant definitions. (Write-Protection Register)                                               */
    125. 

  125. /*---------------------------------------------------------------------------------------------------------*/
    126. 

  126. #define SYS_USBPHY_USBROLE_STD_USBD     (0x0UL << SYS_USBPHY_USBROLE_Pos)   /*!<  Standard USB device \hideinitializer */
    127. 

  127. #define SYS_USBPHY_USBROLE_STD_USBH     (0x1UL << SYS_USBPHY_USBROLE_Pos)   /*!<  Standard USB host \hideinitializer */
    128. 

  128. #define SYS_USBPHY_USBROLE_ID_DEPH      (0x2UL << SYS_USBPHY_USBROLE_Pos)   /*!<  ID dependent device \hideinitializer */
    129. 

  129. #define SYS_USBPHY_USBROLE_ON_THE_GO    (0x3UL << SYS_USBPHY_USBROLE_Pos)   /*!<  On-The-Go device \hideinitializer */
    130. 

  130. #define SYS_USBPHY_HSUSBROLE_STD_USBD   (0x0UL << SYS_USBPHY_HSUSBROLE_Pos)   /*!<  Standard HSUSB device \hideinitializer */
    131. 

  131. #define SYS_USBPHY_HSUSBROLE_STD_USBH   (0x1UL << SYS_USBPHY_HSUSBROLE_Pos)   /*!<  Standard HSUSB host \hideinitializer */
    132. 

  132. #define SYS_USBPHY_HSUSBROLE_ID_DEPH    (0x2UL << SYS_USBPHY_HSUSBROLE_Pos)   /*!<  ID dependent device \hideinitializer */
    133. 

  133. 

  134. /*---------------------------------------------------------------------------------------------------------*/
    135. 

  135. /*  PLCTL constant definitions. (Write-Protection Register)                                                */
    136. 

  136. /*---------------------------------------------------------------------------------------------------------*/
    137. 

  137. #define SYS_PLCTL_PLSEL_PL0     (0x0UL<<SYS_PLCTL_PLSEL_Pos)   /*!< Set power level to power level 0 */
    138. 

  138. #define SYS_PLCTL_PLSEL_PL1     (0x1UL<<SYS_PLCTL_PLSEL_Pos)   /*!< Set power level to power level 1 */
    139. 

  139. 

  140. 

  141. /*---------------------------------------------------------------------------------------------------------*/
    142. 

  142. /*  Multi-Function constant definitions.                                                                   */
    143. 

  143. /*---------------------------------------------------------------------------------------------------------*/
    144. 

  144. /* How to use below #define?
    145. 

  145. Example 1: If user want to set PA.0 as SC0_CLK in initial function,
    146. 

  146.            user can issue following command to achieve it.
    147. 

  147. 

  148.            SYS->GPA_MFPL  = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK  ;
    149. 

  149. 

  150. */
    151. 

  151. /********************* Bit definition of GPA_MFPL register **********************/
    152. 

  152. #define SYS_GPA_MFPL_PA0MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    153. 

  153. #define SYS_GPA_MFPL_PA0MFP_SPIM_MOSI         (0x02UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
    154. 

  154. #define SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0       (0x03UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< 1st QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    155. 

  155. #define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI         (0x04UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    156. 

  156. #define SYS_GPA_MFPL_PA0MFP_SD1_DAT0          (0x05UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
    157. 

  157. #define SYS_GPA_MFPL_PA0MFP_SC0_CLK           (0x06UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< SmartCard0 clock pin. \hideinitializer */
    158. 

  158. #define SYS_GPA_MFPL_PA0MFP_UART0_RXD         (0x07UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
    159. 

  159. #define SYS_GPA_MFPL_PA0MFP_UART1_nRTS        (0x08UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< Request to Send output pin for UART1. \hideinitializer */
    160. 

  160. #define SYS_GPA_MFPL_PA0MFP_I2C2_SDA          (0x09UL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< I2C2 data input/output pin. \hideinitializer */
    161. 

  161. #define SYS_GPA_MFPL_PA0MFP_CCAP_DATA6        (0x0AUL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< Sensor pixel data6 input pin. \hideinitializer */
    162. 

  162. #define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0         (0x0CUL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< BPWM0 channel0 output/capture input. \hideinitializer */
    163. 

  163. #define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5         (0x0DUL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< EPWM0 channel5 output/capture input. \hideinitializer */
    164. 

  164. #define SYS_GPA_MFPL_PA0MFP_DAC0_ST           (0x0FUL<<SYS_GPA_MFPL_PA0MFP_Pos)  /*!< DAC0 external trigger input. \hideinitializer */
    165. 

  165. #define SYS_GPA_MFPL_PA1MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    166. 

  166. #define SYS_GPA_MFPL_PA1MFP_SPIM_MISO         (0x02UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
    167. 

  167. #define SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0       (0x03UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< 1st QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    168. 

  168. #define SYS_GPA_MFPL_PA1MFP_SPI0_MISO         (0x04UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    169. 

  169. #define SYS_GPA_MFPL_PA1MFP_SD1_DAT1          (0x05UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
    170. 

  170. #define SYS_GPA_MFPL_PA1MFP_SC0_DAT           (0x06UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< SmartCard0 data pin. \hideinitializer */
    171. 

  171. #define SYS_GPA_MFPL_PA1MFP_UART0_TXD         (0x07UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
    172. 

  172. #define SYS_GPA_MFPL_PA1MFP_UART1_nCTS        (0x08UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< Clear to Send input pin for UART1. \hideinitializer */
    173. 

  173. #define SYS_GPA_MFPL_PA1MFP_I2C2_SCL          (0x09UL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< I2C2 clock pin. \hideinitializer */
    174. 

  174. #define SYS_GPA_MFPL_PA1MFP_CCAP_DATA7        (0x0AUL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< Sensor pixel data7 input pin. \hideinitializer */
    175. 

  175. #define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1         (0x0CUL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< BPWM0 channel1 output/capture input. \hideinitializer */
    176. 

  176. #define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4         (0x0DUL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< EPWM0 channel4 output/capture input. \hideinitializer */
    177. 

  177. #define SYS_GPA_MFPL_PA1MFP_DAC1_ST           (0x0FUL<<SYS_GPA_MFPL_PA1MFP_Pos)  /*!< DAC1 external trigger input. \hideinitializer */
    178. 

  178. #define SYS_GPA_MFPL_PA2MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    179. 

  179. #define SYS_GPA_MFPL_PA2MFP_SPIM_CLK          (0x02UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< SPIM serial clock pin. \hideinitializer */
    180. 

  180. #define SYS_GPA_MFPL_PA2MFP_QSPI0_CLK         (0x03UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< QSPI0 serial clock pin. \hideinitializer */
    181. 

  181. #define SYS_GPA_MFPL_PA2MFP_SPI0_CLK          (0x04UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< SPI0 serial clock pin. \hideinitializer */
    182. 

  182. #define SYS_GPA_MFPL_PA2MFP_SD1_DAT2          (0x05UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
    183. 

  183. #define SYS_GPA_MFPL_PA2MFP_SC0_RST           (0x06UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< SmartCard0 reset pin. \hideinitializer */
    184. 

  184. #define SYS_GPA_MFPL_PA2MFP_UART4_RXD         (0x07UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
    185. 

  185. #define SYS_GPA_MFPL_PA2MFP_UART1_RXD         (0x08UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
    186. 

  186. #define SYS_GPA_MFPL_PA2MFP_I2C1_SDA          (0x09UL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
    187. 

  187. #define SYS_GPA_MFPL_PA2MFP_I2C0_SMBSUS       (0x0AUL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
    188. 

  188. #define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2         (0x0CUL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< BPWM0 channel2 output/capture input. \hideinitializer */
    189. 

  189. #define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3         (0x0DUL<<SYS_GPA_MFPL_PA2MFP_Pos)  /*!< EPWM0 channel3 output/capture input. \hideinitializer */
    190. 

  190. #define SYS_GPA_MFPL_PA3MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    191. 

  191. #define SYS_GPA_MFPL_PA3MFP_SPIM_SS           (0x02UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< 1st SPIM slave select pin. \hideinitializer */
    192. 

  192. #define SYS_GPA_MFPL_PA3MFP_QSPI0_SS          (0x03UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< 1st QSPI0 slave select pin. \hideinitializer */
    193. 

  193. #define SYS_GPA_MFPL_PA3MFP_SPI0_SS           (0x04UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< 1st SPI0 slave select pin. \hideinitializer */
    194. 

  194. #define SYS_GPA_MFPL_PA3MFP_SD1_DAT3          (0x05UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
    195. 

  195. #define SYS_GPA_MFPL_PA3MFP_SC0_PWR           (0x06UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< SmartCard0 power pin. \hideinitializer */
    196. 

  196. #define SYS_GPA_MFPL_PA3MFP_UART4_TXD         (0x07UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
    197. 

  197. #define SYS_GPA_MFPL_PA3MFP_UART1_TXD         (0x08UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
    198. 

  198. #define SYS_GPA_MFPL_PA3MFP_I2C1_SCL          (0x09UL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
    199. 

  199. #define SYS_GPA_MFPL_PA3MFP_I2C0_SMBAL        (0x0AUL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< I2C0 SMBus SMBALTER# pin. \hideinitializer */
    200. 

  200. #define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3         (0x0CUL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< BPWM0 channel3 output/capture input. \hideinitializer */
    201. 

  201. #define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2         (0x0DUL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< EPWM0 channel2 output/capture input. \hideinitializer */
    202. 

  202. #define SYS_GPA_MFPL_PA3MFP_QEI0_B            (0x0EUL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
    203. 

  203. #define SYS_GPA_MFPL_PA3MFP_EPWM1_BRAKE1      (0x0FUL<<SYS_GPA_MFPL_PA3MFP_Pos)  /*!< Brake input pin 1 of EPWM1. \hideinitializer */
    204. 

  204. #define SYS_GPA_MFPL_PA4MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    205. 

  205. #define SYS_GPA_MFPL_PA4MFP_SPIM_D3           (0x02UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
    206. 

  206. #define SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1       (0x03UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< 2nd QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    207. 

  207. #define SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK      (0x04UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< SPI0 I2S master clock output pin. \hideinitializer */
    208. 

  208. #define SYS_GPA_MFPL_PA4MFP_SD1_CLK           (0x05UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< SD/SDIO 1 clock. \hideinitializer */
    209. 

  209. #define SYS_GPA_MFPL_PA4MFP_SC0_nCD           (0x06UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< SmartCard0 card detect pin. \hideinitializer */
    210. 

  210. #define SYS_GPA_MFPL_PA4MFP_UART0_nRTS        (0x07UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< Request to Send output pin for UART0. \hideinitializer */
    211. 

  211. #define SYS_GPA_MFPL_PA4MFP_UART5_RXD         (0x08UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< Data receiver input pin for UART5. \hideinitializer */
    212. 

  212. #define SYS_GPA_MFPL_PA4MFP_I2C0_SDA          (0x09UL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
    213. 

  213. #define SYS_GPA_MFPL_PA4MFP_CAN0_RXD          (0x0AUL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< CAN0 bus receiver input. \hideinitializer */
    214. 

  214. #define SYS_GPA_MFPL_PA4MFP_UART0_RXD         (0x0BUL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
    215. 

  215. #define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4         (0x0CUL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< BPWM0 channel4 output/capture input. \hideinitializer */
    216. 

  216. #define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1         (0x0DUL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
    217. 

  217. #define SYS_GPA_MFPL_PA4MFP_QEI0_A            (0x0EUL<<SYS_GPA_MFPL_PA4MFP_Pos)  /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
    218. 

  218. #define SYS_GPA_MFPL_PA5MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    219. 

  219. #define SYS_GPA_MFPL_PA5MFP_SPIM_D2           (0x02UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
    220. 

  220. #define SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1       (0x03UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< 2nd QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    221. 

  221. #define SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK      (0x04UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< SPI1 I2S master clock output pin. \hideinitializer */
    222. 

  222. #define SYS_GPA_MFPL_PA5MFP_SD1_CMD           (0x05UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< SD/SDIO 1 command/response. \hideinitializer */
    223. 

  223. #define SYS_GPA_MFPL_PA5MFP_SC2_nCD           (0x06UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< SmartCard2 card detect pin. \hideinitializer */
    224. 

  224. #define SYS_GPA_MFPL_PA5MFP_UART0_nCTS        (0x07UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< Clear to Send input pin for UART0. \hideinitializer */
    225. 

  225. #define SYS_GPA_MFPL_PA5MFP_UART5_TXD         (0x08UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< Data transmitter output pin for UART5. \hideinitializer */
    226. 

  226. #define SYS_GPA_MFPL_PA5MFP_I2C0_SCL          (0x09UL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
    227. 

  227. #define SYS_GPA_MFPL_PA5MFP_CAN0_TXD          (0x0AUL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< CAN0 bus transmitter output. \hideinitializer */
    228. 

  228. #define SYS_GPA_MFPL_PA5MFP_UART0_TXD         (0x0BUL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
    229. 

  229. #define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5         (0x0CUL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< BPWM0 channel5 output/capture input. \hideinitializer */
    230. 

  230. #define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0         (0x0DUL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
    231. 

  231. #define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX        (0x0EUL<<SYS_GPA_MFPL_PA5MFP_Pos)  /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
    232. 

  232. #define SYS_GPA_MFPL_PA6MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    233. 

  233. #define SYS_GPA_MFPL_PA6MFP_EBI_AD6           (0x02UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< EBI address/data bus bit6. \hideinitializer */
    234. 

  234. #define SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR   (0x03UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< RMII Receive Data error. \hideinitializer */
    235. 

  235. #define SYS_GPA_MFPL_PA6MFP_SPI1_SS           (0x04UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< 1st SPI1 slave select pin. \hideinitializer */
    236. 

  236. #define SYS_GPA_MFPL_PA6MFP_SD1_nCD           (0x05UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< SD/SDIO 1 card detect  \hideinitializer */
    237. 

  237. #define SYS_GPA_MFPL_PA6MFP_SC2_CLK           (0x06UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< SmartCard2 clock pin. \hideinitializer */
    238. 

  238. #define SYS_GPA_MFPL_PA6MFP_UART0_RXD         (0x07UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
    239. 

  239. #define SYS_GPA_MFPL_PA6MFP_I2C1_SDA          (0x08UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
    240. 

  240. #define SYS_GPA_MFPL_PA6MFP_QSPI1_MOSI1       (0x09UL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< 2nd QSPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    241. 

  241. #define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5         (0x0BUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< EPWM1 channel5 output/capture input. \hideinitializer */
    242. 

  242. #define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3         (0x0CUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< BPWM1 channel3 output/capture input. \hideinitializer */
    243. 

  243. #define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT        (0x0DUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< Analog comparator1 window latch input pin. \hideinitializer */
    244. 

  244. #define SYS_GPA_MFPL_PA6MFP_TM3               (0x0EUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< Timer3 event counter input / toggle output  \hideinitializer */
    245. 

  245. #define SYS_GPA_MFPL_PA6MFP_INT0              (0x0FUL<<SYS_GPA_MFPL_PA6MFP_Pos)  /*!< External interrupt0 input pin. \hideinitializer */
    246. 

  246. #define SYS_GPA_MFPL_PA7MFP_GPIO              (0x00UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    247. 

  247. #define SYS_GPA_MFPL_PA7MFP_EBI_AD7           (0x02UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< EBI address/data bus bit7. \hideinitializer */
    248. 

  248. #define SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV   (0x03UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */
    249. 

  249. #define SYS_GPA_MFPL_PA7MFP_SPI1_CLK          (0x04UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< SPI1 serial clock pin. \hideinitializer */
    250. 

  250. #define SYS_GPA_MFPL_PA7MFP_SC2_DAT           (0x06UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< SmartCard2 data pin. \hideinitializer */
    251. 

  251. #define SYS_GPA_MFPL_PA7MFP_UART0_TXD         (0x07UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
    252. 

  252. #define SYS_GPA_MFPL_PA7MFP_I2C1_SCL          (0x08UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
    253. 

  253. #define SYS_GPA_MFPL_PA7MFP_QSPI1_MISO1       (0x09UL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< 2nd QSPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    254. 

  254. #define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4         (0x0BUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< EPWM1 channel4 output/capture input. \hideinitializer */
    255. 

  255. #define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2         (0x0CUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< BPWM1 channel2 output/capture input. \hideinitializer */
    256. 

  256. #define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT        (0x0DUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< Analog comparator0 window latch input pin. \hideinitializer */
    257. 

  257. #define SYS_GPA_MFPL_PA7MFP_TM2               (0x0EUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
    258. 

  258. #define SYS_GPA_MFPL_PA7MFP_INT1              (0x0FUL<<SYS_GPA_MFPL_PA7MFP_Pos)  /*!< External interrupt1 input pin. \hideinitializer */
    259. 

  259. /********************* Bit definition of GPA_MFPH register **********************/
    260. 

  260. #define SYS_GPA_MFPH_PA8MFP_GPIO              (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    261. 

  261. #define SYS_GPA_MFPH_PA8MFP_OPA1_P            (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Operational amplifier positive input pin. \hideinitializer */
    262. 

  262. #define SYS_GPA_MFPH_PA8MFP_EADC1_CH4         (0x01UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< EADC1 channel4 analog input. \hideinitializer */
    263. 

  263. #define SYS_GPA_MFPH_PA8MFP_EBI_ALE           (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< EBI address latch enable output pin. \hideinitializer */
    264. 

  264. #define SYS_GPA_MFPH_PA8MFP_SC2_CLK           (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< SmartCard2 clock pin. \hideinitializer */
    265. 

  265. #define SYS_GPA_MFPH_PA8MFP_SPI2_MOSI         (0x04UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
    266. 

  266. #define SYS_GPA_MFPH_PA8MFP_SD1_DAT0          (0x05UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
    267. 

  267. #define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1        (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< USCI0 control1 pin. \hideinitializer */
    268. 

  268. #define SYS_GPA_MFPH_PA8MFP_UART1_RXD         (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
    269. 

  269. #define SYS_GPA_MFPH_PA8MFP_UART7_RXD         (0x08UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Data receiver input pin for UART7. \hideinitializer */
    270. 

  270. #define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3         (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< BPWM0 channel3 output/capture input. \hideinitializer */
    271. 

  271. #define SYS_GPA_MFPH_PA8MFP_QEI1_B            (0x0AUL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
    272. 

  272. #define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2         (0x0BUL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Input 0 of enhanced capture unit 2. \hideinitializer */
    273. 

  273. #define SYS_GPA_MFPH_PA8MFP_TM3_EXT           (0x0DUL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< Timer3 event counter input / toggle output  \hideinitializer */
    274. 

  274. #define SYS_GPA_MFPH_PA8MFP_INT4              (0x0FUL<<SYS_GPA_MFPH_PA8MFP_Pos)  /*!< External interrupt4 input pin. \hideinitializer */
    275. 

  275. #define SYS_GPA_MFPH_PA9MFP_GPIO              (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    276. 

  276. #define SYS_GPA_MFPH_PA9MFP_OPA1_N            (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Operational amplifier negative input pin. \hideinitializer */
    277. 

  277. #define SYS_GPA_MFPH_PA9MFP_EADC1_CH5         (0x01UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< EADC1 channel5 analog input. \hideinitializer */
    278. 

  278. #define SYS_GPA_MFPH_PA9MFP_EBI_MCLK          (0x02UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< EBI external clock output pin. \hideinitializer */
    279. 

  279. #define SYS_GPA_MFPH_PA9MFP_SC2_DAT           (0x03UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< SmartCard2 data pin. \hideinitializer */
    280. 

  280. #define SYS_GPA_MFPH_PA9MFP_SPI2_MISO         (0x04UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
    281. 

  281. #define SYS_GPA_MFPH_PA9MFP_SD1_DAT1          (0x05UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
    282. 

  282. #define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1        (0x06UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< USCI0 data1 pin. \hideinitializer */
    283. 

  283. #define SYS_GPA_MFPH_PA9MFP_UART1_TXD         (0x07UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
    284. 

  284. #define SYS_GPA_MFPH_PA9MFP_UART7_TXD         (0x08UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Data transmitter output pin for UART7. \hideinitializer */
    285. 

  285. #define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2         (0x09UL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< BPWM0 channel2 output/capture input. \hideinitializer */
    286. 

  286. #define SYS_GPA_MFPH_PA9MFP_QEI1_A            (0x0AUL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
    287. 

  287. #define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1         (0x0BUL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Input 1 of enhanced capture unit 0. \hideinitializer */
    288. 

  288. #define SYS_GPA_MFPH_PA9MFP_TM2_EXT           (0x0DUL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
    289. 

  289. #define SYS_GPA_MFPH_PA9MFP_SWDH_DAT          (0x0FUL<<SYS_GPA_MFPH_PA9MFP_Pos)  /*!< SWD Host interface input/output bus bit. \hideinitializer */
    290. 

  290. #define SYS_GPA_MFPH_PA10MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    291. 

  291. #define SYS_GPA_MFPH_PA10MFP_ACMP1_P0         (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
    292. 

  292. #define SYS_GPA_MFPH_PA10MFP_OPA1_O           (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
    293. 

  293. #define SYS_GPA_MFPH_PA10MFP_EADC1_CH6        (0x01UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< EADC1 channel6 analog input. \hideinitializer */
    294. 

  294. #define SYS_GPA_MFPH_PA10MFP_EBI_nWR          (0x02UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< EBI write enable output pin. \hideinitializer */
    295. 

  295. #define SYS_GPA_MFPH_PA10MFP_SC2_RST          (0x03UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
    296. 

  296. #define SYS_GPA_MFPH_PA10MFP_SPI2_CLK         (0x04UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
    297. 

  297. #define SYS_GPA_MFPH_PA10MFP_SD1_DAT2         (0x05UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
    298. 

  298. #define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0       (0x06UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
    299. 

  299. #define SYS_GPA_MFPH_PA10MFP_I2C2_SDA         (0x07UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
    300. 

  300. #define SYS_GPA_MFPH_PA10MFP_UART6_RXD        (0x08UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
    301. 

  301. #define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1        (0x09UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
    302. 

  302. #define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX       (0x0AUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
    303. 

  303. #define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0        (0x0BUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Input 0 of enhanced capture unit 0. \hideinitializer */
    304. 

  304. #define SYS_GPA_MFPH_PA10MFP_TM1_EXT          (0x0DUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< Timer1 event counter input / toggle output  \hideinitializer */
    305. 

  305. #define SYS_GPA_MFPH_PA10MFP_DAC0_ST          (0x0EUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< DAC0 external trigger input. \hideinitializer */
    306. 

  306. #define SYS_GPA_MFPH_PA10MFP_SWDH_CLK         (0x0FUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< SWD Host interface clock output pin. \hideinitializer */
    307. 

  307. #define SYS_GPA_MFPH_PA11MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    308. 

  308. #define SYS_GPA_MFPH_PA11MFP_ACMP0_P0         (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
    309. 

  309. #define SYS_GPA_MFPH_PA11MFP_EADC1_CH7        (0x01UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EADC1 channel7 analog input. \hideinitializer */
    310. 

  310. #define SYS_GPA_MFPH_PA11MFP_EBI_nRD          (0x02UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EBI read enable output pin. \hideinitializer */
    311. 

  311. #define SYS_GPA_MFPH_PA11MFP_SC2_PWR          (0x03UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
    312. 

  312. #define SYS_GPA_MFPH_PA11MFP_SPI2_SS          (0x04UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
    313. 

  313. #define SYS_GPA_MFPH_PA11MFP_SD1_DAT3         (0x05UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
    314. 

  314. #define SYS_GPA_MFPH_PA11MFP_USCI0_CLK        (0x06UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
    315. 

  315. #define SYS_GPA_MFPH_PA11MFP_I2C2_SCL         (0x07UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
    316. 

  316. #define SYS_GPA_MFPH_PA11MFP_UART6_TXD        (0x08UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Data transmitter output pin for UART6. \hideinitializer */
    317. 

  317. #define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0        (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
    318. 

  318. #define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT   (0x0AUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */
    319. 

  319. #define SYS_GPA_MFPH_PA11MFP_TM0_EXT          (0x0DUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
    320. 

  320. #define SYS_GPA_MFPH_PA11MFP_DAC1_ST          (0x0EUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< DAC1 external trigger input. \hideinitializer */
    321. 

  321. #define SYS_GPA_MFPH_PA12MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    322. 

  322. #define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK        (0x02UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
    323. 

  323. #define SYS_GPA_MFPH_PA12MFP_UART4_TXD        (0x03UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
    324. 

  324. #define SYS_GPA_MFPH_PA12MFP_I2C1_SCL         (0x04UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
    325. 

  325. #define SYS_GPA_MFPH_PA12MFP_SPI2_SS          (0x05UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
    326. 

  326. #define SYS_GPA_MFPH_PA12MFP_CAN0_TXD         (0x06UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
    327. 

  327. #define SYS_GPA_MFPH_PA12MFP_SC2_PWR          (0x07UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< SmartCard2 power pin. \hideinitializer */
    328. 

  328. #define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2        (0x0BUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< BPWM1 channel2 output/capture input. \hideinitializer */
    329. 

  329. #define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX       (0x0CUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
    330. 

  330. #define SYS_GPA_MFPH_PA12MFP_USB_VBUS         (0x0EUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
    331. 

  331. #define SYS_GPA_MFPH_PA13MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    332. 

  332. #define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK        (0x02UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2S0 master clock output pin. \hideinitializer */
    333. 

  333. #define SYS_GPA_MFPH_PA13MFP_UART4_RXD        (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
    334. 

  334. #define SYS_GPA_MFPH_PA13MFP_I2C1_SDA         (0x04UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
    335. 

  335. #define SYS_GPA_MFPH_PA13MFP_SPI2_CLK         (0x05UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SPI2 serial clock pin. \hideinitializer */
    336. 

  336. #define SYS_GPA_MFPH_PA13MFP_CAN0_RXD         (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
    337. 

  337. #define SYS_GPA_MFPH_PA13MFP_SC2_RST          (0x07UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< SmartCard2 reset pin. \hideinitializer */
    338. 

  338. #define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3        (0x0BUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< BPWM1 channel3 output/capture input. \hideinitializer */
    339. 

  339. #define SYS_GPA_MFPH_PA13MFP_QEI1_A           (0x0CUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
    340. 

  340. #define SYS_GPA_MFPH_PA13MFP_USB_D_N          (0x0EUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< USB Full speed differential signal D-. \hideinitializer */
    341. 

  341. #define SYS_GPA_MFPH_PA14MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    342. 

  342. #define SYS_GPA_MFPH_PA14MFP_I2S0_DI          (0x02UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2S0 data input. \hideinitializer */
    343. 

  343. #define SYS_GPA_MFPH_PA14MFP_UART0_TXD        (0x03UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
    344. 

  344. #define SYS_GPA_MFPH_PA14MFP_SPI2_MISO        (0x05UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
    345. 

  345. #define SYS_GPA_MFPH_PA14MFP_I2C2_SCL         (0x06UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
    346. 

  346. #define SYS_GPA_MFPH_PA14MFP_SC2_DAT          (0x07UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< SmartCard2 data pin. \hideinitializer */
    347. 

  347. #define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4        (0x0BUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< BPWM1 channel4 output/capture input. \hideinitializer */
    348. 

  348. #define SYS_GPA_MFPH_PA14MFP_QEI1_B           (0x0CUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
    349. 

  349. #define SYS_GPA_MFPH_PA14MFP_USB_D_P          (0x0EUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< USB Full speed differential signal D+. \hideinitializer */
    350. 

  350. #define SYS_GPA_MFPH_PA15MFP_GPIO             (0x00UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    351. 

  351. #define SYS_GPA_MFPH_PA15MFP_I2S0_DO          (0x02UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2S0 data output. \hideinitializer */
    352. 

  352. #define SYS_GPA_MFPH_PA15MFP_UART0_RXD        (0x03UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
    353. 

  353. #define SYS_GPA_MFPH_PA15MFP_SPI2_MOSI        (0x05UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
    354. 

  354. #define SYS_GPA_MFPH_PA15MFP_I2C2_SDA         (0x06UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
    355. 

  355. #define SYS_GPA_MFPH_PA15MFP_SC2_CLK          (0x07UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< SmartCard2 clock pin. \hideinitializer */
    356. 

  356. #define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5        (0x0BUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
    357. 

  357. #define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN    (0x0CUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */
    358. 

  358. #define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID       (0x0EUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< USB Full speed identification. \hideinitializer */
    359. 

  359. /********************* Bit definition of GPB_MFPL register **********************/
    360. 

  360. #define SYS_GPB_MFPL_PB0MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    361. 

  361. #define SYS_GPB_MFPL_PB0MFP_EADC0_CH0         (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< EADC0 channel0 analog input. \hideinitializer */
    362. 

  362. #define SYS_GPB_MFPL_PB0MFP_EADC1_CH8         (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< EADC1 channel8 analog input. \hideinitializer */
    363. 

  363. #define SYS_GPB_MFPL_PB0MFP_OPA0_P            (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< Operational amplifier positive input pin. \hideinitializer */
    364. 

  364. #define SYS_GPB_MFPL_PB0MFP_EBI_ADR9          (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    365. 

  365. #define SYS_GPB_MFPL_PB0MFP_SD0_CMD           (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< SD/SDIO 0 command/response. \hideinitializer */
    366. 

  366. #define SYS_GPB_MFPL_PB0MFP_SPI2_I2SMCLK      (0x04UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< SPI2 I2S master clock output pin. \hideinitializer */
    367. 

  367. #define SYS_GPB_MFPL_PB0MFP_UART2_RXD         (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
    368. 

  368. #define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK      (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< SPI0 I2S master clock output pin. \hideinitializer */
    369. 

  369. #define SYS_GPB_MFPL_PB0MFP_I2C1_SDA          (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
    370. 

  370. #define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5         (0x0BUL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< EPWM0 channel5 output/capture input. \hideinitializer */
    371. 

  371. #define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5         (0x0CUL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< EPWM1 channel5 output/capture input. \hideinitializer */
    372. 

  372. #define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1      (0x0DUL<<SYS_GPB_MFPL_PB0MFP_Pos)  /*!< Brake input pin 1 of EPWM0. \hideinitializer */
    373. 

  373. #define SYS_GPB_MFPL_PB1MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    374. 

  374. #define SYS_GPB_MFPL_PB1MFP_EADC0_CH1         (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< EADC0 channel1 analog input. \hideinitializer */
    375. 

  375. #define SYS_GPB_MFPL_PB1MFP_OPA0_N            (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< Operational amplifier negative input pin. \hideinitializer */
    376. 

  376. #define SYS_GPB_MFPL_PB1MFP_EADC1_CH9         (0x01UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< EADC1 channel9 analog input. \hideinitializer */
    377. 

  377. #define SYS_GPB_MFPL_PB1MFP_EBI_ADR8          (0x02UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    378. 

  378. #define SYS_GPB_MFPL_PB1MFP_SD0_CLK           (0x03UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< SD/SDIO 0 clock. \hideinitializer */
    379. 

  379. #define SYS_GPB_MFPL_PB1MFP_EMAC_RMII_RXERR   (0x04UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< RMII Receive Data error. \hideinitializer */
    380. 

  380. #define SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK      (0x05UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< SPI1 I2S master clock output pin. \hideinitializer */
    381. 

  381. #define SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK      (0x06UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< SPI3 I2S master clock output pin. \hideinitializer */
    382. 

  382. #define SYS_GPB_MFPL_PB1MFP_UART2_TXD         (0x07UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
    383. 

  383. #define SYS_GPB_MFPL_PB1MFP_USCI1_CLK         (0x08UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< USCI1 clock pin. \hideinitializer */
    384. 

  384. #define SYS_GPB_MFPL_PB1MFP_I2C1_SCL          (0x09UL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
    385. 

  385. #define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK         (0x0AUL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< I2S0 left right channel clock. \hideinitializer */
    386. 

  386. #define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4         (0x0BUL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< EPWM0 channel4 output/capture input. \hideinitializer */
    387. 

  387. #define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4         (0x0CUL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< EPWM1 channel4 output/capture input. \hideinitializer */
    388. 

  388. #define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0      (0x0DUL<<SYS_GPB_MFPL_PB1MFP_Pos)  /*!< Brake input pin 0 of EPWM0. \hideinitializer */
    389. 

  389. #define SYS_GPB_MFPL_PB2MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    390. 

  390. #define SYS_GPB_MFPL_PB2MFP_ACMP0_P1          (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Analog comparator0 positive input pin. \hideinitializer */
    391. 

  391. #define SYS_GPB_MFPL_PB2MFP_EADC0_CH2         (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< EADC0 channel2 analog input. \hideinitializer */
    392. 

  392. #define SYS_GPB_MFPL_PB2MFP_OPA0_O            (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Operational amplifier output pin. \hideinitializer */
    393. 

  393. #define SYS_GPB_MFPL_PB2MFP_EADC1_CH10        (0x01UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< EADC1 channel1 analog input. \hideinitializer */
    394. 

  394. #define SYS_GPB_MFPL_PB2MFP_EBI_ADR3          (0x02UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    395. 

  395. #define SYS_GPB_MFPL_PB2MFP_SD0_DAT0          (0x03UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< SD/SDIO 0 data line bit 0. \hideinitializer */
    396. 

  396. #define SYS_GPB_MFPL_PB2MFP_EMAC_RMII_CRSDV   (0x04UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< MII Receive Data Valid / RMII CRS_DV input. \hideinitializer */
    397. 

  397. #define SYS_GPB_MFPL_PB2MFP_SPI1_SS           (0x05UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< 1st SPI1 slave select pin. \hideinitializer */
    398. 

  398. #define SYS_GPB_MFPL_PB2MFP_UART1_RXD         (0x06UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
    399. 

  399. #define SYS_GPB_MFPL_PB2MFP_UART5_nCTS        (0x07UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Clear to Send input pin for UART5. \hideinitializer */
    400. 

  400. #define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0        (0x08UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< USCI1 data0 pin. \hideinitializer */
    401. 

  401. #define SYS_GPB_MFPL_PB2MFP_SC0_PWR           (0x09UL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< SmartCard0 power pin. \hideinitializer */
    402. 

  402. #define SYS_GPB_MFPL_PB2MFP_I2S0_DO           (0x0AUL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< I2S0 data output. \hideinitializer */
    403. 

  403. #define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3         (0x0BUL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< EPWM0 channel3 output/capture input. \hideinitializer */
    404. 

  404. #define SYS_GPB_MFPL_PB2MFP_I2C1_SDA          (0x0CUL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< I2C1 data input/output pin. */
    405. 

  405. #define SYS_GPB_MFPL_PB2MFP_TM3               (0x0EUL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< Timer3 event counter input / toggle output  \hideinitializer */
    406. 

  406. #define SYS_GPB_MFPL_PB2MFP_INT3              (0x0FUL<<SYS_GPB_MFPL_PB2MFP_Pos)  /*!< External interrupt3 input pin. \hideinitializer */
    407. 

  407. #define SYS_GPB_MFPL_PB3MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    408. 

  408. #define SYS_GPB_MFPL_PB3MFP_ACMP0_N           (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< Analog comparator0 negative input pin. \hideinitializer */
    409. 

  409. #define SYS_GPB_MFPL_PB3MFP_EADC0_CH3         (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< EADC0 channel3 analog input. \hideinitializer */
    410. 

  410. #define SYS_GPB_MFPL_PB3MFP_EADC1_CH11        (0x01UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< EADC1 channel1 analog input. \hideinitializer */
    411. 

  411. #define SYS_GPB_MFPL_PB3MFP_EBI_ADR2          (0x02UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    412. 

  412. #define SYS_GPB_MFPL_PB3MFP_SD0_DAT1          (0x03UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< SD/SDIO 0 data line bit 1. \hideinitializer */
    413. 

  413. #define SYS_GPB_MFPL_PB3MFP_EMAC_RMII_RXD1    (0x04UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< RMII Receive Data bus bit 1. \hideinitializer */
    414. 

  414. #define SYS_GPB_MFPL_PB3MFP_SPI1_CLK          (0x05UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< SPI1 serial clock pin. \hideinitializer */
    415. 

  415. #define SYS_GPB_MFPL_PB3MFP_UART1_TXD         (0x06UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
    416. 

  416. #define SYS_GPB_MFPL_PB3MFP_UART5_nRTS        (0x07UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< Request to Send output pin for UART5. \hideinitializer */
    417. 

  417. #define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1        (0x08UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< USCI1 data1 pin. \hideinitializer */
    418. 

  418. #define SYS_GPB_MFPL_PB3MFP_SC0_RST           (0x09UL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< SmartCard0 reset pin. \hideinitializer */
    419. 

  419. #define SYS_GPB_MFPL_PB3MFP_I2S0_DI           (0x0AUL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< I2S0 data input. \hideinitializer */
    420. 

  420. #define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2         (0x0BUL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< EPWM0 channel2 output/capture input. \hideinitializer */
    421. 

  421. #define SYS_GPB_MFPL_PB3MFP_I2C1_SCL          (0x0CUL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< I2C1 clock pin. */
    422. 

  422. #define SYS_GPB_MFPL_PB3MFP_TM2               (0x0EUL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
    423. 

  423. #define SYS_GPB_MFPL_PB3MFP_INT2              (0x0FUL<<SYS_GPB_MFPL_PB3MFP_Pos)  /*!< External interrupt2 input pin. \hideinitializer */
    424. 

  424. #define SYS_GPB_MFPL_PB4MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    425. 

  425. #define SYS_GPB_MFPL_PB4MFP_ACMP1_P1          (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< Analog comparator1 positive input pin. \hideinitializer */
    426. 

  426. #define SYS_GPB_MFPL_PB4MFP_EADC0_CH4         (0x01UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< EADC0 channel4 analog input. \hideinitializer */
    427. 

  427. #define SYS_GPB_MFPL_PB4MFP_EBI_ADR1          (0x02UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    428. 

  428. #define SYS_GPB_MFPL_PB4MFP_SD0_DAT2          (0x03UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< SD/SDIO 0 data line bit 2. \hideinitializer */
    429. 

  429. #define SYS_GPB_MFPL_PB4MFP_EMAC_RMII_RXD0    (0x04UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< RMII Receive Data bus bit 0. \hideinitializer */
    430. 

  430. #define SYS_GPB_MFPL_PB4MFP_SPI1_MOSI         (0x05UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    431. 

  431. #define SYS_GPB_MFPL_PB4MFP_I2C0_SDA          (0x06UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
    432. 

  432. #define SYS_GPB_MFPL_PB4MFP_UART5_RXD         (0x07UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< Data receiver input pin for UART5. \hideinitializer */
    433. 

  433. #define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1        (0x08UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< USCI1 control1 pin. \hideinitializer */
    434. 

  434. #define SYS_GPB_MFPL_PB4MFP_SC0_DAT           (0x09UL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< SmartCard0 data pin. \hideinitializer */
    435. 

  435. #define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK         (0x0AUL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
    436. 

  436. #define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1         (0x0BUL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
    437. 

  437. #define SYS_GPB_MFPL_PB4MFP_UART2_RXD         (0x0CUL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
    438. 

  438. #define SYS_GPB_MFPL_PB4MFP_TM1               (0x0EUL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< Timer1 event counter input / toggle output  \hideinitializer */
    439. 

  439. #define SYS_GPB_MFPL_PB4MFP_INT1              (0x0FUL<<SYS_GPB_MFPL_PB4MFP_Pos)  /*!< External interrupt1 input pin. \hideinitializer */
    440. 

  440. #define SYS_GPB_MFPL_PB5MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    441. 

  441. #define SYS_GPB_MFPL_PB5MFP_ACMP1_N           (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< Analog comparator1 negative input pin. \hideinitializer */
    442. 

  442. #define SYS_GPB_MFPL_PB5MFP_EADC0_CH5         (0x01UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< EADC0 channel5 analog input. \hideinitializer */
    443. 

  443. #define SYS_GPB_MFPL_PB5MFP_EBI_ADR0          (0x02UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    444. 

  444. #define SYS_GPB_MFPL_PB5MFP_SD0_DAT3          (0x03UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< SD/SDIO 0 data line bit 3. \hideinitializer */
    445. 

  445. #define SYS_GPB_MFPL_PB5MFP_EMAC_RMII_REFCLK  (0x04UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< EMAC mode clock input. \hideinitializer */
    446. 

  446. #define SYS_GPB_MFPL_PB5MFP_SPI1_MISO         (0x05UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    447. 

  447. #define SYS_GPB_MFPL_PB5MFP_I2C0_SCL          (0x06UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
    448. 

  448. #define SYS_GPB_MFPL_PB5MFP_UART5_TXD         (0x07UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< Data transmitter output pin for UART5. \hideinitializer */
    449. 

  449. #define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0        (0x08UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< USCI1 control0 pin. \hideinitializer */
    450. 

  450. #define SYS_GPB_MFPL_PB5MFP_SC0_CLK           (0x09UL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< SmartCard0 clock pin. \hideinitializer */
    451. 

  451. #define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK         (0x0AUL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< I2S0 bit clock pin. \hideinitializer */
    452. 

  452. #define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0         (0x0BUL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
    453. 

  453. #define SYS_GPB_MFPL_PB5MFP_UART2_TXD         (0x0CUL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
    454. 

  454. #define SYS_GPB_MFPL_PB5MFP_TM0               (0x0EUL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< Timer0 event counter input / toggle output  \hideinitializer */
    455. 

  455. #define SYS_GPB_MFPL_PB5MFP_INT0              (0x0FUL<<SYS_GPB_MFPL_PB5MFP_Pos)  /*!< External interrupt0 input pin. \hideinitializer */
    456. 

  456. #define SYS_GPB_MFPL_PB6MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    457. 

  457. #define SYS_GPB_MFPL_PB6MFP_EADC0_CH6         (0x01UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EADC0 channel6 analog input. \hideinitializer */
    458. 

  458. #define SYS_GPB_MFPL_PB6MFP_EBI_nWRH          (0x02UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
    459. 

  459. #define SYS_GPB_MFPL_PB6MFP_EMAC_PPS          (0x03UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EMAC Pulse Per Second output  \hideinitializer */
    460. 

  460. #define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1        (0x04UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< USCI1 data1 pin. \hideinitializer */
    461. 

  461. #define SYS_GPB_MFPL_PB6MFP_CAN1_RXD          (0x05UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
    462. 

  462. #define SYS_GPB_MFPL_PB6MFP_UART1_RXD         (0x06UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
    463. 

  463. #define SYS_GPB_MFPL_PB6MFP_SD1_CLK           (0x07UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< SD/SDIO 1 clock. \hideinitializer */
    464. 

  464. #define SYS_GPB_MFPL_PB6MFP_EBI_nCS1          (0x08UL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
    465. 

  465. #define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5         (0x0AUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< BPWM1 channel5 output/capture input. \hideinitializer */
    466. 

  466. #define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1      (0x0BUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< Brake input pin 1 of EPWM1. \hideinitializer */
    467. 

  467. #define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5         (0x0CUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< EPWM1 channel5 output/capture input. \hideinitializer */
    468. 

  468. #define SYS_GPB_MFPL_PB6MFP_INT4              (0x0DUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< External interrupt4 input pin. \hideinitializer */
    469. 

  469. #define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN       (0x0EUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
    470. 

  470. #define SYS_GPB_MFPL_PB6MFP_ACMP1_O           (0x0FUL<<SYS_GPB_MFPL_PB6MFP_Pos)  /*!< Analog comparator1 output. \hideinitializer */
    471. 

  471. #define SYS_GPB_MFPL_PB7MFP_GPIO              (0x00UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    472. 

  472. #define SYS_GPB_MFPL_PB7MFP_EADC0_CH7         (0x01UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< EADC0 channel7 analog input. \hideinitializer */
    473. 

  473. #define SYS_GPB_MFPL_PB7MFP_EBI_nWRL          (0x02UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
    474. 

  474. #define SYS_GPB_MFPL_PB7MFP_EMAC_RMII_TXEN    (0x03UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< RMII Transmit Enable. \hideinitializer */
    475. 

  475. #define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0        (0x04UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< USCI1 data0 pin. \hideinitializer */
    476. 

  476. #define SYS_GPB_MFPL_PB7MFP_CAN1_TXD          (0x05UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< CAN1 bus transmitter output. \hideinitializer */
    477. 

  477. #define SYS_GPB_MFPL_PB7MFP_UART1_TXD         (0x06UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
    478. 

  478. #define SYS_GPB_MFPL_PB7MFP_SD1_CMD           (0x07UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< SD/SDIO 1 command/response. \hideinitializer */
    479. 

  479. #define SYS_GPB_MFPL_PB7MFP_EBI_nCS0          (0x08UL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
    480. 

  480. #define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4         (0x0AUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< BPWM1 channel4 output/capture input. \hideinitializer */
    481. 

  481. #define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0      (0x0BUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< Brake input pin 0 of EPWM1. \hideinitializer */
    482. 

  482. #define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4         (0x0CUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< EPWM1 channel4 output/capture input. \hideinitializer */
    483. 

  483. #define SYS_GPB_MFPL_PB7MFP_INT5              (0x0DUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< External interrupt5 input pin. \hideinitializer */
    484. 

  484. #define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST       (0x0EUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
    485. 

  485. #define SYS_GPB_MFPL_PB7MFP_ACMP0_O           (0x0FUL<<SYS_GPB_MFPL_PB7MFP_Pos)  /*!< Analog comparator0 output. \hideinitializer */
    486. 

  486. /********************* Bit definition of GPB_MFPH register **********************/
    487. 

  487. #define SYS_GPB_MFPH_PB8MFP_GPIO              (0x00UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    488. 

  488. #define SYS_GPB_MFPH_PB8MFP_EADC0_CH8         (0x01UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< EADC0 channel8 analog input. \hideinitializer */
    489. 

  489. #define SYS_GPB_MFPH_PB8MFP_EBI_ADR19         (0x02UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    490. 

  490. #define SYS_GPB_MFPH_PB8MFP_EMAC_RMII_TXD1    (0x03UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< RMII Transmit Data bus bit 1. \hideinitializer */
    491. 

  491. #define SYS_GPB_MFPH_PB8MFP_USCI1_CLK         (0x04UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< USCI1 clock pin. \hideinitializer */
    492. 

  492. #define SYS_GPB_MFPH_PB8MFP_UART0_RXD         (0x05UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
    493. 

  493. #define SYS_GPB_MFPH_PB8MFP_UART1_nRTS        (0x06UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< Request to Send output pin for UART1. \hideinitializer */
    494. 

  494. #define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS       (0x07UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin) \hideinitializer */
    495. 

  495. #define SYS_GPB_MFPH_PB8MFP_UART7_RXD         (0x08UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< Data receiver input pin for UART7.  \hideinitializer */
    496. 

  496. #define SYS_GPB_MFPH_PB8MFP_I2C0_SDA          (0x09UL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< I2C0 data input/output pin.  \hideinitializer */
    497. 

  497. #define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3         (0x0AUL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< BPWM1 channel3 output/capture input. \hideinitializer */
    498. 

  498. #define SYS_GPB_MFPH_PB8MFP_SPI3_MOSI         (0x0BUL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
    499. 

  499. #define SYS_GPB_MFPH_PB8MFP_CAN2_RXD          (0x0CUL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< CAN2 bus receiver input. \hideinitializer */
    500. 

  500. #define SYS_GPB_MFPH_PB8MFP_INT6              (0x0DUL<<SYS_GPB_MFPH_PB8MFP_Pos)  /*!< External interrupt6 input pin. \hideinitializer */
    501. 

  501. #define SYS_GPB_MFPH_PB9MFP_GPIO              (0x00UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    502. 

  502. #define SYS_GPB_MFPH_PB9MFP_EADC0_CH9         (0x01UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< EADC0 channel9 analog input. \hideinitializer */
    503. 

  503. #define SYS_GPB_MFPH_PB9MFP_EBI_ADR18         (0x02UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    504. 

  504. #define SYS_GPB_MFPH_PB9MFP_EMAC_RMII_TXD0    (0x03UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< RMII Transmit Data bus bit 0. \hideinitializer */
    505. 

  505. #define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1        (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< USCI1 control1 pin. \hideinitializer */
    506. 

  506. #define SYS_GPB_MFPH_PB9MFP_UART0_TXD         (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
    507. 

  507. #define SYS_GPB_MFPH_PB9MFP_UART1_nCTS        (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< Clear to Send input pin for UART1. \hideinitializer */
    508. 

  508. #define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL        (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< I2C1 SMBus SMBALTER# pin  \hideinitializer */
    509. 

  509. #define SYS_GPB_MFPH_PB9MFP_UART7_TXD         (0x08UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< Data transmitter output pin for UART7. \hideinitializer */
    510. 

  510. #define SYS_GPB_MFPH_PB9MFP_I2C0_SCL          (0x09UL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
    511. 

  511. #define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2         (0x0AUL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< BPWM1 channel2 output/capture input. \hideinitializer */
    512. 

  512. #define SYS_GPB_MFPH_PB9MFP_SPI3_MISO         (0x0BUL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
    513. 

  513. #define SYS_GPB_MFPH_PB9MFP_CAN2_TXD          (0x0CUL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< CAN2 bus transmitter output. \hideinitializer */
    514. 

  514. #define SYS_GPB_MFPH_PB9MFP_INT7              (0x0DUL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< External interrupt7 input pin. \hideinitializer */
    515. 

  515. #define SYS_GPB_MFPH_PB9MFP_CCAP_HSYNC        (0x0EUL<<SYS_GPB_MFPH_PB9MFP_Pos)  /*!< Sensor horizontal synchronization input pin. \hideinitializer */
    516. 

  516. #define SYS_GPB_MFPH_PB10MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    517. 

  517. #define SYS_GPB_MFPH_PB10MFP_EADC0_CH10       (0x01UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
    518. 

  518. #define SYS_GPB_MFPH_PB10MFP_EBI_ADR17        (0x02UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    519. 

  519. #define SYS_GPB_MFPH_PB10MFP_EMAC_RMII_MDIO   (0x03UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< RMII Management Data I/O. \hideinitializer */
    520. 

  520. #define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0       (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< USCI1 control0 pin. \hideinitializer */
    521. 

  521. #define SYS_GPB_MFPH_PB10MFP_UART0_nRTS       (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
    522. 

  522. #define SYS_GPB_MFPH_PB10MFP_UART4_RXD        (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
    523. 

  523. #define SYS_GPB_MFPH_PB10MFP_I2C1_SDA         (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< I2C1 data input/output pin. \hideinitializer */
    524. 

  524. #define SYS_GPB_MFPH_PB10MFP_CAN0_RXD         (0x08UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
    525. 

  525. #define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1        (0x0AUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< BPWM1 channel1 output/capture input. \hideinitializer */
    526. 

  526. #define SYS_GPB_MFPH_PB10MFP_SPI3_SS          (0x0BUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< 1st SPI3 slave select pin. \hideinitializer */
    527. 

  527. #define SYS_GPB_MFPH_PB10MFP_CCAP_VSYNC       (0x0CUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Sensor vertical synchronization input pin. \hideinitializer */
    528. 

  528. #define SYS_GPB_MFPH_PB10MFP_HSUSB_VBUS_EN    (0x0EUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
    529. 

  529. #define SYS_GPB_MFPH_PB11MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    530. 

  530. #define SYS_GPB_MFPH_PB11MFP_EADC0_CH11       (0x01UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
    531. 

  531. #define SYS_GPB_MFPH_PB11MFP_EBI_ADR16        (0x02UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    532. 

  532. #define SYS_GPB_MFPH_PB11MFP_EMAC_RMII_MDC    (0x03UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< RMII Management Data Clock. \hideinitializer */
    533. 

  533. #define SYS_GPB_MFPH_PB11MFP_UART0_nCTS       (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
    534. 

  534. #define SYS_GPB_MFPH_PB11MFP_UART4_TXD        (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
    535. 

  535. #define SYS_GPB_MFPH_PB11MFP_I2C1_SCL         (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< I2C1 clock pin. \hideinitializer */
    536. 

  536. #define SYS_GPB_MFPH_PB11MFP_CAN0_TXD         (0x08UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
    537. 

  537. #define SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK     (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
    538. 

  538. #define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0        (0x0AUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< BPWM1 channel0 output/capture input. \hideinitializer */
    539. 

  539. #define SYS_GPB_MFPH_PB11MFP_SPI3_CLK         (0x0BUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
    540. 

  540. #define SYS_GPB_MFPH_PB11MFP_CCAP_SFIELD      (0x0CUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Even/Odd Field Flag input pin. \hideinitializer */
    541. 

  541. #define SYS_GPB_MFPH_PB11MFP_HSUSB_VBUS_ST    (0x0EUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
    542. 

  542. #define SYS_GPB_MFPH_PB12MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    543. 

  543. #define SYS_GPB_MFPH_PB12MFP_ACMP0_P2         (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
    544. 

  544. #define SYS_GPB_MFPH_PB12MFP_ACMP1_P2         (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
    545. 

  545. #define SYS_GPB_MFPH_PB12MFP_DAC0_OUT         (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< DAC0 channel analog output. \hideinitializer */
    546. 

  546. #define SYS_GPB_MFPH_PB12MFP_EADC0_CH12       (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
    547. 

  547. #define SYS_GPB_MFPH_PB12MFP_EADC1_CH12       (0x01UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
    548. 

  548. #define SYS_GPB_MFPH_PB12MFP_EBI_AD15         (0x02UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
    549. 

  549. #define SYS_GPB_MFPH_PB12MFP_SC1_CLK          (0x03UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SmartCard1 clock pin. \hideinitializer */
    550. 

  550. #define SYS_GPB_MFPH_PB12MFP_SPI0_MOSI        (0x04UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    551. 

  551. #define SYS_GPB_MFPH_PB12MFP_USCI0_CLK        (0x05UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< USCI0 clock pin. \hideinitializer */
    552. 

  552. #define SYS_GPB_MFPH_PB12MFP_UART0_RXD        (0x06UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
    553. 

  553. #define SYS_GPB_MFPH_PB12MFP_UART3_nCTS       (0x07UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Clear to Send input pin for UART3. \hideinitializer */
    554. 

  554. #define SYS_GPB_MFPH_PB12MFP_I2C2_SDA         (0x08UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< I2C2 data input/output pin. \hideinitializer */
    555. 

  555. #define SYS_GPB_MFPH_PB12MFP_SD0_nCD          (0x09UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< SD/SDIO 0 card detect. \hideinitializer */
    556. 

  556. #define SYS_GPB_MFPH_PB12MFP_CCAP_SCLK        (0x0AUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Sensor pixel clock(to sensor) output pin. \hideinitializer */
    557. 

  557. #define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3        (0x0BUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< EPWM1 channel3 output/capture input. \hideinitializer */
    558. 

  558. #define SYS_GPB_MFPH_PB12MFP_ETM_TRACE_DATA3  (0x0CUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< ETM Rx input bus bit3. \hideinitializer */
    559. 

  559. #define SYS_GPB_MFPH_PB12MFP_TM3_EXT          (0x0DUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< Timer3 event counter input / toggle output  \hideinitializer */
    560. 

  560. #define SYS_GPB_MFPH_PB13MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    561. 

  561. #define SYS_GPB_MFPH_PB13MFP_ACMP0_P3         (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator0 positive input pin. \hideinitializer */
    562. 

  562. #define SYS_GPB_MFPH_PB13MFP_ACMP1_P3         (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Analog comparator1 positive input pin. \hideinitializer */
    563. 

  563. #define SYS_GPB_MFPH_PB13MFP_DAC1_OUT         (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< DAC1 channel analog output. \hideinitializer */
    564. 

  564. #define SYS_GPB_MFPH_PB13MFP_EADC0_CH13       (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
    565. 

  565. #define SYS_GPB_MFPH_PB13MFP_EADC1_CH13       (0x01UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
    566. 

  566. #define SYS_GPB_MFPH_PB13MFP_EBI_AD14         (0x02UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
    567. 

  567. #define SYS_GPB_MFPH_PB13MFP_SC1_DAT          (0x03UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< SmartCard1 data pin. \hideinitializer */
    568. 

  568. #define SYS_GPB_MFPH_PB13MFP_SPI0_MISO        (0x04UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    569. 

  569. #define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0       (0x05UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< USCI0 data0 pin. \hideinitializer */
    570. 

  570. #define SYS_GPB_MFPH_PB13MFP_UART0_TXD        (0x06UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
    571. 

  571. #define SYS_GPB_MFPH_PB13MFP_UART3_nRTS       (0x07UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Request to Send output pin for UART3. \hideinitializer */
    572. 

  572. #define SYS_GPB_MFPH_PB13MFP_I2C2_SCL         (0x08UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
    573. 

  573. #define SYS_GPB_MFPH_PB13MFP_CCAP_PIXCLK      (0x0AUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Sensor pixel clock(from sensor) input pin. \hideinitializer */
    574. 

  574. #define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2        (0x0BUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
    575. 

  575. #define SYS_GPB_MFPH_PB13MFP_ETM_TRACE_DATA2  (0x0CUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< ETM Rx input bus bit2. \hideinitializer */
    576. 

  576. #define SYS_GPB_MFPH_PB13MFP_TM2_EXT          (0x0DUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< Timer2 event counter input / toggle output  \hideinitializer */
    577. 

  577. #define SYS_GPB_MFPH_PB14MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    578. 

  578. #define SYS_GPB_MFPH_PB14MFP_EADC0_CH14       (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
    579. 

  579. #define SYS_GPB_MFPH_PB14MFP_EADC1_CH14       (0x01UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
    580. 

  580. #define SYS_GPB_MFPH_PB14MFP_EBI_AD13         (0x02UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
    581. 

  581. #define SYS_GPB_MFPH_PB14MFP_SC1_RST          (0x03UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SmartCard1 reset pin. \hideinitializer */
    582. 

  582. #define SYS_GPB_MFPH_PB14MFP_SPI0_CLK         (0x04UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< SPI0 serial clock pin. \hideinitializer */
    583. 

  583. #define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1       (0x05UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< USCI0 data1 pin. \hideinitializer */
    584. 

  584. #define SYS_GPB_MFPH_PB14MFP_UART0_nRTS       (0x06UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Request to Send output pin for UART0. \hideinitializer */
    585. 

  585. #define SYS_GPB_MFPH_PB14MFP_UART3_RXD        (0x07UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
    586. 

  586. #define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS      (0x08UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< I2C2 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
    587. 

  587. #define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1        (0x0BUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
    588. 

  588. #define SYS_GPB_MFPH_PB14MFP_ETM_TRACE_DATA1  (0x0CUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */
    589. 

  589. #define SYS_GPB_MFPH_PB14MFP_TM1_EXT          (0x0DUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Timer1 event counter input / toggle output  \hideinitializer */
    590. 

  590. #define SYS_GPB_MFPH_PB14MFP_CLKO             (0x0EUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Clock Output pin. \hideinitializer */
    591. 

  591. #define SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST      (0x0FUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< Power supply from USB Full speed host or HUB. */
    592. 

  592. #define SYS_GPB_MFPH_PB15MFP_GPIO             (0x00UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    593. 

  593. #define SYS_GPB_MFPH_PB15MFP_EADC0_CH15       (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EADC0 channel1 analog input. \hideinitializer */
    594. 

  594. #define SYS_GPB_MFPH_PB15MFP_EADC1_CH15       (0x01UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
    595. 

  595. #define SYS_GPB_MFPH_PB15MFP_EBI_AD12         (0x02UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
    596. 

  596. #define SYS_GPB_MFPH_PB15MFP_SC1_PWR          (0x03UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< SmartCard1 power pin. \hideinitializer */
    597. 

  597. #define SYS_GPB_MFPH_PB15MFP_SPI0_SS          (0x04UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< 1st SPI0 slave select pin. \hideinitializer */
    598. 

  598. #define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1       (0x05UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< USCI0 control1 pin. \hideinitializer */
    599. 

  599. #define SYS_GPB_MFPH_PB15MFP_UART0_nCTS       (0x06UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Clear to Send input pin for UART0. \hideinitializer */
    600. 

  600. #define SYS_GPB_MFPH_PB15MFP_UART3_TXD        (0x07UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
    601. 

  601. #define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL       (0x08UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< I2C2 SMBus SMBALTER# pin.  \hideinitializer */
    602. 

  602. #define SYS_GPB_MFPH_PB15MFP_EPWM0_BRAKE1     (0x0AUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Brake input pin 1 of EPWM0. \hideinitializer */
    603. 

  603. #define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0        (0x0BUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
    604. 

  604. #define SYS_GPB_MFPH_PB15MFP_ETM_TRACE_DATA0  (0x0CUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< ETM Rx input bus bit0. \hideinitializer */
    605. 

  605. #define SYS_GPB_MFPH_PB15MFP_TM0_EXT          (0x0DUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Timer0 event counter input / toggle output  \hideinitializer */
    606. 

  606. #define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN      (0x0EUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
    607. 

  607. #define SYS_GPB_MFPH_PB15MFP_HSUSB_VBUS_EN    (0x0FUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
    608. 

  608. /********************* Bit definition of GPC_MFPL register **********************/
    609. 

  609. #define SYS_GPC_MFPL_PC0MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    610. 

  610. #define SYS_GPC_MFPL_PC0MFP_EBI_AD0           (0x02UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< EBI address/data bus bit0. \hideinitializer */
    611. 

  611. #define SYS_GPC_MFPL_PC0MFP_SPIM_MOSI         (0x03UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
    612. 

  612. #define SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0       (0x04UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< 1st QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    613. 

  613. #define SYS_GPC_MFPL_PC0MFP_SC1_CLK           (0x05UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< SmartCard1 clock pin. \hideinitializer */
    614. 

  614. #define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK         (0x06UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< I2S0 left right channel clock. \hideinitializer */
    615. 

  615. #define SYS_GPC_MFPL_PC0MFP_SPI1_SS           (0x07UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< 1st SPI1 slave select pin. \hideinitializer */
    616. 

  616. #define SYS_GPC_MFPL_PC0MFP_UART2_RXD         (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
    617. 

  617. #define SYS_GPC_MFPL_PC0MFP_I2C0_SDA          (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
    618. 

  618. #define SYS_GPC_MFPL_PC0MFP_CAN2_RXD          (0x0AUL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< CAN2 bus receiver input. \hideinitializer */
    619. 

  619. #define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5         (0x0CUL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< EPWM1 channel5 output/capture input. \hideinitializer */
    620. 

  620. #define SYS_GPC_MFPL_PC0MFP_CCAP_DATA0        (0x0DUL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< Sensor pixel data0 input pin. \hideinitializer */
    621. 

  621. #define SYS_GPC_MFPL_PC0MFP_ACMP1_O           (0x0EUL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< Analog comparator1 output. \hideinitializer */
    622. 

  622. #define SYS_GPC_MFPL_PC0MFP_EADC1_ST          (0x0FUL<<SYS_GPC_MFPL_PC0MFP_Pos)  /*!< EADC external trigger input. \hideinitializer */
    623. 

  623. #define SYS_GPC_MFPL_PC1MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    624. 

  624. #define SYS_GPC_MFPL_PC1MFP_EBI_AD1           (0x02UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
    625. 

  625. #define SYS_GPC_MFPL_PC1MFP_SPIM_MISO         (0x03UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
    626. 

  626. #define SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0       (0x04UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< 1st QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    627. 

  627. #define SYS_GPC_MFPL_PC1MFP_SC1_DAT           (0x05UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< SmartCard1 data pin. \hideinitializer */
    628. 

  628. #define SYS_GPC_MFPL_PC1MFP_I2S0_DO           (0x06UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< I2S0 data output. \hideinitializer */
    629. 

  629. #define SYS_GPC_MFPL_PC1MFP_SPI1_CLK          (0x07UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< SPI1 serial clock pin. \hideinitializer */
    630. 

  630. #define SYS_GPC_MFPL_PC1MFP_UART2_TXD         (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
    631. 

  631. #define SYS_GPC_MFPL_PC1MFP_I2C0_SCL          (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
    632. 

  632. #define SYS_GPC_MFPL_PC1MFP_CAN2_TXD          (0x0AUL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< CAN2 bus transmitter output. \hideinitializer */
    633. 

  633. #define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4         (0x0CUL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< EPWM1 channel4 output/capture input. \hideinitializer */
    634. 

  634. #define SYS_GPC_MFPL_PC1MFP_CCAP_DATA1        (0x0DUL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< Sensor pixel data1 input pin. \hideinitializer */
    635. 

  635. #define SYS_GPC_MFPL_PC1MFP_ACMP0_O           (0x0EUL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< Analog comparator0 output. \hideinitializer */
    636. 

  636. #define SYS_GPC_MFPL_PC1MFP_EADC0_ST          (0x0FUL<<SYS_GPC_MFPL_PC1MFP_Pos)  /*!< EADC external trigger input. \hideinitializer */
    637. 

  637. #define SYS_GPC_MFPL_PC2MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    638. 

  638. #define SYS_GPC_MFPL_PC2MFP_EBI_AD2           (0x02UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< EBI address/data bus bit2. \hideinitializer */
    639. 

  639. #define SYS_GPC_MFPL_PC2MFP_SPIM_CLK          (0x03UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< SPIM serial clock pin. \hideinitializer */
    640. 

  640. #define SYS_GPC_MFPL_PC2MFP_QSPI0_CLK         (0x04UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< QSPI0 serial clock pin. \hideinitializer */
    641. 

  641. #define SYS_GPC_MFPL_PC2MFP_SC1_RST           (0x05UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< SmartCard1 reset pin. \hideinitializer */
    642. 

  642. #define SYS_GPC_MFPL_PC2MFP_I2S0_DI           (0x06UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< I2S0 data input. \hideinitializer */
    643. 

  643. #define SYS_GPC_MFPL_PC2MFP_SPI1_MOSI         (0x07UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    644. 

  644. #define SYS_GPC_MFPL_PC2MFP_UART2_nCTS        (0x08UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< Clear to Send input pin for UART2. \hideinitializer */
    645. 

  645. #define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS       (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
    646. 

  646. #define SYS_GPC_MFPL_PC2MFP_CAN1_RXD          (0x0AUL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
    647. 

  647. #define SYS_GPC_MFPL_PC2MFP_UART3_RXD         (0x0BUL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< Data receiver input pin for UART3. \hideinitializer */
    648. 

  648. #define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3         (0x0CUL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< EPWM1 channel3 output/capture input. \hideinitializer */
    649. 

  649. #define SYS_GPC_MFPL_PC2MFP_CCAP_DATA2        (0x0DUL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< Sensor pixel data2 input pin. \hideinitializer */
    650. 

  650. #define SYS_GPC_MFPL_PC2MFP_QSPI1_MOSI0       (0x0EUL<<SYS_GPC_MFPL_PC2MFP_Pos)  /*!< 1st QSPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    651. 

  651. #define SYS_GPC_MFPL_PC3MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    652. 

  652. #define SYS_GPC_MFPL_PC3MFP_EBI_AD3           (0x02UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< EBI address/data bus bit3. \hideinitializer */
    653. 

  653. #define SYS_GPC_MFPL_PC3MFP_SPIM_SS           (0x03UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< 1st SPIM slave select pin. \hideinitializer */
    654. 

  654. #define SYS_GPC_MFPL_PC3MFP_QSPI0_SS          (0x04UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< 1st QSPI0 slave select pin. \hideinitializer */
    655. 

  655. #define SYS_GPC_MFPL_PC3MFP_SC1_PWR           (0x05UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< SmartCard1 power pin. \hideinitializer */
    656. 

  656. #define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK         (0x06UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
    657. 

  657. #define SYS_GPC_MFPL_PC3MFP_SPI1_MISO         (0x07UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    658. 

  658. #define SYS_GPC_MFPL_PC3MFP_UART2_nRTS        (0x08UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< Request to Send output pin for UART2. \hideinitializer */
    659. 

  659. #define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL        (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< I2C0 SMBus SMBALTER# pin  \hideinitializer  */
    660. 

  660. #define SYS_GPC_MFPL_PC3MFP_CAN1_TXD          (0x0AUL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< CAN1 bus transmitter output. \hideinitializer */
    661. 

  661. #define SYS_GPC_MFPL_PC3MFP_UART3_TXD         (0x0BUL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< Data transmitter output pin for UART3. \hideinitializer */
    662. 

  662. #define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2         (0x0CUL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< EPWM1 channel2 output/capture input. \hideinitializer */
    663. 

  663. #define SYS_GPC_MFPL_PC3MFP_CCAP_DATA3        (0x0DUL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< Sensor pixel data3 input pin. \hideinitializer */
    664. 

  664. #define SYS_GPC_MFPL_PC3MFP_QSPI1_MISO0       (0x0EUL<<SYS_GPC_MFPL_PC3MFP_Pos)  /*!< 1st QSPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    665. 

  665. #define SYS_GPC_MFPL_PC4MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    666. 

  666. #define SYS_GPC_MFPL_PC4MFP_EBI_AD4           (0x02UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< EBI address/data bus bit4. \hideinitializer */
    667. 

  667. #define SYS_GPC_MFPL_PC4MFP_SPIM_D3           (0x03UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
    668. 

  668. #define SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1       (0x04UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< 2nd QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    669. 

  669. #define SYS_GPC_MFPL_PC4MFP_SC1_nCD           (0x05UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< SmartCard1 card detect pin. \hideinitializer */
    670. 

  670. #define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK         (0x06UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< I2S0 bit clock pin. \hideinitializer */
    671. 

  671. #define SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK      (0x07UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< SPI1 I2S master clock output pin. \hideinitializer */
    672. 

  672. #define SYS_GPC_MFPL_PC4MFP_UART2_RXD         (0x08UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
    673. 

  673. #define SYS_GPC_MFPL_PC4MFP_I2C1_SDA          (0x09UL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
    674. 

  674. #define SYS_GPC_MFPL_PC4MFP_CAN0_RXD          (0x0AUL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< CAN0 bus receiver input. \hideinitializer */
    675. 

  675. #define SYS_GPC_MFPL_PC4MFP_UART4_RXD         (0x0BUL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
    676. 

  676. #define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1         (0x0CUL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< EPWM1 channel1 output/capture input. \hideinitializer */
    677. 

  677. #define SYS_GPC_MFPL_PC4MFP_CCAP_DATA4        (0x0DUL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< Sensor pixel data4 input pin. \hideinitializer */
    678. 

  678. #define SYS_GPC_MFPL_PC4MFP_QSPI1_CLK         (0x0EUL<<SYS_GPC_MFPL_PC4MFP_Pos)  /*!< QSPI1 serial clock pin. \hideinitializer */
    679. 

  679. #define SYS_GPC_MFPL_PC5MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    680. 

  680. #define SYS_GPC_MFPL_PC5MFP_EBI_AD5           (0x02UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< EBI address/data bus bit5. \hideinitializer */
    681. 

  681. #define SYS_GPC_MFPL_PC5MFP_SPIM_D2           (0x03UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
    682. 

  682. #define SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1       (0x04UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< 2nd QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    683. 

  683. #define SYS_GPC_MFPL_PC5MFP_UART2_TXD         (0x08UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
    684. 

  684. #define SYS_GPC_MFPL_PC5MFP_I2C1_SCL          (0x09UL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
    685. 

  685. #define SYS_GPC_MFPL_PC5MFP_CAN0_TXD          (0x0AUL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< CAN0 bus transmitter output. \hideinitializer */
    686. 

  686. #define SYS_GPC_MFPL_PC5MFP_UART4_TXD         (0x0BUL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
    687. 

  687. #define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0         (0x0CUL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< EPWM1 channel0 output/capture input. \hideinitializer */
    688. 

  688. #define SYS_GPC_MFPL_PC5MFP_CCAP_DATA5        (0x0DUL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< Sensor pixel data5 input pin. \hideinitializer */
    689. 

  689. #define SYS_GPC_MFPL_PC5MFP_QSPI1_SS          (0x0EUL<<SYS_GPC_MFPL_PC5MFP_Pos)  /*!< 1st QSPI1 slave select pin. \hideinitializer */
    690. 

  690. #define SYS_GPC_MFPL_PC6MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    691. 

  691. #define SYS_GPC_MFPL_PC6MFP_EBI_AD8           (0x02UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< EBI address/data bus bit8. \hideinitializer */
    692. 

  692. #define SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1    (0x03UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< RMII Receive Data bus bit 1. \hideinitializer */
    693. 

  693. #define SYS_GPC_MFPL_PC6MFP_SPI1_MOSI         (0x04UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    694. 

  694. #define SYS_GPC_MFPL_PC6MFP_UART4_RXD         (0x05UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
    695. 

  695. #define SYS_GPC_MFPL_PC6MFP_SC2_RST           (0x06UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< SmartCard2 reset pin. \hideinitializer */
    696. 

  696. #define SYS_GPC_MFPL_PC6MFP_UART0_nRTS        (0x07UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< Request to Send output pin for UART0. \hideinitializer */
    697. 

  697. #define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS       (0x08UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
    698. 

  698. #define SYS_GPC_MFPL_PC6MFP_UART6_RXD         (0x09UL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< Data receiver input pin for UART6.  \hideinitializer */
    699. 

  699. #define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3         (0x0BUL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< EPWM1 channel3 output/capture input. \hideinitializer */
    700. 

  700. #define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1         (0x0CUL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< BPWM1 channel1 output/capture input. \hideinitializer */
    701. 

  701. #define SYS_GPC_MFPL_PC6MFP_TM1               (0x0EUL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< Timer1 event counter input / toggle output  \hideinitializer */
    702. 

  702. #define SYS_GPC_MFPL_PC6MFP_INT2              (0x0FUL<<SYS_GPC_MFPL_PC6MFP_Pos)  /*!< External interrupt2 input pin. \hideinitializer */
    703. 

  703. #define SYS_GPC_MFPL_PC7MFP_GPIO              (0x00UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    704. 

  704. #define SYS_GPC_MFPL_PC7MFP_EBI_AD9           (0x02UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< EBI address/data bus bit9. \hideinitializer */
    705. 

  705. #define SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0    (0x03UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< RMII Receive Data bus bit 0. \hideinitializer */
    706. 

  706. #define SYS_GPC_MFPL_PC7MFP_SPI1_MISO         (0x04UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    707. 

  707. #define SYS_GPC_MFPL_PC7MFP_UART4_TXD         (0x05UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
    708. 

  708. #define SYS_GPC_MFPL_PC7MFP_SC2_PWR           (0x06UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< SmartCard2 power pin. \hideinitializer */
    709. 

  709. #define SYS_GPC_MFPL_PC7MFP_UART0_nCTS        (0x07UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< Clear to Send input pin for UART0. \hideinitializer */
    710. 

  710. #define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL        (0x08UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< I2C1 SMBus SMBALTER# pin  \hideinitializer */
    711. 

  711. #define SYS_GPC_MFPL_PC7MFP_UART6_TXD         (0x09UL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< Data transmitter output pin for UART6. \hideinitializer */
    712. 

  712. #define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2         (0x0BUL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< EPWM1 channel2 output/capture input. \hideinitializer */
    713. 

  713. #define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0         (0x0CUL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< BPWM1 channel0 output/capture input. \hideinitializer */
    714. 

  714. #define SYS_GPC_MFPL_PC7MFP_TM0               (0x0EUL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< Timer0 event counter input / toggle output  \hideinitializer */
    715. 

  715. #define SYS_GPC_MFPL_PC7MFP_INT3              (0x0FUL<<SYS_GPC_MFPL_PC7MFP_Pos)  /*!< External interrupt3 input pin. \hideinitializer */
    716. 

  716. /********************* Bit definition of GPC_MFPH register **********************/
    717. 

  717. #define SYS_GPC_MFPH_PC8MFP_GPIO              (0x00UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    718. 

  718. #define SYS_GPC_MFPH_PC8MFP_EBI_ADR16         (0x02UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    719. 

  719. #define SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK  (0x03UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< EMAC mode clock input. \hideinitializer */
    720. 

  720. #define SYS_GPC_MFPH_PC8MFP_I2C0_SDA          (0x04UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
    721. 

  721. #define SYS_GPC_MFPH_PC8MFP_UART4_nCTS        (0x05UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< Clear to Send input pin for UART4. \hideinitializer */
    722. 

  722. #define SYS_GPC_MFPH_PC8MFP_UART1_RXD         (0x08UL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
    723. 

  723. #define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1         (0x0BUL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< EPWM1 channel1 output/capture input. \hideinitializer */
    724. 

  724. #define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4         (0x0CUL<<SYS_GPC_MFPH_PC8MFP_Pos)  /*!< BPWM1 channel4 output/capture input. \hideinitializer */
    725. 

  725. #define SYS_GPC_MFPH_PC9MFP_GPIO              (0x00UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    726. 

  726. #define SYS_GPC_MFPH_PC9MFP_EBI_ADR7          (0x02UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    727. 

  727. #define SYS_GPC_MFPH_PC9MFP_UART6_nCTS        (0x05UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< Clear to Send input pin for UART6. \hideinitializer */
    728. 

  728. #define SYS_GPC_MFPH_PC9MFP_SPI3_SS           (0x06UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< 1st SPI3 slave select pin. \hideinitializer */
    729. 

  729. #define SYS_GPC_MFPH_PC9MFP_UART3_RXD         (0x07UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< Data receiver input pin for UART3. \hideinitializer */
    730. 

  730. #define SYS_GPC_MFPH_PC9MFP_CAN1_RXD          (0x09UL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
    731. 

  731. #define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3         (0x0CUL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< EPWM1 channel3 output/capture input. \hideinitializer */
    732. 

  732. #define SYS_GPC_MFPH_PC9MFP_EADC1_ST          (0x0EUL<<SYS_GPC_MFPH_PC9MFP_Pos)  /*!< EADC external trigger input. \hideinitializer */
    733. 

  733. #define SYS_GPC_MFPH_PC10MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    734. 

  734. #define SYS_GPC_MFPH_PC10MFP_EBI_ADR6         (0x02UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    735. 

  735. #define SYS_GPC_MFPH_PC10MFP_UART6_nRTS       (0x05UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Request to Send output pin for UART6. \hideinitializer */
    736. 

  736. #define SYS_GPC_MFPH_PC10MFP_SPI3_CLK         (0x06UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< SPI3 serial clock pin. \hideinitializer */
    737. 

  737. #define SYS_GPC_MFPH_PC10MFP_UART3_TXD        (0x07UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
    738. 

  738. #define SYS_GPC_MFPH_PC10MFP_CAN1_TXD         (0x09UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
    739. 

  739. #define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0        (0x0BUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */
    740. 

  740. #define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2        (0x0CUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EPWM1 channel2 output/capture input. \hideinitializer */
    741. 

  741. #define SYS_GPC_MFPH_PC10MFP_EADC1_ST         (0x0EUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
    742. 

  742. #define SYS_GPC_MFPH_PC11MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    743. 

  743. #define SYS_GPC_MFPH_PC11MFP_EBI_ADR5         (0x02UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    744. 

  744. #define SYS_GPC_MFPH_PC11MFP_UART0_RXD        (0x03UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
    745. 

  745. #define SYS_GPC_MFPH_PC11MFP_I2C0_SDA         (0x04UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< I2C0 data input/output pin. \hideinitializer */
    746. 

  746. #define SYS_GPC_MFPH_PC11MFP_UART6_RXD        (0x05UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
    747. 

  747. #define SYS_GPC_MFPH_PC11MFP_SPI3_MOSI        (0x06UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
    748. 

  748. #define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1        (0x0BUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */
    749. 

  749. #define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1        (0x0CUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< EPWM1 channel1 output/capture input. \hideinitializer */
    750. 

  750. #define SYS_GPC_MFPH_PC11MFP_ACMP1_O          (0x0EUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< Analog comparator1 output. \hideinitializer */
    751. 

  751. #define SYS_GPC_MFPH_PC12MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    752. 

  752. #define SYS_GPC_MFPH_PC12MFP_EBI_ADR4         (0x02UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    753. 

  753. #define SYS_GPC_MFPH_PC12MFP_UART0_TXD        (0x03UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
    754. 

  754. #define SYS_GPC_MFPH_PC12MFP_I2C0_SCL         (0x04UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
    755. 

  755. #define SYS_GPC_MFPH_PC12MFP_UART6_TXD        (0x05UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Data transmitter output pin for UART6. \hideinitializer */
    756. 

  756. #define SYS_GPC_MFPH_PC12MFP_SPI3_MISO        (0x06UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
    757. 

  757. #define SYS_GPC_MFPH_PC12MFP_SC0_nCD          (0x09UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
    758. 

  758. #define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2        (0x0BUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */
    759. 

  759. #define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0        (0x0CUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
    760. 

  760. #define SYS_GPC_MFPH_PC12MFP_ACMP0_O          (0x0EUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< Analog comparator0 output. \hideinitializer */
    761. 

  761. #define SYS_GPC_MFPH_PC13MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    762. 

  762. #define SYS_GPC_MFPH_PC13MFP_EADC1_CH3        (0x01UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EADC1 channel3 analog input. \hideinitializer */
    763. 

  763. #define SYS_GPC_MFPH_PC13MFP_EBI_ADR10        (0x02UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    764. 

  764. #define SYS_GPC_MFPH_PC13MFP_SC2_nCD          (0x03UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
    765. 

  765. #define SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK     (0x04UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
    766. 

  766. #define SYS_GPC_MFPH_PC13MFP_CAN1_TXD         (0x05UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< CAN1 bus transmitter output. \hideinitializer */
    767. 

  767. #define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0       (0x06UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
    768. 

  768. #define SYS_GPC_MFPH_PC13MFP_UART2_TXD        (0x07UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
    769. 

  769. #define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4        (0x09UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
    770. 

  770. #define SYS_GPC_MFPH_PC13MFP_CLKO             (0x0DUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< Clock Output pin. \hideinitializer */
    771. 

  771. #define SYS_GPC_MFPH_PC13MFP_EADC0_ST         (0x0EUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
    772. 

  772. #define SYS_GPC_MFPH_PC14MFP_GPIO             (0x00UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    773. 

  773. #define SYS_GPC_MFPH_PC14MFP_EBI_AD11         (0x02UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
    774. 

  774. #define SYS_GPC_MFPH_PC14MFP_SC1_nCD          (0x03UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
    775. 

  775. #define SYS_GPC_MFPH_PC14MFP_SPI0_I2SMCLK     (0x04UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
    776. 

  776. #define SYS_GPC_MFPH_PC14MFP_USCI0_CTL0       (0x05UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< USCI0 control0 pin. \hideinitializer */
    777. 

  777. #define SYS_GPC_MFPH_PC14MFP_QSPI0_CLK        (0x06UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< QSPI0 serial clock pin. \hideinitializer */
    778. 

  778. #define SYS_GPC_MFPH_PC14MFP_EPWM0_SYNC_IN    (0x0BUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< EPWM0 counter synchronous trigger input pin. \hideinitializer */
    779. 

  779. #define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_CLK    (0x0CUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< ETM Rx clock input pin. \hideinitializer */
    780. 

  780. #define SYS_GPC_MFPH_PC14MFP_TM1              (0x0DUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Timer1 event counter input / toggle output  \hideinitializer */
    781. 

  781. #define SYS_GPC_MFPH_PC14MFP_USB_VBUS_ST      (0x0EUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
    782. 

  782. #define SYS_GPC_MFPH_PC14MFP_HSUSB_VBUS_ST    (0x0FUL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< Power supply from USB High speed host or HUB. \hideinitializer */
    783. 

  783. /********************* Bit definition of GPD_MFPL register **********************/
    784. 

  784. #define SYS_GPD_MFPL_PD0MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    785. 

  785. #define SYS_GPD_MFPL_PD0MFP_EBI_AD13          (0x02UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
    786. 

  786. #define SYS_GPD_MFPL_PD0MFP_USCI0_CLK         (0x03UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< USCI0 clock pin. \hideinitializer */
    787. 

  787. #define SYS_GPD_MFPL_PD0MFP_SPI0_MOSI         (0x04UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    788. 

  788. #define SYS_GPD_MFPL_PD0MFP_UART3_RXD         (0x05UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< Data receiver input pin for UART3. \hideinitializer */
    789. 

  789. #define SYS_GPD_MFPL_PD0MFP_I2C2_SDA          (0x06UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< I2C2 data input/output pin. \hideinitializer */
    790. 

  790. #define SYS_GPD_MFPL_PD0MFP_SC2_CLK           (0x07UL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< SmartCard2 clock pin. \hideinitializer */
    791. 

  791. #define SYS_GPD_MFPL_PD0MFP_TM2               (0x0EUL<<SYS_GPD_MFPL_PD0MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
    792. 

  792. #define SYS_GPD_MFPL_PD1MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    793. 

  793. #define SYS_GPD_MFPL_PD1MFP_EBI_AD12          (0x02UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
    794. 

  794. #define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0        (0x03UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< USCI0 data0 pin. \hideinitializer */
    795. 

  795. #define SYS_GPD_MFPL_PD1MFP_SPI0_MISO         (0x04UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    796. 

  796. #define SYS_GPD_MFPL_PD1MFP_UART3_TXD         (0x05UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< Data transmitter output pin for UART3. \hideinitializer */
    797. 

  797. #define SYS_GPD_MFPL_PD1MFP_I2C2_SCL          (0x06UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< I2C2 clock pin. \hideinitializer */
    798. 

  798. #define SYS_GPD_MFPL_PD1MFP_SC2_DAT           (0x07UL<<SYS_GPD_MFPL_PD1MFP_Pos)  /*!< SmartCard2 data pin. \hideinitializer */
    799. 

  799. #define SYS_GPD_MFPL_PD2MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    800. 

  800. #define SYS_GPD_MFPL_PD2MFP_EBI_AD11          (0x02UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
    801. 

  801. #define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1        (0x03UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< USCI0 data1 pin. \hideinitializer */
    802. 

  802. #define SYS_GPD_MFPL_PD2MFP_SPI0_CLK          (0x04UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< SPI0 serial clock pin. \hideinitializer */
    803. 

  803. #define SYS_GPD_MFPL_PD2MFP_UART3_nCTS        (0x05UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< Clear to Send input pin for UART3. \hideinitializer */
    804. 

  804. #define SYS_GPD_MFPL_PD2MFP_SC2_RST           (0x07UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< SmartCard2 reset pin. \hideinitializer */
    805. 

  805. #define SYS_GPD_MFPL_PD2MFP_UART0_RXD         (0x09UL<<SYS_GPD_MFPL_PD2MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
    806. 

  806. #define SYS_GPD_MFPL_PD3MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    807. 

  807. #define SYS_GPD_MFPL_PD3MFP_EBI_AD10          (0x02UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
    808. 

  808. #define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1        (0x03UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< USCI0 control1 pin. \hideinitializer */
    809. 

  809. #define SYS_GPD_MFPL_PD3MFP_SPI0_SS           (0x04UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< 1st SPI0 slave select pin. \hideinitializer */
    810. 

  810. #define SYS_GPD_MFPL_PD3MFP_UART3_nRTS        (0x05UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< Request to Send output pin for UART3. \hideinitializer */
    811. 

  811. #define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0        (0x06UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< USCI1 control0 pin. \hideinitializer */
    812. 

  812. #define SYS_GPD_MFPL_PD3MFP_SC2_PWR           (0x07UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< SmartCard2 power pin. \hideinitializer */
    813. 

  813. #define SYS_GPD_MFPL_PD3MFP_SC1_nCD           (0x08UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< SmartCard1 card detect pin. \hideinitializer */
    814. 

  814. #define SYS_GPD_MFPL_PD3MFP_UART0_TXD         (0x09UL<<SYS_GPD_MFPL_PD3MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
    815. 

  815. #define SYS_GPD_MFPL_PD4MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    816. 

  816. #define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0        (0x03UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< USCI0 control0 pin. \hideinitializer */
    817. 

  817. #define SYS_GPD_MFPL_PD4MFP_I2C1_SDA          (0x04UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
    818. 

  818. #define SYS_GPD_MFPL_PD4MFP_SPI1_SS           (0x05UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< 1st SPI1 slave select pin. \hideinitializer */
    819. 

  819. #define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1        (0x06UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< USCI1 control1 pin. \hideinitializer */
    820. 

  820. #define SYS_GPD_MFPL_PD4MFP_SC1_CLK           (0x08UL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< SmartCard1 clock pin. \hideinitializer */
    821. 

  821. #define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST       (0x0EUL<<SYS_GPD_MFPL_PD4MFP_Pos)  /*!< Power supply from USB Full speed host or HUB. \hideinitializer */
    822. 

  822. #define SYS_GPD_MFPL_PD5MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    823. 

  823. #define SYS_GPD_MFPL_PD5MFP_I2C1_SCL          (0x04UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
    824. 

  824. #define SYS_GPD_MFPL_PD5MFP_SPI1_CLK          (0x05UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< SPI1 serial clock pin. \hideinitializer */
    825. 

  825. #define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0        (0x06UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< USCI1 data0 pin. \hideinitializer */
    826. 

  826. #define SYS_GPD_MFPL_PD5MFP_SC1_DAT           (0x08UL<<SYS_GPD_MFPL_PD5MFP_Pos)  /*!< SmartCard1 data pin. \hideinitializer */
    827. 

  827. #define SYS_GPD_MFPL_PD6MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    828. 

  828. #define SYS_GPD_MFPL_PD6MFP_UART1_RXD         (0x03UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
    829. 

  829. #define SYS_GPD_MFPL_PD6MFP_I2C0_SDA          (0x04UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
    830. 

  830. #define SYS_GPD_MFPL_PD6MFP_SPI1_MOSI         (0x05UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    831. 

  831. #define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1        (0x06UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< USCI1 data1 pin. \hideinitializer */
    832. 

  832. #define SYS_GPD_MFPL_PD6MFP_SC1_RST           (0x08UL<<SYS_GPD_MFPL_PD6MFP_Pos)  /*!< SmartCard1 reset pin. \hideinitializer */
    833. 

  833. #define SYS_GPD_MFPL_PD7MFP_GPIO              (0x00UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    834. 

  834. #define SYS_GPD_MFPL_PD7MFP_UART1_TXD         (0x03UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
    835. 

  835. #define SYS_GPD_MFPL_PD7MFP_I2C0_SCL          (0x04UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
    836. 

  836. #define SYS_GPD_MFPL_PD7MFP_SPI1_MISO         (0x05UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    837. 

  837. #define SYS_GPD_MFPL_PD7MFP_USCI1_CLK         (0x06UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< USCI1 clock pin. \hideinitializer */
    838. 

  838. #define SYS_GPD_MFPL_PD7MFP_SC1_PWR           (0x08UL<<SYS_GPD_MFPL_PD7MFP_Pos)  /*!< SmartCard1 power pin. \hideinitializer */
    839. 

  839. /********************* Bit definition of GPD_MFPH register **********************/
    840. 

  840. #define SYS_GPD_MFPH_PD8MFP_GPIO              (0x00UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    841. 

  841. #define SYS_GPD_MFPH_PD8MFP_EBI_AD6           (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< EBI address/data bus bit6. \hideinitializer */
    842. 

  842. #define SYS_GPD_MFPH_PD8MFP_I2C2_SDA          (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< I2C2 data input/output pin. \hideinitializer */
    843. 

  843. #define SYS_GPD_MFPH_PD8MFP_UART2_nRTS        (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< Request to Send output pin for UART2. \hideinitializer */
    844. 

  844. #define SYS_GPD_MFPH_PD8MFP_UART7_RXD         (0x05UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< Data receiver input pin for UART7. \hideinitializer */
    845. 

  845. #define SYS_GPD_MFPH_PD8MFP_CAN2_RXD          (0x06UL<<SYS_GPD_MFPH_PD8MFP_Pos)  /*!< CAN2 bus receiver input. \hideinitializer */
    846. 

  846. #define SYS_GPD_MFPH_PD9MFP_GPIO              (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    847. 

  847. #define SYS_GPD_MFPH_PD9MFP_EBI_AD7           (0x02UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< EBI address/data bus bit7. \hideinitializer */
    848. 

  848. #define SYS_GPD_MFPH_PD9MFP_I2C2_SCL          (0x03UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< I2C2 clock pin. \hideinitializer */
    849. 

  849. #define SYS_GPD_MFPH_PD9MFP_UART2_nCTS        (0x04UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< Clear to Send input pin for UART2. \hideinitializer */
    850. 

  850. #define SYS_GPD_MFPH_PD9MFP_UART7_TXD         (0x05UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< Data transmitter output pin for UART7. \hideinitializer */
    851. 

  851. #define SYS_GPD_MFPH_PD9MFP_CAN2_TXD          (0x06UL<<SYS_GPD_MFPH_PD9MFP_Pos)  /*!< CAN2 bus transmitter output. \hideinitializer */
    852. 

  852. #define SYS_GPD_MFPH_PD10MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    853. 

  853. #define SYS_GPD_MFPH_PD10MFP_OPA2_P           (0x01UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Operational amplifier positive input pin. \hideinitializer */
    854. 

  854. #define SYS_GPD_MFPH_PD10MFP_EADC1_CH0        (0x01UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< EADC1 channel0 analog input. \hideinitializer */
    855. 

  855. #define SYS_GPD_MFPH_PD10MFP_EBI_nCS2         (0x02UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
    856. 

  856. #define SYS_GPD_MFPH_PD10MFP_UART1_RXD        (0x03UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Data receiver input pin for UART1. \hideinitializer */
    857. 

  857. #define SYS_GPD_MFPH_PD10MFP_CAN0_RXD         (0x04UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
    858. 

  858. #define SYS_GPD_MFPH_PD10MFP_QEI0_B           (0x0AUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
    859. 

  859. #define SYS_GPD_MFPH_PD10MFP_INT7             (0x0FUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< External interrupt7 input pin. \hideinitializer */
    860. 

  860. #define SYS_GPD_MFPH_PD11MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    861. 

  861. #define SYS_GPD_MFPH_PD11MFP_EADC1_CH1        (0x01UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< EADC1 channel1 analog input. \hideinitializer */
    862. 

  862. #define SYS_GPD_MFPH_PD11MFP_OPA2_N           (0x01UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Operational amplifier negative input pin. \hideinitializer */
    863. 

  863. #define SYS_GPD_MFPH_PD11MFP_EBI_nCS1         (0x02UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
    864. 

  864. #define SYS_GPD_MFPH_PD11MFP_UART1_TXD        (0x03UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
    865. 

  865. #define SYS_GPD_MFPH_PD11MFP_CAN0_TXD         (0x04UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
    866. 

  866. #define SYS_GPD_MFPH_PD11MFP_QEI0_A           (0x0AUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
    867. 

  867. #define SYS_GPD_MFPH_PD11MFP_INT6             (0x0FUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< External interrupt6 input pin. \hideinitializer */
    868. 

  868. #define SYS_GPD_MFPH_PD12MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    869. 

  869. #define SYS_GPD_MFPH_PD12MFP_OPA2_O           (0x01UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Operational amplifier output pin. \hideinitializer */
    870. 

  870. #define SYS_GPD_MFPH_PD12MFP_EADC1_CH2        (0x01UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EADC1 channel2 analog input. \hideinitializer */
    871. 

  871. #define SYS_GPD_MFPH_PD12MFP_EBI_nCS0         (0x02UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
    872. 

  872. #define SYS_GPD_MFPH_PD12MFP_CAN1_RXD         (0x05UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< CAN1 bus receiver input. \hideinitializer */
    873. 

  873. #define SYS_GPD_MFPH_PD12MFP_UART2_RXD        (0x07UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
    874. 

  874. #define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5        (0x09UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< BPWM0 channel5 output/capture input. \hideinitializer */
    875. 

  875. #define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX       (0x0AUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
    876. 

  876. #define SYS_GPD_MFPH_PD12MFP_CLKO             (0x0DUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< Clock Output pin. \hideinitializer */
    877. 

  877. #define SYS_GPD_MFPH_PD12MFP_EADC0_ST         (0x0EUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
    878. 

  878. #define SYS_GPD_MFPH_PD12MFP_INT5             (0x0FUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< External interrupt5 input pin. \hideinitializer */
    879. 

  879. #define SYS_GPD_MFPH_PD13MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    880. 

  880. #define SYS_GPD_MFPH_PD13MFP_EBI_AD10         (0x02UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
    881. 

  881. #define SYS_GPD_MFPH_PD13MFP_SD0_nCD          (0x03UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SD/SDIO 0 card detect  \hideinitializer */
    882. 

  882. #define SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK     (0x04UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
    883. 

  883. #define SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK     (0x05UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
    884. 

  884. #define SYS_GPD_MFPH_PD13MFP_SC2_nCD          (0x07UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
    885. 

  885. #define SYS_GPD_MFPH_PD14MFP_GPIO             (0x00UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    886. 

  886. #define SYS_GPD_MFPH_PD14MFP_EBI_nCS0         (0x02UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EBI chip select enable output pin. \hideinitializer */
    887. 

  887. #define SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK     (0x03UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SPI3 I2S master clock output pin. \hideinitializer */
    888. 

  888. #define SYS_GPD_MFPH_PD14MFP_SC1_nCD          (0x04UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SmartCard1 card detect pin. \hideinitializer */
    889. 

  889. #define SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK     (0x05UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
    890. 

  890. #define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4        (0x0BUL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
    891. 

  891. /********************* Bit definition of GPE_MFPL register **********************/
    892. 

  892. #define SYS_GPE_MFPL_PE0MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    893. 

  893. #define SYS_GPE_MFPL_PE0MFP_EBI_AD11          (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
    894. 

  894. #define SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0       (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< 1st QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    895. 

  895. #define SYS_GPE_MFPL_PE0MFP_SC2_CLK           (0x04UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< SmartCard2 clock pin. \hideinitializer */
    896. 

  896. #define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK         (0x05UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
    897. 

  897. #define SYS_GPE_MFPL_PE0MFP_SPI1_MOSI         (0x06UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    898. 

  898. #define SYS_GPE_MFPL_PE0MFP_UART3_RXD         (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< Data receiver input pin for UART3. \hideinitializer */
    899. 

  899. #define SYS_GPE_MFPL_PE0MFP_I2C1_SDA          (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
    900. 

  900. #define SYS_GPE_MFPL_PE0MFP_UART4_nRTS        (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos)  /*!< Request to Send output pin for UART4. \hideinitializer */
    901. 

  901. #define SYS_GPE_MFPL_PE1MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    902. 

  902. #define SYS_GPE_MFPL_PE1MFP_EBI_AD10          (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
    903. 

  903. #define SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0       (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< 1st QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    904. 

  904. #define SYS_GPE_MFPL_PE1MFP_SC2_DAT           (0x04UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< SmartCard2 data pin. \hideinitializer */
    905. 

  905. #define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK         (0x05UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< I2S0 bit clock pin. \hideinitializer */
    906. 

  906. #define SYS_GPE_MFPL_PE1MFP_SPI1_MISO         (0x06UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    907. 

  907. #define SYS_GPE_MFPL_PE1MFP_UART3_TXD         (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< Data transmitter output pin for UART3. \hideinitializer */
    908. 

  908. #define SYS_GPE_MFPL_PE1MFP_I2C1_SCL          (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
    909. 

  909. #define SYS_GPE_MFPL_PE1MFP_UART4_nCTS        (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos)  /*!< Clear to Send input pin for UART4. \hideinitializer */
    910. 

  910. #define SYS_GPE_MFPL_PE2MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    911. 

  911. #define SYS_GPE_MFPL_PE2MFP_EBI_ALE           (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< EBI address latch enable output pin. \hideinitializer */
    912. 

  912. #define SYS_GPE_MFPL_PE2MFP_SD0_DAT0          (0x03UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< SD/SDIO 0 data line bit 0. \hideinitializer */
    913. 

  913. #define SYS_GPE_MFPL_PE2MFP_SPIM_MOSI         (0x04UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
    914. 

  914. #define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI         (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
    915. 

  915. #define SYS_GPE_MFPL_PE2MFP_SC0_CLK           (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< SmartCard0 clock pin. \hideinitializer */
    916. 

  916. #define SYS_GPE_MFPL_PE2MFP_USCI0_CLK         (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< USCI0 clock pin. \hideinitializer */
    917. 

  917. #define SYS_GPE_MFPL_PE2MFP_UART6_nCTS        (0x08UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< Clear to Send input pin for UART6. \hideinitializer */
    918. 

  918. #define SYS_GPE_MFPL_PE2MFP_UART7_RXD         (0x09UL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< Data receiver input pin for UART7. \hideinitializer */
    919. 

  919. #define SYS_GPE_MFPL_PE2MFP_QEI0_B            (0x0BUL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< Quadrature encoder phase B input of QEI Unit 0. \hideinitializer */
    920. 

  920. #define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5         (0x0CUL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< EPWM0 channel5 output/capture input. \hideinitializer */
    921. 

  921. #define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0         (0x0DUL<<SYS_GPE_MFPL_PE2MFP_Pos)  /*!< BPWM0 channel0 output/capture input. \hideinitializer */
    922. 

  922. #define SYS_GPE_MFPL_PE3MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    923. 

  923. #define SYS_GPE_MFPL_PE3MFP_EBI_MCLK          (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< EBI external clock output pin. \hideinitializer */
    924. 

  924. #define SYS_GPE_MFPL_PE3MFP_SD0_DAT1          (0x03UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< SD/SDIO 0 data line bit 1. \hideinitializer */
    925. 

  925. #define SYS_GPE_MFPL_PE3MFP_SPIM_MISO         (0x04UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
    926. 

  926. #define SYS_GPE_MFPL_PE3MFP_SPI3_MISO         (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
    927. 

  927. #define SYS_GPE_MFPL_PE3MFP_SC0_DAT           (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< SmartCard0 data pin. \hideinitializer */
    928. 

  928. #define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0        (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< USCI0 data0 pin. \hideinitializer */
    929. 

  929. #define SYS_GPE_MFPL_PE3MFP_UART6_nRTS        (0x08UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< Request to Send output pin for UART6. \hideinitializer */
    930. 

  930. #define SYS_GPE_MFPL_PE3MFP_UART7_TXD         (0x09UL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< Data transmitter output pin for UART7. \hideinitializer */
    931. 

  931. #define SYS_GPE_MFPL_PE3MFP_QEI0_A            (0x0BUL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< Quadrature encoder phase A input of QEI Unit 0. \hideinitializer */
    932. 

  932. #define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4         (0x0CUL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< EPWM0 channel4 output/capture input. \hideinitializer */
    933. 

  933. #define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1         (0x0DUL<<SYS_GPE_MFPL_PE3MFP_Pos)  /*!< BPWM0 channel1 output/capture input. \hideinitializer */
    934. 

  934. #define SYS_GPE_MFPL_PE4MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    935. 

  935. #define SYS_GPE_MFPL_PE4MFP_EBI_nWR           (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
    936. 

  936. #define SYS_GPE_MFPL_PE4MFP_SD0_DAT2          (0x03UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< SD/SDIO 0 data line bit 2. \hideinitializer */
    937. 

  937. #define SYS_GPE_MFPL_PE4MFP_SPIM_CLK          (0x04UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< SPIM serial clock pin. \hideinitializer */
    938. 

  938. #define SYS_GPE_MFPL_PE4MFP_SPI3_CLK          (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< SPI3 serial clock pin. \hideinitializer */
    939. 

  939. #define SYS_GPE_MFPL_PE4MFP_SC0_RST           (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< SmartCard0 reset pin. \hideinitializer */
    940. 

  940. #define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1        (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< USCI0 data1 pin. \hideinitializer */
    941. 

  941. #define SYS_GPE_MFPL_PE4MFP_UART6_RXD         (0x08UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< Data receiver input pin for UART6. \hideinitializer */
    942. 

  942. #define SYS_GPE_MFPL_PE4MFP_UART7_nCTS        (0x09UL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< Clear to Send input pin for UART7. \hideinitializer */
    943. 

  943. #define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX        (0x0BUL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< Quadrature encoder index input of QEI Unit 0. \hideinitializer */
    944. 

  944. #define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3         (0x0CUL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< EPWM0 channel3 output/capture input. \hideinitializer */
    945. 

  945. #define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2         (0x0DUL<<SYS_GPE_MFPL_PE4MFP_Pos)  /*!< BPWM0 channel2 output/capture input. \hideinitializer */
    946. 

  946. #define SYS_GPE_MFPL_PE5MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    947. 

  947. #define SYS_GPE_MFPL_PE5MFP_EBI_nRD           (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< EBI read enable output pin. \hideinitializer */
    948. 

  948. #define SYS_GPE_MFPL_PE5MFP_SD0_DAT3          (0x03UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< SD/SDIO 0 data line bit 3. \hideinitializer */
    949. 

  949. #define SYS_GPE_MFPL_PE5MFP_SPIM_SS           (0x04UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< 1st SPIM slave select pin. \hideinitializer */
    950. 

  950. #define SYS_GPE_MFPL_PE5MFP_SPI3_SS           (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< 1st SPI3 slave select pin. \hideinitializer */
    951. 

  951. #define SYS_GPE_MFPL_PE5MFP_SC0_PWR           (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< SmartCard0 power pin. \hideinitializer */
    952. 

  952. #define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1        (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< USCI0 control1 pin. \hideinitializer */
    953. 

  953. #define SYS_GPE_MFPL_PE5MFP_UART6_TXD         (0x08UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< Data transmitter output pin for UART6. \hideinitializer */
    954. 

  954. #define SYS_GPE_MFPL_PE5MFP_UART7_nRTS        (0x09UL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< Request to Send output pin for UART7. \hideinitializer */
    955. 

  955. #define SYS_GPE_MFPL_PE5MFP_QEI1_B            (0x0BUL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< Quadrature encoder phase B input of QEI Unit 1. \hideinitializer */
    956. 

  956. #define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2         (0x0CUL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< EPWM0 channel2 output/capture input. \hideinitializer */
    957. 

  957. #define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3         (0x0DUL<<SYS_GPE_MFPL_PE5MFP_Pos)  /*!< BPWM0 channel3 output/capture input. \hideinitializer */
    958. 

  958. #define SYS_GPE_MFPL_PE6MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    959. 

  959. #define SYS_GPE_MFPL_PE6MFP_SD0_CLK           (0x03UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< SD/SDIO 0 clock. \hideinitializer */
    960. 

  960. #define SYS_GPE_MFPL_PE6MFP_SPIM_D3           (0x04UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
    961. 

  961. #define SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK      (0x05UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< SPI3 I2S master clock output pin. \hideinitializer */
    962. 

  962. #define SYS_GPE_MFPL_PE6MFP_SC0_nCD           (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< SmartCard0 card detect pin. \hideinitializer */
    963. 

  963. #define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0        (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< USCI0 control0 pin. \hideinitializer */
    964. 

  964. #define SYS_GPE_MFPL_PE6MFP_UART5_RXD         (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< Data receiver input pin for UART5. \hideinitializer */
    965. 

  965. #define SYS_GPE_MFPL_PE6MFP_CAN1_RXD          (0x09UL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
    966. 

  966. #define SYS_GPE_MFPL_PE6MFP_QEI1_A            (0x0BUL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< Quadrature encoder phase A input of QEI Unit 1. \hideinitializer */
    967. 

  967. #define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1         (0x0CUL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
    968. 

  968. #define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4         (0x0DUL<<SYS_GPE_MFPL_PE6MFP_Pos)  /*!< BPWM0 channel4 output/capture input. \hideinitializer */
    969. 

  969. #define SYS_GPE_MFPL_PE7MFP_GPIO              (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    970. 

  970. #define SYS_GPE_MFPL_PE7MFP_SD0_CMD           (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< SD/SDIO 0 command/response. \hideinitializer */
    971. 

  971. #define SYS_GPE_MFPL_PE7MFP_SPIM_D2           (0x04UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
    972. 

  972. #define SYS_GPE_MFPL_PE7MFP_UART5_TXD         (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< Data transmitter output pin for UART5. \hideinitializer */
    973. 

  973. #define SYS_GPE_MFPL_PE7MFP_CAN1_TXD          (0x09UL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< CAN1 bus transmitter output. \hideinitializer */
    974. 

  974. #define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX        (0x0BUL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< Quadrature encoder index input of QEI Unit 1. \hideinitializer */
    975. 

  975. #define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0         (0x0CUL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
    976. 

  976. #define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5         (0x0DUL<<SYS_GPE_MFPL_PE7MFP_Pos)  /*!< BPWM0 channel5 output/capture input. \hideinitializer */
    977. 

  977. /********************* Bit definition of GPE_MFPH register **********************/
    978. 

  978. #define SYS_GPE_MFPH_PE8MFP_GPIO              (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    979. 

  979. #define SYS_GPE_MFPH_PE8MFP_EBI_ADR10         (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    980. 

  980. #define SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC      (0x03UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< RMII Management Data Clock. \hideinitializer */
    981. 

  981. #define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK         (0x04UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< I2S0 bit clock pin. \hideinitializer */
    982. 

  982. #define SYS_GPE_MFPH_PE8MFP_SPI2_CLK          (0x05UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< SPI2 serial clock pin. \hideinitializer */
    983. 

  983. #define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1        (0x06UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< USCI1 control1 pin. \hideinitializer */
    984. 

  984. #define SYS_GPE_MFPH_PE8MFP_UART2_TXD         (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
    985. 

  985. #define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0         (0x0AUL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
    986. 

  986. #define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0      (0x0BUL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< Brake input pin 0 of EPWM0. \hideinitializer */
    987. 

  987. #define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0         (0x0CUL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< Input 0 of enhanced capture unit 0. \hideinitializer */
    988. 

  988. #define SYS_GPE_MFPH_PE8MFP_TRACE_DATA3       (0x0EUL<<SYS_GPE_MFPH_PE8MFP_Pos)  /*!< ETM Rx input bus bit3. \hideinitializer */
    989. 

  989. #define SYS_GPE_MFPH_PE9MFP_GPIO              (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    990. 

  990. #define SYS_GPE_MFPH_PE9MFP_EBI_ADR11         (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    991. 

  991. #define SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO    (0x03UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< RMII Management Data I/O. \hideinitializer */
    992. 

  992. #define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK         (0x04UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
    993. 

  993. #define SYS_GPE_MFPH_PE9MFP_SPI2_MISO         (0x05UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
    994. 

  994. #define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0        (0x06UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< USCI1 control0 pin. \hideinitializer */
    995. 

  995. #define SYS_GPE_MFPH_PE9MFP_UART2_RXD         (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
    996. 

  996. #define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1         (0x0AUL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
    997. 

  997. #define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1      (0x0BUL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< Brake input pin 1 of EPWM0. \hideinitializer */
    998. 

  998. #define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1         (0x0CUL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< Input 1 of enhanced capture unit 0. \hideinitializer */
    999. 

  999. #define SYS_GPE_MFPH_PE9MFP_TRACE_DATA2       (0x0EUL<<SYS_GPE_MFPH_PE9MFP_Pos)  /*!< ETM Rx input bus bit2. \hideinitializer */
    1000. 

  1000. #define SYS_GPE_MFPH_PE10MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1001. 

  1001. #define SYS_GPE_MFPH_PE10MFP_EBI_ADR12        (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    1002. 

  1002. #define SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0   (0x03UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< RMII Transmit Data bus bit 0. \hideinitializer */
    1003. 

  1003. #define SYS_GPE_MFPH_PE10MFP_I2S0_DI          (0x04UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< I2S0 data input. \hideinitializer */
    1004. 

  1004. #define SYS_GPE_MFPH_PE10MFP_SPI2_MOSI        (0x05UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
    1005. 

  1005. #define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0       (0x06UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< USCI1 data0 pin. \hideinitializer */
    1006. 

  1006. #define SYS_GPE_MFPH_PE10MFP_UART3_TXD        (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Data transmitter output pin for UART3. \hideinitializer */
    1007. 

  1007. #define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2        (0x0AUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< EPWM0 channel2 output/capture input. \hideinitializer */
    1008. 

  1008. #define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0     (0x0BUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Brake input pin 0 of EPWM1. \hideinitializer */
    1009. 

  1009. #define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2        (0x0CUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Input 0 of enhanced capture unit 2. \hideinitializer */
    1010. 

  1010. #define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1      (0x0EUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< ETM Rx input bus bit1. \hideinitializer */
    1011. 

  1011. #define SYS_GPE_MFPH_PE11MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1012. 

  1012. #define SYS_GPE_MFPH_PE11MFP_EBI_ADR13        (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    1013. 

  1013. #define SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1   (0x03UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< RMII Transmit Data bus bit 1. \hideinitializer */
    1014. 

  1014. #define SYS_GPE_MFPH_PE11MFP_I2S0_DO          (0x04UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< I2S0 data output. \hideinitializer */
    1015. 

  1015. #define SYS_GPE_MFPH_PE11MFP_SPI2_SS          (0x05UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< 1st SPI2 slave select pin. \hideinitializer */
    1016. 

  1016. #define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1       (0x06UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< USCI1 data1 pin. \hideinitializer */
    1017. 

  1017. #define SYS_GPE_MFPH_PE11MFP_UART3_RXD        (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Data receiver input pin for UART3. \hideinitializer */
    1018. 

  1018. #define SYS_GPE_MFPH_PE11MFP_UART1_nCTS       (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Clear to Send input pin for UART1. \hideinitializer */
    1019. 

  1019. #define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3        (0x0AUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< EPWM0 channel3 output/capture input. \hideinitializer */
    1020. 

  1020. #define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1     (0x0BUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Brake input pin 1 of EPWM1. \hideinitializer */
    1021. 

  1021. #define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2        (0x0DUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Input 1 of enhanced capture unit 2. \hideinitializer */
    1022. 

  1022. #define SYS_GPE_MFPH_PE11MFP_TRACE_DATA0      (0x0EUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< ETM Rx input bus bit0. \hideinitializer */
    1023. 

  1023. #define SYS_GPE_MFPH_PE12MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1024. 

  1024. #define SYS_GPE_MFPH_PE12MFP_EBI_ADR14        (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    1025. 

  1025. #define SYS_GPE_MFPH_PE12MFP_EMAC_RMII_TXEN    (0x03UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< RMII? Transmit Enable. \hideinitializer */
    1026. 

  1026. #define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK        (0x04UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
    1027. 

  1027. #define SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK     (0x05UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< SPI2 I2S master clock output pin. \hideinitializer */
    1028. 

  1028. #define SYS_GPE_MFPH_PE12MFP_USCI1_CLK        (0x06UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< USCI1 clock pin. \hideinitializer */
    1029. 

  1029. #define SYS_GPE_MFPH_PE12MFP_UART1_nRTS       (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Request to Send output pin for UART1. \hideinitializer */
    1030. 

  1030. #define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4        (0x0AUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< EPWM0 channel4 output/capture input. \hideinitializer */
    1031. 

  1031. #define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1        (0x0DUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Input 1 of enhanced capture unit 1. \hideinitializer */
    1032. 

  1032. #define SYS_GPE_MFPH_PE12MFP_TRACE_CLK        (0x0EUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< ETM Rx clock input pin. \hideinitializer */
    1033. 

  1033. #define SYS_GPE_MFPH_PE13MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1034. 

  1034. #define SYS_GPE_MFPH_PE13MFP_EBI_ADR15        (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    1035. 

  1035. #define SYS_GPE_MFPH_PE13MFP_EMAC_PPS         (0x03UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EMAC Pulse Per Second output  \hideinitializer */
    1036. 

  1036. #define SYS_GPE_MFPH_PE13MFP_I2C0_SCL         (0x04UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< I2C0 clock pin. \hideinitializer */
    1037. 

  1037. #define SYS_GPE_MFPH_PE13MFP_UART4_nRTS       (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Request to Send output pin for UART4. \hideinitializer */
    1038. 

  1038. #define SYS_GPE_MFPH_PE13MFP_UART1_TXD        (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Data transmitter output pin for UART1. \hideinitializer */
    1039. 

  1039. #define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5        (0x0AUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
    1040. 

  1040. #define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0        (0x0BUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< EPWM1 channel0 output/capture input. \hideinitializer */
    1041. 

  1041. #define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5        (0x0CUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< BPWM1 channel5 output/capture input. \hideinitializer */
    1042. 

  1042. #define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0        (0x0DUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Input 0 of enhanced capture unit 1. \hideinitializer */
    1043. 

  1043. #define SYS_GPE_MFPH_PE14MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1044. 

  1044. #define SYS_GPE_MFPH_PE14MFP_EBI_AD8          (0x02UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< EBI address/data bus bit8. \hideinitializer */
    1045. 

  1045. #define SYS_GPE_MFPH_PE14MFP_UART2_TXD        (0x03UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< Data transmitter output pin for UART2. \hideinitializer */
    1046. 

  1046. #define SYS_GPE_MFPH_PE14MFP_CAN0_TXD         (0x04UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< CAN0 bus transmitter output. \hideinitializer */
    1047. 

  1047. #define SYS_GPE_MFPH_PE14MFP_SD1_nCD          (0x05UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< SD/SDIO 1 card detect  \hideinitializer */
    1048. 

  1048. #define SYS_GPE_MFPH_PE14MFP_UART6_TXD        (0x06UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< Data transmitter output pin for UART6. */
    1049. 

  1049. #define SYS_GPE_MFPH_PE15MFP_GPIO             (0x00UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1050. 

  1050. #define SYS_GPE_MFPH_PE15MFP_EBI_AD9          (0x02UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< EBI address/data bus bit9. \hideinitializer */
    1051. 

  1051. #define SYS_GPE_MFPH_PE15MFP_UART2_RXD        (0x03UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< Data receiver input pin for UART2. \hideinitializer */
    1052. 

  1052. #define SYS_GPE_MFPH_PE15MFP_CAN0_RXD         (0x04UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< CAN0 bus receiver input. \hideinitializer */
    1053. 

  1053. #define SYS_GPE_MFPH_PE15MFP_UART6_RXD        (0x06UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
    1054. 

  1054. /********************* Bit definition of GPF_MFPL register **********************/
    1055. 

  1055. #define SYS_GPF_MFPL_PF0MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1056. 

  1056. #define SYS_GPF_MFPL_PF0MFP_UART1_TXD         (0x02UL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
    1057. 

  1057. #define SYS_GPF_MFPL_PF0MFP_I2C1_SCL          (0x03UL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
    1058. 

  1058. #define SYS_GPF_MFPL_PF0MFP_UART0_TXD         (0x04UL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
    1059. 

  1059. #define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0         (0x0CUL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< BPWM1 channel0 output/capture input. \hideinitializer */
    1060. 

  1060. #define SYS_GPF_MFPL_PF0MFP_ICE_DAT           (0x0EUL<<SYS_GPF_MFPL_PF0MFP_Pos)  /*!< Serial wired debugger data pin. \hideinitializer */
    1061. 

  1061. #define SYS_GPF_MFPL_PF1MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1062. 

  1062. #define SYS_GPF_MFPL_PF1MFP_UART1_RXD         (0x02UL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
    1063. 

  1063. #define SYS_GPF_MFPL_PF1MFP_I2C1_SDA          (0x03UL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
    1064. 

  1064. #define SYS_GPF_MFPL_PF1MFP_UART0_RXD         (0x04UL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
    1065. 

  1065. #define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1         (0x0CUL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< BPWM1 channel1 output/capture input. \hideinitializer */
    1066. 

  1066. #define SYS_GPF_MFPL_PF1MFP_ICE_CLK           (0x0EUL<<SYS_GPF_MFPL_PF1MFP_Pos)  /*!< Serial wired debugger clock pin. \hideinitializer */
    1067. 

  1067. #define SYS_GPF_MFPL_PF2MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1068. 

  1068. #define SYS_GPF_MFPL_PF2MFP_EBI_nCS1          (0x02UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
    1069. 

  1069. #define SYS_GPF_MFPL_PF2MFP_UART0_RXD         (0x03UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< Data receiver input pin for UART0. \hideinitializer */
    1070. 

  1070. #define SYS_GPF_MFPL_PF2MFP_I2C0_SDA          (0x04UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
    1071. 

  1071. #define SYS_GPF_MFPL_PF2MFP_QSPI0_CLK         (0x05UL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< QSPI0 serial clock pin. \hideinitializer */
    1072. 

  1072. #define SYS_GPF_MFPL_PF2MFP_XT1_OUT           (0x0AUL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< External 4~24 MHz (high speed) crystal output pin. \hideinitializer */
    1073. 

  1073. #define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1         (0x0BUL<<SYS_GPF_MFPL_PF2MFP_Pos)  /*!< BPWM1 channel1 output/capture input. \hideinitializer */
    1074. 

  1074. #define SYS_GPF_MFPL_PF3MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1075. 

  1075. #define SYS_GPF_MFPL_PF3MFP_EBI_nCS0          (0x02UL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
    1076. 

  1076. #define SYS_GPF_MFPL_PF3MFP_UART0_TXD         (0x03UL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< Data transmitter output pin for UART0. \hideinitializer */
    1077. 

  1077. #define SYS_GPF_MFPL_PF3MFP_I2C0_SCL          (0x04UL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
    1078. 

  1078. #define SYS_GPF_MFPL_PF3MFP_XT1_IN            (0x0AUL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< External 4~24 MHz (high speed) crystal input pin. \hideinitializer */
    1079. 

  1079. #define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0         (0x0BUL<<SYS_GPF_MFPL_PF3MFP_Pos)  /*!< BPWM1 channel0 output/capture input. \hideinitializer */
    1080. 

  1080. #define SYS_GPF_MFPL_PF4MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< General purpose digital I/O pin.  \hideinitializer */
    1081. 

  1081. #define SYS_GPF_MFPL_PF4MFP_UART2_TXD         (0x02UL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
    1082. 

  1082. #define SYS_GPF_MFPL_PF4MFP_UART2_nRTS        (0x04UL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< Request to Send output pin for UART2. \hideinitializer */
    1083. 

  1083. #define SYS_GPF_MFPL_PF4MFP_EPWM0_CH1         (0x07UL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
    1084. 

  1084. #define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5         (0x08UL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< BPWM0 channel5 output/capture input. \hideinitializer */
    1085. 

  1085. #define SYS_GPF_MFPL_PF4MFP_X32_OUT           (0x0AUL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< External 32.768 kHz (low speed) crystal output pin. \hideinitializer */
    1086. 

  1086. #define SYS_GPF_MFPL_PF4MFP_EADC1_ST          (0x0BUL<<SYS_GPF_MFPL_PF4MFP_Pos)  /*!< EADC external trigger input. \hideinitializer */
    1087. 

  1087. #define SYS_GPF_MFPL_PF5MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1088. 

  1088. #define SYS_GPF_MFPL_PF5MFP_UART2_RXD         (0x02UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
    1089. 

  1089. #define SYS_GPF_MFPL_PF5MFP_UART2_nCTS        (0x04UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< Clear to Send input pin for UART2. \hideinitializer */
    1090. 

  1090. #define SYS_GPF_MFPL_PF5MFP_EPWM0_CH0         (0x07UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
    1091. 

  1091. #define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4         (0x08UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< BPWM0 channel4 output/capture input. \hideinitializer */
    1092. 

  1092. #define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT    (0x09UL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */
    1093. 

  1093. #define SYS_GPF_MFPL_PF5MFP_X32_IN            (0x0AUL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< External 32.768 kHz (low speed) crystal input pin. \hideinitializer */
    1094. 

  1094. #define SYS_GPF_MFPL_PF5MFP_EADC0_ST          (0x0BUL<<SYS_GPF_MFPL_PF5MFP_Pos)  /*!< EADC external trigger input. \hideinitializer */
    1095. 

  1095. #define SYS_GPF_MFPL_PF6MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1096. 

  1096. #define SYS_GPF_MFPL_PF6MFP_EBI_ADR19         (0x02UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1097. 

  1097. #define SYS_GPF_MFPL_PF6MFP_SC0_CLK           (0x03UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< SmartCard0 clock pin. \hideinitializer */
    1098. 

  1098. #define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK         (0x04UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< I2S0 left right channel clock. \hideinitializer */
    1099. 

  1099. #define SYS_GPF_MFPL_PF6MFP_SPI0_MOSI         (0x05UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    1100. 

  1100. #define SYS_GPF_MFPL_PF6MFP_UART4_RXD         (0x06UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
    1101. 

  1101. #define SYS_GPF_MFPL_PF6MFP_EBI_nCS0          (0x07UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
    1102. 

  1102. #define SYS_GPF_MFPL_PF6MFP_CAN2_RXD          (0x08UL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< CAN2 bus receiver input. \hideinitializer */
    1103. 

  1103. #define SYS_GPF_MFPL_PF6MFP_TAMPER0           (0x0AUL<<SYS_GPF_MFPL_PF6MFP_Pos)  /*!< TAMPER detector loop pin0. \hideinitializer */
    1104. 

  1104. #define SYS_GPF_MFPL_PF7MFP_GPIO              (0x00UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1105. 

  1105. #define SYS_GPF_MFPL_PF7MFP_EBI_ADR18         (0x02UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1106. 

  1106. #define SYS_GPF_MFPL_PF7MFP_SC0_DAT           (0x03UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< SmartCard0 data pin. \hideinitializer */
    1107. 

  1107. #define SYS_GPF_MFPL_PF7MFP_I2S0_DO           (0x04UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< I2S0 data output. \hideinitializer */
    1108. 

  1108. #define SYS_GPF_MFPL_PF7MFP_SPI0_MISO         (0x05UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< 1st SPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    1109. 

  1109. #define SYS_GPF_MFPL_PF7MFP_UART4_TXD         (0x06UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
    1110. 

  1110. #define SYS_GPF_MFPL_PF7MFP_CCAP_DATA0        (0x07UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< Sensor pixel data0 input pin. */
    1111. 

  1111. #define SYS_GPF_MFPL_PF7MFP_CAN2_TXD          (0x08UL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< CAN2 bus transmitter output. */
    1112. 

  1112. #define SYS_GPF_MFPL_PF7MFP_TAMPER1           (0x0AUL<<SYS_GPF_MFPL_PF7MFP_Pos)  /*!< TAMPER detector loop pin1. \hideinitializer */
    1113. 

  1113. /********************* Bit definition of GPF_MFPH register **********************/
    1114. 

  1114. #define SYS_GPF_MFPH_PF8MFP_GPIO              (0x00UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1115. 

  1115. #define SYS_GPF_MFPH_PF8MFP_EBI_ADR17         (0x02UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1116. 

  1116. #define SYS_GPF_MFPH_PF8MFP_SC0_RST           (0x03UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< SmartCard0 reset pin. \hideinitializer */
    1117. 

  1117. #define SYS_GPF_MFPH_PF8MFP_I2S0_DI           (0x04UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< I2S0 data input. \hideinitializer */
    1118. 

  1118. #define SYS_GPF_MFPH_PF8MFP_SPI0_CLK          (0x05UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< SPI0 serial clock pin. \hideinitializer */
    1119. 

  1119. #define SYS_GPF_MFPH_PF8MFP_UART5_nCTS        (0x06UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< Clear to Send input pin for UART5. \hideinitializer */
    1120. 

  1120. #define SYS_GPF_MFPH_PF8MFP_CCAP_DATA1        (0x07UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< Sensor pixel data1 input pin. \hideinitializer */
    1121. 

  1121. #define SYS_GPF_MFPH_PF8MFP_CAN1_RXD          (0x08UL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< CAN1 bus receiver input. */
    1122. 

  1122. #define SYS_GPF_MFPH_PF8MFP_TAMPER2           (0x0AUL<<SYS_GPF_MFPH_PF8MFP_Pos)  /*!< TAMPER detector loop pin2. \hideinitializer */
    1123. 

  1123. #define SYS_GPF_MFPH_PF9MFP_GPIO              (0x00UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1124. 

  1124. #define SYS_GPF_MFPH_PF9MFP_EBI_ADR16         (0x02UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1125. 

  1125. #define SYS_GPF_MFPH_PF9MFP_SC0_PWR           (0x03UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< SmartCard0 power pin. \hideinitializer */
    1126. 

  1126. #define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK         (0x04UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< I2S0 master clock output pin. \hideinitializer */
    1127. 

  1127. #define SYS_GPF_MFPH_PF9MFP_SPI0_SS           (0x05UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< 1st SPI0 slave select pin. \hideinitializer */
    1128. 

  1128. #define SYS_GPF_MFPH_PF9MFP_UART5_nRTS        (0x06UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< Request to Send output pin for UART5. \hideinitializer */
    1129. 

  1129. #define SYS_GPF_MFPH_PF9MFP_CCAP_DATA2        (0x07UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< Sensor pixel data2 input pin. \hideinitializer */
    1130. 

  1130. #define SYS_GPF_MFPH_PF9MFP_CAN1_TXD          (0x08UL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< CAN1 bus transmitter output. \hideinitializer */
    1131. 

  1131. #define SYS_GPF_MFPH_PF9MFP_TAMPER3           (0x0AUL<<SYS_GPF_MFPH_PF9MFP_Pos)  /*!< TAMPER detector loop pin3. \hideinitializer */
    1132. 

  1132. #define SYS_GPF_MFPH_PF10MFP_GPIO             (0x00UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1133. 

  1133. #define SYS_GPF_MFPH_PF10MFP_EBI_ADR15        (0x02UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    1134. 

  1134. #define SYS_GPF_MFPH_PF10MFP_SC0_nCD          (0x03UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SmartCard0 card detect pin. \hideinitializer */
    1135. 

  1135. #define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK        (0x04UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */
    1136. 

  1136. #define SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK     (0x05UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< SPI0 I2S master clock output pin. \hideinitializer */
    1137. 

  1137. #define SYS_GPF_MFPH_PF10MFP_UART5_RXD        (0x06UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< Data receiver input pin for UART5. \hideinitializer */
    1138. 

  1138. #define SYS_GPF_MFPH_PF10MFP_CCAP_DATA3       (0x07UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< Sensor pixel data3 input pin. \hideinitializer */
    1139. 

  1139. #define SYS_GPF_MFPH_PF10MFP_TAMPER4          (0x0AUL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< TAMPER detector loop pin4. \hideinitializer */
    1140. 

  1140. #define SYS_GPF_MFPH_PF11MFP_GPIO             (0x00UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1141. 

  1141. #define SYS_GPF_MFPH_PF11MFP_EBI_ADR14        (0x02UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< EBI address/data bus bit*. \hideinitializer */
    1142. 

  1142. #define SYS_GPF_MFPH_PF11MFP_SPI2_MOSI        (0x03UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< 1st SPI2 MOSI (Master Out, Slave In) pin. \hideinitializer */
    1143. 

  1143. #define SYS_GPF_MFPH_PF11MFP_UART5_TXD        (0x06UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< Data transmitter output pin for UART5. \hideinitializer */
    1144. 

  1144. #define SYS_GPF_MFPH_PF11MFP_CCAP_DATA4       (0x07UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< Sensor pixel data4 input pin. \hideinitializer */
    1145. 

  1145. #define SYS_GPF_MFPH_PF11MFP_TAMPER5          (0x0AUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< TAMPER detector loop pin5. \hideinitializer */
    1146. 

  1146. #define SYS_GPF_MFPH_PF11MFP_TM3              (0x0DUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< Timer3 event counter input / toggle output  \hideinitializer */
    1147. 

  1147. /********************* Bit definition of GPG_MFPL register **********************/
    1148. 

  1148. #define SYS_GPG_MFPL_PG0MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1149. 

  1149. #define SYS_GPG_MFPL_PG0MFP_EBI_ADR8          (0x02UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1150. 

  1150. #define SYS_GPG_MFPL_PG0MFP_I2C0_SCL          (0x04UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
    1151. 

  1151. #define SYS_GPG_MFPL_PG0MFP_I2C1_SMBAL        (0x05UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< I2C1 SMBus SMBALTER# pin  \hideinitializer  */
    1152. 

  1152. #define SYS_GPG_MFPL_PG0MFP_UART2_RXD         (0x06UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< Data receiver input pin for UART2. \hideinitializer */
    1153. 

  1153. #define SYS_GPG_MFPL_PG0MFP_CAN1_TXD          (0x07UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< CAN1 bus transmitter output. \hideinitializer */
    1154. 

  1154. #define SYS_GPG_MFPL_PG0MFP_UART1_TXD         (0x08UL<<SYS_GPG_MFPL_PG0MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
    1155. 

  1155. #define SYS_GPG_MFPL_PG1MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1156. 

  1156. #define SYS_GPG_MFPL_PG1MFP_EBI_ADR9          (0x02UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1157. 

  1157. #define SYS_GPG_MFPL_PG1MFP_SPI2_I2SMCLK      (0x03UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< SPI2 I2S master clock output pin. \hideinitializer */
    1158. 

  1158. #define SYS_GPG_MFPL_PG1MFP_I2C0_SDA          (0x04UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
    1159. 

  1159. #define SYS_GPG_MFPL_PG1MFP_I2C1_SMBSUS       (0x05UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
    1160. 

  1160. #define SYS_GPG_MFPL_PG1MFP_UART2_TXD         (0x06UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< Data transmitter output pin for UART2. \hideinitializer */
    1161. 

  1161. #define SYS_GPG_MFPL_PG1MFP_CAN1_RXD          (0x07UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< CAN1 bus receiver input. \hideinitializer */
    1162. 

  1162. #define SYS_GPG_MFPL_PG1MFP_UART1_RXD         (0x08UL<<SYS_GPG_MFPL_PG1MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
    1163. 

  1163. #define SYS_GPG_MFPL_PG2MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1164. 

  1164. #define SYS_GPG_MFPL_PG2MFP_EBI_ADR11         (0x02UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1165. 

  1165. #define SYS_GPG_MFPL_PG2MFP_SPI2_SS           (0x03UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< 1st SPI2 slave select pin. \hideinitializer */
    1166. 

  1166. #define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL        (0x04UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< I2C0 SMBus SMBALTER# pin  \hideinitializer  */
    1167. 

  1167. #define SYS_GPG_MFPL_PG2MFP_I2C1_SCL          (0x05UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< I2C1 clock pin. \hideinitializer */
    1168. 

  1168. #define SYS_GPG_MFPL_PG2MFP_CCAP_DATA7        (0x07UL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< Sensor pixel data7 input pin. \hideinitializer */
    1169. 

  1169. #define SYS_GPG_MFPL_PG2MFP_TM0               (0x0DUL<<SYS_GPG_MFPL_PG2MFP_Pos)  /*!< Timer0 event counter input / toggle output  \hideinitializer */
    1170. 

  1170. #define SYS_GPG_MFPL_PG3MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1171. 

  1171. #define SYS_GPG_MFPL_PG3MFP_EBI_ADR12         (0x02UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1172. 

  1172. #define SYS_GPG_MFPL_PG3MFP_SPI2_CLK          (0x03UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< SPI2 serial clock pin. \hideinitializer */
    1173. 

  1173. #define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS       (0x04UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
    1174. 

  1174. #define SYS_GPG_MFPL_PG3MFP_I2C1_SDA          (0x05UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< I2C1 data input/output pin. \hideinitializer */
    1175. 

  1175. #define SYS_GPG_MFPL_PG3MFP_CCAP_DATA6        (0x07UL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< Sensor pixel data6 input pin. \hideinitializer */
    1176. 

  1176. #define SYS_GPG_MFPL_PG3MFP_TM1               (0x0DUL<<SYS_GPG_MFPL_PG3MFP_Pos)  /*!< Timer1 event counter input / toggle output  \hideinitializer */
    1177. 

  1177. #define SYS_GPG_MFPL_PG4MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1178. 

  1178. #define SYS_GPG_MFPL_PG4MFP_EBI_ADR13         (0x02UL<<SYS_GPG_MFPL_PG4MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1179. 

  1179. #define SYS_GPG_MFPL_PG4MFP_SPI2_MISO         (0x03UL<<SYS_GPG_MFPL_PG4MFP_Pos)  /*!< 1st SPI2 MISO (Master In, Slave Out) pin. \hideinitializer */
    1180. 

  1180. #define SYS_GPG_MFPL_PG4MFP_CCAP_DATA5        (0x07UL<<SYS_GPG_MFPL_PG4MFP_Pos)  /*!< Sensor pixel data5 input pin. \hideinitializer */
    1181. 

  1181. #define SYS_GPG_MFPL_PG4MFP_TM2               (0x0DUL<<SYS_GPG_MFPL_PG4MFP_Pos)  /*!< Timer2 event counter input / toggle output \hideinitializer  */
    1182. 

  1182. #define SYS_GPG_MFPL_PG5MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1183. 

  1183. #define SYS_GPG_MFPL_PG5MFP_EBI_nCS1          (0x02UL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
    1184. 

  1184. #define SYS_GPG_MFPL_PG5MFP_SPI3_SS           (0x03UL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< 1st SPI3 slave select pin. \hideinitializer */
    1185. 

  1185. #define SYS_GPG_MFPL_PG5MFP_SC1_PWR           (0x04UL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< SmartCard1 power pin. \hideinitializer */
    1186. 

  1186. #define SYS_GPG_MFPL_PG5MFP_EPWM0_CH3         (0x0BUL<<SYS_GPG_MFPL_PG5MFP_Pos)  /*!< EPWM0 channel3 output/capture input. \hideinitializer */
    1187. 

  1187. #define SYS_GPG_MFPL_PG6MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1188. 

  1188. #define SYS_GPG_MFPL_PG6MFP_EBI_nCS2          (0x02UL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< EBI chip select enable output pin. \hideinitializer */
    1189. 

  1189. #define SYS_GPG_MFPL_PG6MFP_SPI3_CLK          (0x03UL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< SPI3 serial clock pin. \hideinitializer */
    1190. 

  1190. #define SYS_GPG_MFPL_PG6MFP_SC1_RST           (0x04UL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< SmartCard1 reset pin. \hideinitializer */
    1191. 

  1191. #define SYS_GPG_MFPL_PG6MFP_EPWM0_CH2         (0x0BUL<<SYS_GPG_MFPL_PG6MFP_Pos)  /*!< EPWM0 channel2 output/capture input. \hideinitializer */
    1192. 

  1192. #define SYS_GPG_MFPL_PG7MFP_GPIO              (0x00UL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1193. 

  1193. #define SYS_GPG_MFPL_PG7MFP_EBI_nWRL          (0x02UL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
    1194. 

  1194. #define SYS_GPG_MFPL_PG7MFP_SPI3_MISO         (0x03UL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< 1st SPI3 MISO (Master In, Slave Out) pin. \hideinitializer */
    1195. 

  1195. #define SYS_GPG_MFPL_PG7MFP_SC1_DAT           (0x04UL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< SmartCard1 data pin. \hideinitializer */
    1196. 

  1196. #define SYS_GPG_MFPL_PG7MFP_EPWM0_CH1         (0x0BUL<<SYS_GPG_MFPL_PG7MFP_Pos)  /*!< EPWM0 channel1 output/capture input. \hideinitializer */
    1197. 

  1197. /********************* Bit definition of GPG_MFPH register **********************/
    1198. 

  1198. #define SYS_GPG_MFPH_PG8MFP_GPIO              (0x00UL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1199. 

  1199. #define SYS_GPG_MFPH_PG8MFP_EBI_nWRH          (0x02UL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< EBI write enable output pin. \hideinitializer */
    1200. 

  1200. #define SYS_GPG_MFPH_PG8MFP_SPI3_MOSI         (0x03UL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< 1st SPI3 MOSI (Master Out, Slave In) pin. \hideinitializer */
    1201. 

  1201. #define SYS_GPG_MFPH_PG8MFP_SC1_CLK           (0x04UL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< SmartCard1 clock pin. \hideinitializer */
    1202. 

  1202. #define SYS_GPG_MFPH_PG8MFP_EPWM0_CH0         (0x0BUL<<SYS_GPG_MFPH_PG8MFP_Pos)  /*!< EPWM0 channel0 output/capture input. \hideinitializer */
    1203. 

  1203. #define SYS_GPG_MFPH_PG9MFP_GPIO              (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1204. 

  1204. #define SYS_GPG_MFPH_PG9MFP_EBI_AD0           (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< EBI address/data bus bit0. \hideinitializer */
    1205. 

  1205. #define SYS_GPG_MFPH_PG9MFP_SD1_DAT3          (0x03UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< SD/SDIO 1 data line bit 3. \hideinitializer */
    1206. 

  1206. #define SYS_GPG_MFPH_PG9MFP_SPIM_D2           (0x04UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< SPIM data 2 pin for Quad Mode I/O. \hideinitializer */
    1207. 

  1207. #define SYS_GPG_MFPH_PG9MFP_QSPI1_MISO1       (0x05UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< 2nd QSPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    1208. 

  1208. #define SYS_GPG_MFPH_PG9MFP_CCAP_PIXCLK       (0x07UL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< Sensor pixel clock(from sensor) input pin. \hideinitializer */
    1209. 

  1209. #define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5         (0x0CUL<<SYS_GPG_MFPH_PG9MFP_Pos)  /*!< BPWM0 channel5 output/capture input. \hideinitializer */
    1210. 

  1210. #define SYS_GPG_MFPH_PG10MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1211. 

  1211. #define SYS_GPG_MFPH_PG10MFP_EBI_AD1          (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
    1212. 

  1212. #define SYS_GPG_MFPH_PG10MFP_SD1_DAT2         (0x03UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SD/SDIO 1 data line bit 2. \hideinitializer */
    1213. 

  1213. #define SYS_GPG_MFPH_PG10MFP_SPIM_D3          (0x04UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< SPIM data 3 pin for Quad Mode I/O. \hideinitializer */
    1214. 

  1214. #define SYS_GPG_MFPH_PG10MFP_QSPI1_MOSI1      (0x05UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< 2nd QSPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    1215. 

  1215. #define SYS_GPG_MFPH_PG10MFP_CCAP_SCLK        (0x07UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< Sensor pixel clock(to sensor) output pin. \hideinitializer */
    1216. 

  1216. #define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4        (0x0CUL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< BPWM0 channel4 output/capture input. \hideinitializer */
    1217. 

  1217. #define SYS_GPG_MFPH_PG11MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1218. 

  1218. #define SYS_GPG_MFPH_PG11MFP_EBI_AD2          (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< EBI address/data bus bit2. \hideinitializer */
    1219. 

  1219. #define SYS_GPG_MFPH_PG11MFP_SD1_DAT1         (0x03UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< SD/SDIO 1 data line bit 1. \hideinitializer */
    1220. 

  1220. #define SYS_GPG_MFPH_PG11MFP_SPIM_SS          (0x04UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< 1st SPIM slave select pin. \hideinitializer */
    1221. 

  1221. #define SYS_GPG_MFPH_PG11MFP_QSPI1_SS         (0x05UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< 1st QSPI1 slave select pin. \hideinitializer */
    1222. 

  1222. #define SYS_GPG_MFPH_PG11MFP_UART7_TXD        (0x06UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< Data transmitter output pin for UART7. \hideinitializer */
    1223. 

  1223. #define SYS_GPG_MFPH_PG11MFP_CCAP_SFIELD      (0x07UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< Even/Odd Field Flag input pin. \hideinitializer */
    1224. 

  1224. #define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3        (0x0CUL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< BPWM0 channel3 output/capture input. \hideinitializer */
    1225. 

  1225. #define SYS_GPG_MFPH_PG12MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1226. 

  1226. #define SYS_GPG_MFPH_PG12MFP_EBI_AD3          (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< EBI address/data bus bit3. \hideinitializer */
    1227. 

  1227. #define SYS_GPG_MFPH_PG12MFP_SD1_DAT0         (0x03UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SD/SDIO 1 data line bit 0. \hideinitializer */
    1228. 

  1228. #define SYS_GPG_MFPH_PG12MFP_SPIM_CLK         (0x04UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< SPIM serial clock pin. \hideinitializer */
    1229. 

  1229. #define SYS_GPG_MFPH_PG12MFP_QSPI1_CLK        (0x05UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< QSPI1 serial clock pin. \hideinitializer */
    1230. 

  1230. #define SYS_GPG_MFPH_PG12MFP_UART7_RXD        (0x06UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< Data receiver input pin for UART7. \hideinitializer */
    1231. 

  1231. #define SYS_GPG_MFPH_PG12MFP_CCAP_VSYNC       (0x07UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< Sensor vertical synchronization input pin. \hideinitializer */
    1232. 

  1232. #define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2        (0x0CUL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< BPWM0 channel2 output/capture input. \hideinitializer */
    1233. 

  1233. #define SYS_GPG_MFPH_PG13MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1234. 

  1234. #define SYS_GPG_MFPH_PG13MFP_EBI_AD4          (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< EBI address/data bus bit4. \hideinitializer */
    1235. 

  1235. #define SYS_GPG_MFPH_PG13MFP_SD1_CMD          (0x03UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< SD/SDIO 1 command/response. \hideinitializer */
    1236. 

  1236. #define SYS_GPG_MFPH_PG13MFP_SPIM_MISO        (0x04UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< 1st SPIM MISO (Master In, Slave Out) pin. \hideinitializer */
    1237. 

  1237. #define SYS_GPG_MFPH_PG13MFP_QSPI1_MISO0      (0x05UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< 1st QSPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    1238. 

  1238. #define SYS_GPG_MFPH_PG13MFP_UART6_TXD        (0x06UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< Data transmitter output pin for UART6. \hideinitializer */
    1239. 

  1239. #define SYS_GPG_MFPH_PG13MFP_CCAP_HSYNC       (0x07UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< Sensor horizontal synchronization input pin. \hideinitializer */
    1240. 

  1240. #define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1        (0x0CUL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< BPWM0 channel1 output/capture input. \hideinitializer */
    1241. 

  1241. #define SYS_GPG_MFPH_PG14MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1242. 

  1242. #define SYS_GPG_MFPH_PG14MFP_EBI_AD5          (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< EBI address/data bus bit5. \hideinitializer */
    1243. 

  1243. #define SYS_GPG_MFPH_PG14MFP_SD1_CLK          (0x03UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< SD/SDIO 1 clock. \hideinitializer */
    1244. 

  1244. #define SYS_GPG_MFPH_PG14MFP_SPIM_MOSI        (0x04UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< 1st SPIM MOSI (Master Out, Slave In) pin. \hideinitializer */
    1245. 

  1245. #define SYS_GPG_MFPH_PG14MFP_QSPI1_MOSI0      (0x05UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< 1st QSPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    1246. 

  1246. #define SYS_GPG_MFPH_PG14MFP_UART6_RXD        (0x06UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< Data receiver input pin for UART6. \hideinitializer */
    1247. 

  1247. #define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0        (0x0CUL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
    1248. 

  1248. #define SYS_GPG_MFPH_PG15MFP_GPIO             (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1249. 

  1249. #define SYS_GPG_MFPH_PG15MFP_SD1_nCD          (0x03UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< SD/SDIO 1 card detect  \hideinitializer */
    1250. 

  1250. #define SYS_GPG_MFPH_PG15MFP_CLKO             (0x0EUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< Clock Output pin. \hideinitializer */
    1251. 

  1251. #define SYS_GPG_MFPH_PG15MFP_EADC0_ST         (0x0FUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< EADC external trigger input. \hideinitializer */
    1252. 

  1252. /********************* Bit definition of GPH_MFPL register **********************/
    1253. 

  1253. #define SYS_GPH_MFPL_PH0MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH0MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1254. 

  1254. #define SYS_GPH_MFPL_PH0MFP_EBI_ADR7          (0x02UL<<SYS_GPH_MFPL_PH0MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1255. 

  1255. #define SYS_GPH_MFPL_PH0MFP_UART5_TXD         (0x04UL<<SYS_GPH_MFPL_PH0MFP_Pos)  /*!< Data transmitter output pin for UART5. \hideinitializer */
    1256. 

  1256. #define SYS_GPH_MFPL_PH0MFP_TM0_EXT           (0x0DUL<<SYS_GPH_MFPL_PH0MFP_Pos)  /*!< Timer0 event counter input / toggle output  \hideinitializer */
    1257. 

  1257. #define SYS_GPH_MFPL_PH1MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH1MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1258. 

  1258. #define SYS_GPH_MFPL_PH1MFP_EBI_ADR6          (0x02UL<<SYS_GPH_MFPL_PH1MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1259. 

  1259. #define SYS_GPH_MFPL_PH1MFP_UART5_RXD         (0x04UL<<SYS_GPH_MFPL_PH1MFP_Pos)  /*!< Data receiver input pin for UART5. \hideinitializer */
    1260. 

  1260. #define SYS_GPH_MFPL_PH1MFP_TM1_EXT           (0x0DUL<<SYS_GPH_MFPL_PH1MFP_Pos)  /*!< Timer1 event counter input / toggle output  \hideinitializer */
    1261. 

  1261. #define SYS_GPH_MFPL_PH2MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1262. 

  1262. #define SYS_GPH_MFPL_PH2MFP_EBI_ADR5          (0x02UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1263. 

  1263. #define SYS_GPH_MFPL_PH2MFP_UART5_nRTS        (0x04UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< Request to Send output pin for UART5. \hideinitializer */
    1264. 

  1264. #define SYS_GPH_MFPL_PH2MFP_UART4_TXD         (0x05UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< Data transmitter output pin for UART4. \hideinitializer */
    1265. 

  1265. #define SYS_GPH_MFPL_PH2MFP_I2C0_SCL          (0x06UL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< I2C0 clock pin. \hideinitializer */
    1266. 

  1266. #define SYS_GPH_MFPL_PH2MFP_TM2_EXT           (0x0DUL<<SYS_GPH_MFPL_PH2MFP_Pos)  /*!< Timer2 event counter input / toggle output  \hideinitializer */
    1267. 

  1267. #define SYS_GPH_MFPL_PH3MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1268. 

  1268. #define SYS_GPH_MFPL_PH3MFP_EBI_ADR4          (0x02UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1269. 

  1269. #define SYS_GPH_MFPL_PH3MFP_SPI1_I2SMCLK      (0x03UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< SPI1 I2S master clock output pin. \hideinitializer */
    1270. 

  1270. #define SYS_GPH_MFPL_PH3MFP_UART5_nCTS        (0x04UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< Clear to Send input pin for UART5. \hideinitializer */
    1271. 

  1271. #define SYS_GPH_MFPL_PH3MFP_UART4_RXD         (0x05UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< Data receiver input pin for UART4. \hideinitializer */
    1272. 

  1272. #define SYS_GPH_MFPL_PH3MFP_I2C0_SDA          (0x06UL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< I2C0 data input/output pin. \hideinitializer */
    1273. 

  1273. #define SYS_GPH_MFPL_PH3MFP_TM3_EXT           (0x0DUL<<SYS_GPH_MFPL_PH3MFP_Pos)  /*!< Timer3 event counter input / toggle output  \hideinitializer */
    1274. 

  1274. #define SYS_GPH_MFPL_PH4MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH4MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1275. 

  1275. #define SYS_GPH_MFPL_PH4MFP_EBI_ADR3          (0x02UL<<SYS_GPH_MFPL_PH4MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1276. 

  1276. #define SYS_GPH_MFPL_PH4MFP_SPI1_MISO         (0x03UL<<SYS_GPH_MFPL_PH4MFP_Pos)  /*!< 1st SPI1 MISO (Master In, Slave Out) pin. \hideinitializer */
    1277. 

  1277. #define SYS_GPH_MFPL_PH4MFP_UART7_nRTS        (0x04UL<<SYS_GPH_MFPL_PH4MFP_Pos)  /*!< Request to Send output pin for UART7. \hideinitializer */
    1278. 

  1278. #define SYS_GPH_MFPL_PH4MFP_UART6_TXD         (0x05UL<<SYS_GPH_MFPL_PH4MFP_Pos)  /*!< Data transmitter output pin for UART6. \hideinitializer */
    1279. 

  1279. #define SYS_GPH_MFPL_PH5MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH5MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1280. 

  1280. #define SYS_GPH_MFPL_PH5MFP_EBI_ADR2          (0x02UL<<SYS_GPH_MFPL_PH5MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1281. 

  1281. #define SYS_GPH_MFPL_PH5MFP_SPI1_MOSI         (0x03UL<<SYS_GPH_MFPL_PH5MFP_Pos)  /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. \hideinitializer */
    1282. 

  1282. #define SYS_GPH_MFPL_PH5MFP_UART7_nCTS        (0x04UL<<SYS_GPH_MFPL_PH5MFP_Pos)  /*!< Clear to Send input pin for UART7. \hideinitializer */
    1283. 

  1283. #define SYS_GPH_MFPL_PH5MFP_UART6_RXD         (0x05UL<<SYS_GPH_MFPL_PH5MFP_Pos)  /*!< Data receiver input pin for UART6. \hideinitializer */
    1284. 

  1284. #define SYS_GPH_MFPL_PH6MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH6MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1285. 

  1285. #define SYS_GPH_MFPL_PH6MFP_EBI_ADR1          (0x02UL<<SYS_GPH_MFPL_PH6MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1286. 

  1286. #define SYS_GPH_MFPL_PH6MFP_SPI1_CLK          (0x03UL<<SYS_GPH_MFPL_PH6MFP_Pos)  /*!< SPI1 serial clock pin. \hideinitializer */
    1287. 

  1287. #define SYS_GPH_MFPL_PH6MFP_UART7_TXD         (0x04UL<<SYS_GPH_MFPL_PH6MFP_Pos)  /*!< Data transmitter output pin for UART7. \hideinitializer */
    1288. 

  1288. #define SYS_GPH_MFPL_PH7MFP_GPIO              (0x00UL<<SYS_GPH_MFPL_PH7MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1289. 

  1289. #define SYS_GPH_MFPL_PH7MFP_EBI_ADR0          (0x02UL<<SYS_GPH_MFPL_PH7MFP_Pos)  /*!< EBI address/data bus bit*. \hideinitializer */
    1290. 

  1290. #define SYS_GPH_MFPL_PH7MFP_SPI1_SS           (0x03UL<<SYS_GPH_MFPL_PH7MFP_Pos)  /*!< 1st SPI1 slave select pin. \hideinitializer */
    1291. 

  1291. #define SYS_GPH_MFPL_PH7MFP_UART7_RXD         (0x04UL<<SYS_GPH_MFPL_PH7MFP_Pos)  /*!< Data receiver input pin for UART7. \hideinitializer */
    1292. 

  1292. /********************* Bit definition of GPH_MFPH register **********************/
    1293. 

  1293. #define SYS_GPH_MFPH_PH8MFP_GPIO              (0x00UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1294. 

  1294. #define SYS_GPH_MFPH_PH8MFP_EBI_AD12          (0x02UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
    1295. 

  1295. #define SYS_GPH_MFPH_PH8MFP_QSPI0_CLK         (0x03UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< QSPI0 serial clock pin. \hideinitializer */
    1296. 

  1296. #define SYS_GPH_MFPH_PH8MFP_SC2_PWR           (0x04UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< SmartCard2 power pin. \hideinitializer */
    1297. 

  1297. #define SYS_GPH_MFPH_PH8MFP_I2S0_DI           (0x05UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< I2S0 data input. \hideinitializer */
    1298. 

  1298. #define SYS_GPH_MFPH_PH8MFP_SPI1_CLK          (0x06UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< SPI1 serial clock pin. \hideinitializer */
    1299. 

  1299. #define SYS_GPH_MFPH_PH8MFP_UART3_nRTS        (0x07UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< Request to Send output pin for UART3. \hideinitializer */
    1300. 

  1300. #define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL        (0x08UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< I2C1 SMBus SMBALTER# pin  \hideinitializer  */
    1301. 

  1301. #define SYS_GPH_MFPH_PH8MFP_I2C2_SCL          (0x09UL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< I2C2 clock pin. \hideinitializer */
    1302. 

  1302. #define SYS_GPH_MFPH_PH8MFP_UART1_TXD         (0x0AUL<<SYS_GPH_MFPH_PH8MFP_Pos)  /*!< Data transmitter output pin for UART1. \hideinitializer */
    1303. 

  1303. #define SYS_GPH_MFPH_PH9MFP_GPIO              (0x00UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< General purpose digital I/O pin. \hideinitializer */
    1304. 

  1304. #define SYS_GPH_MFPH_PH9MFP_EBI_AD13          (0x02UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< EBI address/data bus bit1. \hideinitializer */
    1305. 

  1305. #define SYS_GPH_MFPH_PH9MFP_QSPI0_SS          (0x03UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< 1st QSPI0 slave select pin. \hideinitializer */
    1306. 

  1306. #define SYS_GPH_MFPH_PH9MFP_SC2_RST           (0x04UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< SmartCard2 reset pin. \hideinitializer */
    1307. 

  1307. #define SYS_GPH_MFPH_PH9MFP_I2S0_DO           (0x05UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< I2S0 data output. \hideinitializer */
    1308. 

  1308. #define SYS_GPH_MFPH_PH9MFP_SPI1_SS           (0x06UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< 1st SPI1 slave select pin. \hideinitializer */
    1309. 

  1309. #define SYS_GPH_MFPH_PH9MFP_UART3_nCTS        (0x07UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< Clear to Send input pin for UART3. \hideinitializer */
    1310. 

  1310. #define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS       (0x08UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)  \hideinitializer */
    1311. 

  1311. #define SYS_GPH_MFPH_PH9MFP_I2C2_SDA          (0x09UL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< I2C2 data input/output pin. \hideinitializer */
    1312. 

  1312. #define SYS_GPH_MFPH_PH9MFP_UART1_RXD         (0x0AUL<<SYS_GPH_MFPH_PH9MFP_Pos)  /*!< Data receiver input pin for UART1. \hideinitializer */
    1313. 

  1313. #define SYS_GPH_MFPH_PH10MFP_GPIO             (0x00UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1314. 

  1314. #define SYS_GPH_MFPH_PH10MFP_EBI_AD14         (0x02UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
    1315. 

  1315. #define SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1      (0x03UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< 2nd QSPI0 MISO (Master In, Slave Out) pin. \hideinitializer */
    1316. 

  1316. #define SYS_GPH_MFPH_PH10MFP_SC2_nCD          (0x04UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SmartCard2 card detect pin. \hideinitializer */
    1317. 

  1317. #define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK        (0x05UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< I2S0 left right channel clock. \hideinitializer */
    1318. 

  1318. #define SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK     (0x06UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< SPI1 I2S master clock output pin. \hideinitializer */
    1319. 

  1319. #define SYS_GPH_MFPH_PH10MFP_UART4_TXD        (0x07UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART4. \hideinitializer */
    1320. 

  1320. #define SYS_GPH_MFPH_PH10MFP_UART0_TXD        (0x08UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< Data transmitter output pin for UART0. \hideinitializer */
    1321. 

  1321. #define SYS_GPH_MFPH_PH11MFP_GPIO             (0x00UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
    1322. 

  1322. #define SYS_GPH_MFPH_PH11MFP_EBI_AD15         (0x02UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EBI address/data bus bit1. \hideinitializer */
    1323. 

  1323. #define SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1      (0x03UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< 2nd QSPI0 MOSI (Master Out, Slave In) pin. \hideinitializer */
    1324. 

  1324. #define SYS_GPH_MFPH_PH11MFP_UART4_RXD        (0x07UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART4. \hideinitializer */
    1325. 

  1325. #define SYS_GPH_MFPH_PH11MFP_UART0_RXD        (0x08UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< Data receiver input pin for UART0. \hideinitializer */
    1326. 

  1326. #define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5        (0x0BUL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< EPWM0 channel5 output/capture input. \hideinitializer */
    1327. 

  1327. 

  1328. /*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
    1329. 

  1329. 

  1330. 

  1331. /** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
    1332. 

  1332.   @{
    1333. 

  1333. */
    1334. 

  1334. 

  1335. 

  1336. /**
    1337. 

  1337.   * @brief      Clear Brown-out detector interrupt flag
    1338. 

  1338.   * @param      None
    1339. 

  1339.   * @return     None
    1340. 

  1340.   * @details    This macro clear Brown-out detector interrupt flag.
    1341. 

  1341.   * \hideinitializer
    1342. 

  1342.   */
    1343. 

  1343. #define SYS_CLEAR_BOD_INT_FLAG()        (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
    1344. 

  1344. 

  1345. /**
    1346. 

  1346.   * @brief      Set Brown-out detector function to normal mode
    1347. 

  1347.   * @param      None
    1348. 

  1348.   * @return     None
    1349. 

  1349.   * @details    This macro set Brown-out detector to normal mode.
    1350. 

  1350.   *             The register write-protection function should be disabled before using this macro.
    1351. 

  1351.   * \hideinitializer
    1352. 

  1352.   */
    1353. 

  1353. #define SYS_CLEAR_BOD_LPM()             (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
    1354. 

  1354. 

  1355. /**
    1356. 

  1356.   * @brief      Disable Brown-out detector function
    1357. 

  1357.   * @param      None
    1358. 

  1358.   * @return     None
    1359. 

  1359.   * @details    This macro disable Brown-out detector function.
    1360. 

  1360.   *             The register write-protection function should be disabled before using this macro.
    1361. 

  1361.   * \hideinitializer
    1362. 

  1362.   */
    1363. 

  1363. #define SYS_DISABLE_BOD()               (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
    1364. 

  1364. 

  1365. /**
    1366. 

  1366.   * @brief      Enable Brown-out detector function
    1367. 

  1367.   * @param      None
    1368. 

  1368.   * @return     None
    1369. 

  1369.   * @details    This macro enable Brown-out detector function.
    1370. 

  1370.   *             The register write-protection function should be disabled before using this macro.
    1371. 

  1371.   * \hideinitializer
    1372. 

  1372.   */
    1373. 

  1373. #define SYS_ENABLE_BOD()                (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
    1374. 

  1374. 

  1375. /**
    1376. 

  1376.   * @brief      Get Brown-out detector interrupt flag
    1377. 

  1377.   * @param      None
    1378. 

  1378.   * @retval     0   Brown-out detect interrupt flag is not set.
    1379. 

  1379.   * @retval     >=1 Brown-out detect interrupt flag is set.
    1380. 

  1380.   * @details    This macro get Brown-out detector interrupt flag.
    1381. 

  1381.   * \hideinitializer
    1382. 

  1382.   */
    1383. 

  1383. #define SYS_GET_BOD_INT_FLAG()          (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
    1384. 

  1384. 

  1385. /**
    1386. 

  1386.   * @brief      Get Brown-out detector status
    1387. 

  1387.   * @param      None
    1388. 

  1388.   * @retval     0   System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
    1389. 

  1389.   * @retval     >=1 System voltage is lower than BOD threshold voltage setting.
    1390. 

  1390.   * @details    This macro get Brown-out detector output status.
    1391. 

  1391.   *             If the BOD function is disabled, this function always return 0.
    1392. 

  1392.   * \hideinitializer
    1393. 

  1393.   */
    1394. 

  1394. #define SYS_GET_BOD_OUTPUT()            (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
    1395. 

  1395. 

  1396. /**
    1397. 

  1397.   * @brief      Enable Brown-out detector interrupt function
    1398. 

  1398.   * @param      None
    1399. 

  1399.   * @return     None
    1400. 

  1400.   * @details    This macro enable Brown-out detector interrupt function.
    1401. 

  1401.   *             The register write-protection function should be disabled before using this macro.
    1402. 

  1402.   * \hideinitializer
    1403. 

  1403.   */
    1404. 

  1404. #define SYS_DISABLE_BOD_RST()           (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
    1405. 

  1405. 

  1406. /**
    1407. 

  1407.   * @brief      Enable Brown-out detector reset function
    1408. 

  1408.   * @param      None
    1409. 

  1409.   * @return     None
    1410. 

  1410.   * @details    This macro enable Brown-out detect reset function.
    1411. 

  1411.   *             The register write-protection function should be disabled before using this macro.
    1412. 

  1412.   * \hideinitializer
    1413. 

  1413.   */
    1414. 

  1414. #define SYS_ENABLE_BOD_RST()            (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
    1415. 

  1415. 

  1416. /**
    1417. 

  1417.   * @brief      Set Brown-out detector function low power mode
    1418. 

  1418.   * @param      None
    1419. 

  1419.   * @return     None
    1420. 

  1420.   * @details    This macro set Brown-out detector to low power mode.
    1421. 

  1421.   *             The register write-protection function should be disabled before using this macro.
    1422. 

  1422.   * \hideinitializer
    1423. 

  1423.   */
    1424. 

  1424. #define SYS_SET_BOD_LPM()               (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
    1425. 

  1425. 

  1426. /**
    1427. 

  1427.   * @brief      Set Brown-out detector voltage level
    1428. 

  1428.   * @param[in]  u32Level is Brown-out voltage level. Including :
    1429. 

  1429.   *             - \ref SYS_BODCTL_BODVL_3_0V
    1430. 

  1430.   *             - \ref SYS_BODCTL_BODVL_2_8V
    1431. 

  1431.   *             - \ref SYS_BODCTL_BODVL_2_6V
    1432. 

  1432.   *             - \ref SYS_BODCTL_BODVL_2_4V
    1433. 

  1433.   *             - \ref SYS_BODCTL_BODVL_2_2V
    1434. 

  1434.   *             - \ref SYS_BODCTL_BODVL_2_0V
    1435. 

  1435.   *             - \ref SYS_BODCTL_BODVL_1_8V
    1436. 

  1436.   *             - \ref SYS_BODCTL_BODVL_1_6V
    1437. 

  1437.   * @return     None
    1438. 

  1438.   * @details    This macro set Brown-out detector voltage level.
    1439. 

  1439.   *             The write-protection function should be disabled before using this macro.
    1440. 

  1440.   * \hideinitializer
    1441. 

  1441.   */
    1442. 

  1442. #define SYS_SET_BOD_LEVEL(u32Level)     (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
    1443. 

  1443. 

  1444. /**
    1445. 

  1445.   * @brief      Get reset source is from Brown-out detector reset
    1446. 

  1446.   * @param      None
    1447. 

  1447.   * @retval     0   Previous reset source is not from Brown-out detector reset
    1448. 

  1448.   * @retval     >=1 Previous reset source is from Brown-out detector reset
    1449. 

  1449.   * @details    This macro get previous reset source is from Brown-out detect reset or not.
    1450. 

  1450.   * \hideinitializer
    1451. 

  1451.   */
    1452. 

  1452. #define SYS_IS_BOD_RST()                (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
    1453. 

  1453. 

  1454. /**
    1455. 

  1455.   * @brief      Get reset source is from CPU reset
    1456. 

  1456.   * @param      None
    1457. 

  1457.   * @retval     0   Previous reset source is not from CPU reset
    1458. 

  1458.   * @retval     >=1 Previous reset source is from CPU reset
    1459. 

  1459.   * @details    This macro get previous reset source is from CPU reset.
    1460. 

  1460.   * \hideinitializer
    1461. 

  1461.   */
    1462. 

  1462. #define SYS_IS_CPU_RST()                (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
    1463. 

  1463. 

  1464. /**
    1465. 

  1465.   * @brief      Get reset source is from LVR Reset
    1466. 

  1466.   * @param      None
    1467. 

  1467.   * @retval     0   Previous reset source is not from Low-Voltage-Reset
    1468. 

  1468.   * @retval     >=1 Previous reset source is from Low-Voltage-Reset
    1469. 

  1469.   * @details    This macro get previous reset source is from Low-Voltage-Reset.
    1470. 

  1470.   * \hideinitializer
    1471. 

  1471.   */
    1472. 

  1472. #define SYS_IS_LVR_RST()                (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
    1473. 

  1473. 

  1474. /**
    1475. 

  1475.   * @brief      Get reset source is from Power-on Reset
    1476. 

  1476.   * @param      None
    1477. 

  1477.   * @retval     0   Previous reset source is not from Power-on Reset
    1478. 

  1478.   * @retval     >=1 Previous reset source is from Power-on Reset
    1479. 

  1479.   * @details    This macro get previous reset source is from Power-on Reset.
    1480. 

  1480.   * \hideinitializer
    1481. 

  1481.   */
    1482. 

  1482. #define SYS_IS_POR_RST()                (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
    1483. 

  1483. 

  1484. /**
    1485. 

  1485.   * @brief      Get reset source is from reset pin reset
    1486. 

  1486.   * @param      None
    1487. 

  1487.   * @retval     0   Previous reset source is not from reset pin reset
    1488. 

  1488.   * @retval     >=1 Previous reset source is from reset pin reset
    1489. 

  1489.   * @details    This macro get previous reset source is from reset pin reset.
    1490. 

  1490.   * \hideinitializer
    1491. 

  1491.   */
    1492. 

  1492. #define SYS_IS_RSTPIN_RST()             (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
    1493. 

  1493. 

  1494. /**
    1495. 

  1495.   * @brief      Get reset source is from system reset
    1496. 

  1496.   * @param      None
    1497. 

  1497.   * @retval     0   Previous reset source is not from system reset
    1498. 

  1498.   * @retval     >=1 Previous reset source is from system reset
    1499. 

  1499.   * @details    This macro get previous reset source is from system reset.
    1500. 

  1500.   * \hideinitializer
    1501. 

  1501.   */
    1502. 

  1502. #define SYS_IS_SYSTEM_RST()             (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
    1503. 

  1503. 

  1504. /**
    1505. 

  1505.   * @brief      Get reset source is from window watch dog reset
    1506. 

  1506.   * @param      None
    1507. 

  1507.   * @retval     0   Previous reset source is not from window watch dog reset
    1508. 

  1508.   * @retval     >=1 Previous reset source is from window watch dog reset
    1509. 

  1509.   * @details    This macro get previous reset source is from window watch dog reset.
    1510. 

  1510.   * \hideinitializer
    1511. 

  1511.   */
    1512. 

  1512. #define SYS_IS_WDT_RST()                (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
    1513. 

  1513. 

  1514. /**
    1515. 

  1515.   * @brief      Disable Low-Voltage-Reset function
    1516. 

  1516.   * @param      None
    1517. 

  1517.   * @return     None
    1518. 

  1518.   * @details    This macro disable Low-Voltage-Reset function.
    1519. 

  1519.   *             The register write-protection function should be disabled before using this macro.
    1520. 

  1520.   * \hideinitializer
    1521. 

  1521.   */
    1522. 

  1522. #define SYS_DISABLE_LVR()               (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
    1523. 

  1523. 

  1524. /**
    1525. 

  1525.   * @brief      Enable Low-Voltage-Reset function
    1526. 

  1526.   * @param      None
    1527. 

  1527.   * @return     None
    1528. 

  1528.   * @details    This macro enable Low-Voltage-Reset function.
    1529. 

  1529.   *             The register write-protection function should be disabled before using this macro.
    1530. 

  1530.   * \hideinitializer
    1531. 

  1531.   */
    1532. 

  1532. #define SYS_ENABLE_LVR()                (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
    1533. 

  1533. 

  1534. /**
    1535. 

  1535.   * @brief      Disable Power-on Reset function
    1536. 

  1536.   * @param      None
    1537. 

  1537.   * @return     None
    1538. 

  1538.   * @details    This macro disable Power-on Reset function.
    1539. 

  1539.   *             The register write-protection function should be disabled before using this macro.
    1540. 

  1540.   * \hideinitializer
    1541. 

  1541.   */
    1542. 

  1542. #define SYS_DISABLE_POR()               (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0x5AA5):(SYS->PORDISAN = 0x5AA5))
    1543. 

  1543. 

  1544. /**
    1545. 

  1545.   * @brief      Enable Power-on Reset function
    1546. 

  1546.   * @param      None
    1547. 

  1547.   * @return     None
    1548. 

  1548.   * @details    This macro enable Power-on Reset function.
    1549. 

  1549.   *             The register write-protection function should be disabled before using this macro.
    1550. 

  1550.   * \hideinitializer
    1551. 

  1551.   */
    1552. 

  1552. #define SYS_ENABLE_POR()               (((SYS->CSERVER & SYS_CSERVER_VERSION_Msk) == 0) ? (SYS->PORCTL = 0):(SYS->PORDISAN = 0))
    1553. 

  1553. 

  1554. /**
    1555. 

  1555.   * @brief      Clear reset source flag
    1556. 

  1556.   * @param[in]  u32RstSrc is reset source. Including :
    1557. 

  1557.   *             - \ref SYS_RSTSTS_PORF_Msk
    1558. 

  1558.   *             - \ref SYS_RSTSTS_PINRF_Msk
    1559. 

  1559.   *             - \ref SYS_RSTSTS_WDTRF_Msk
    1560. 

  1560.   *             - \ref SYS_RSTSTS_LVRF_Msk
    1561. 

  1561.   *             - \ref SYS_RSTSTS_BODRF_Msk
    1562. 

  1562.   *             - \ref SYS_RSTSTS_SYSRF_Msk
    1563. 

  1563.   *             - \ref SYS_RSTSTS_CPURF_Msk
    1564. 

  1564.   *             - \ref SYS_RSTSTS_CPULKRF_Msk
    1565. 

  1565.   * @return     None
    1566. 

  1566.   * @details    This macro clear reset source flag.
    1567. 

  1567.   * \hideinitializer
    1568. 

  1568.   */
    1569. 

  1569. #define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
    1570. 

  1570. 

  1571. 

  1572. /*---------------------------------------------------------------------------------------------------------*/
    1573. 

  1573. /* static inline functions                                                                                 */
    1574. 

  1574. /*---------------------------------------------------------------------------------------------------------*/
    1575. 

  1575. /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
    1576. 

  1576. __STATIC_INLINE void SYS_UnlockReg(void);
    1577. 

  1577. __STATIC_INLINE void SYS_LockReg(void);
    1578. 

  1578. 

  1579. /**
    1580. 

  1580.   * @brief      Disable register write-protection function
    1581. 

  1581.   * @param      None
    1582. 

  1582.   * @return     None
    1583. 

  1583.   * @details    This function disable register write-protection function.
    1584. 

  1584.   *             To unlock the protected register to allow write access.
    1585. 

  1585.   */
    1586. 

  1586. __STATIC_INLINE void SYS_UnlockReg(void)
    1587. 

  1587. {
    1588. 

  1588.     do
    1589. 

  1589.     {
    1590. 

  1590.         SYS->REGLCTL = 0x59UL;
    1591. 

  1591.         SYS->REGLCTL = 0x16UL;
    1592. 

  1592.         SYS->REGLCTL = 0x88UL;
    1593. 

  1593.     }
    1594. 

  1594.     while(SYS->REGLCTL == 0UL);
    1595. 

  1595. }
    1596. 

  1596. 

  1597. /**
    1598. 

  1598.   * @brief      Enable register write-protection function
    1599. 

  1599.   * @param      None
    1600. 

  1600.   * @return     None
    1601. 

  1601.   * @details    This function is used to enable register write-protection function.
    1602. 

  1602.   *             To lock the protected register to forbid write access.
    1603. 

  1603.   */
    1604. 

  1604. __STATIC_INLINE void SYS_LockReg(void)
    1605. 

  1605. {
    1606. 

  1606.     SYS->REGLCTL = 0UL;
    1607. 

  1607. }
    1608. 

  1608. 

  1609. 

  1610. void SYS_ClearResetSrc(uint32_t u32Src);
    1611. 

  1611. uint32_t SYS_GetBODStatus(void);
    1612. 

  1612. uint32_t SYS_GetResetSrc(void);
    1613. 

  1613. uint32_t SYS_IsRegLocked(void);
    1614. 

  1614. uint32_t SYS_ReadPDID(void);
    1615. 

  1615. void SYS_ResetChip(void);
    1616. 

  1616. void SYS_ResetCPU(void);
    1617. 

  1617. void SYS_ResetModule(uint32_t u32ModuleIndex);
    1618. 

  1618. void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
    1619. 

  1619. void SYS_DisableBOD(void);
    1620. 

  1620. void SYS_SetPowerLevel(uint32_t u32PowerLevel);
    1621. 

  1621. void SYS_SetVRef(uint32_t u32VRefCTL);
    1622. 

  1622. 

  1623. /*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
    1624. 

  1624. 

  1625. /*@}*/ /* end of group SYS_Driver */
    1626. 

  1626. 

  1627. /*@}*/ /* end of group Standard_Driver */
    1628. 

  1628. 

  1629. 

  1630. #ifdef __cplusplus
    1631. 

  1631. }
    1632. 

  1632. #endif
    1633. 

  1633. 

  1634. #endif  /* __NU_SYS_H__ */
    1635. 

  1635. 

  1636. /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
    1637.