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nu_crypto.h

nu_crypto.h 49 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file     crypto.h
    3. 

  3.  * @version  V1.10
    4. 

  4.  * $Revision: 2 $
    5. 

  5.  * $Date: 15/05/06 3:55p $
    6. 

  6.  * @brief    Cryptographic Accelerator driver header file
    7. 

  7.  *
    8. 

  8.  * @note
    9. 

  9.  * SPDX-License-Identifier: Apache-2.0
    10. 

  10.  * Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
    11. 

  11.  ******************************************************************************/
    12. 

  12. #ifndef __NU_CRYPTO_H__
    13. 

  13. #define __NU_CRYPTO_H__
    14. 

  14. 

  15. #include "N9H30.h"
    16. 

  16. #include "nu_sys.h"
    17. 

  17. 

  18. #ifdef __cplusplus
    19. 

  19. extern "C"
    20. 

  20. {
    21. 

  21. #endif
    22. 

  22. 

  23. /** @addtogroup N9H30_Device_Driver N9H30 Device Driver
    24. 

  24.   @{
    25. 

  25. */
    26. 

  26. 

  27. /** @addtogroup N9H30_CRYPTO_Driver CRYPTO Driver
    28. 

  28.   @{
    29. 

  29. */
    30. 

  30. 

  31. /// @cond HIDDEN_SYMBOLS
    32. 

  32. 

  33. typedef struct
    34. 

  34. {
    35. 

  35.     __IO uint32_t INTEN;           /*!< Offset: 0x000:  Crypto Interrupt Enable Control Register      */
    36. 

  36.     __IO uint32_t INTSTS;          /*!< Offset: 0x004:  Crypto Interrupt Flag                         */
    37. 

  37.     __IO uint32_t PRNG_CTL;        /*!< Offset: 0x008:  PRNG Control Flag                             */
    38. 

  38.     __IO uint32_t PRNG_SEED;       /*!< Offset: 0x00C:  PRNG Control Flag                             */
    39. 

  39.     __I  uint32_t PRNG_KEY[8];     /*!< Offset: 0x010:  PRNG Generated Key0 - Key7                    */
    40. 

  40.     uint32_t RESERVE0[8];
    41. 

  41.     __I  uint32_t AES_FDBCK0;      /*!< Offset: 0x050:  AES Engine Output Feedback Data after Cryptographic Operation */
    42. 

  42.     __I  uint32_t AES_FDBCK1;      /*!< Offset: 0x054:  AES Engine Output Feedback Data after Cryptographic Operation */
    43. 

  43.     __I  uint32_t AES_FDBCK2;      /*!< Offset: 0x058:  AES Engine Output Feedback Data after Cryptographic Operation */
    44. 

  44.     __I  uint32_t AES_FDBCK3;      /*!< Offset: 0x05C:  AES Engine Output Feedback Data after Cryptographic Operation */
    45. 

  45.     __I  uint32_t TDES_FDBCKH;     /*!< Offset: 0x060:  TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */
    46. 

  46.     __I  uint32_t TDES_FDBCKL;     /*!< Offset: 0x064:  TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation  */
    47. 

  47.     uint32_t RESERVE1[38];
    48. 

  48.     __IO uint32_t AES_CTL;         /*!< Offset: 0x100:  AES Control Register                          */
    49. 

  49.     __IO uint32_t AES_STS;         /*!< Offset: 0x104:  AES Engine Flag                               */
    50. 

  50.     __IO uint32_t AES_DATIN;       /*!< Offset: 0x108:  AES Engine Data Input Port Register           */
    51. 

  51.     __I  uint32_t AES_DATOUT;      /*!< Offset: 0x10C:  AES Engine Data Output Port Register          */
    52. 

  52.     __IO uint32_t AES0_KEY0;       /*!< Offset: 0x110:  AES Key Word 0 Register for Channel 0         */
    53. 

  53.     __IO uint32_t AES0_KEY1;       /*!< Offset: 0x114:  AES Key Word 1 Register for Channel 0         */
    54. 

  54.     __IO uint32_t AES0_KEY2;       /*!< Offset: 0x118:  AES Key Word 2 Register for Channel 0         */
    55. 

  55.     __IO uint32_t AES0_KEY3;       /*!< Offset: 0x11C:  AES Key Word 3 Register for Channel 0         */
    56. 

  56.     __IO uint32_t AES0_KEY4;       /*!< Offset: 0x120:  AES Key Word 4 Register for Channel 0         */
    57. 

  57.     __IO uint32_t AES0_KEY5;       /*!< Offset: 0x124:  AES Key Word 5 Register for Channel 0         */
    58. 

  58.     __IO uint32_t AES0_KEY6;       /*!< Offset: 0x128:  AES Key Word 6 Register for Channel 0         */
    59. 

  59.     __IO uint32_t AES0_KEY7;       /*!< Offset: 0x12C:  AES Key Word 7 Register for Channel 0         */
    60. 

  60.     __IO uint32_t AES0_IV0;        /*!< Offset: 0x130:  AES Initial Vector Word 0 Register for Channel 0   */
    61. 

  61.     __IO uint32_t AES0_IV1;        /*!< Offset: 0x134:  AES Initial Vector Word 1 Register for Channel 0   */
    62. 

  62.     __IO uint32_t AES0_IV2;        /*!< Offset: 0x138:  AES Initial Vector Word 2 Register for Channel 0   */
    63. 

  63.     __IO uint32_t AES0_IV3;        /*!< Offset: 0x13C:  AES Initial Vector Word 3 Register for Channel 0   */
    64. 

  64.     __IO uint32_t AES0_SADDR;      /*!< Offset: 0x140:  AES DMA Source Address Register for Channel 0      */
    65. 

  65.     __IO uint32_t AES0_DADDR;      /*!< Offset: 0x144:  AES DMA Destination Address Register for Channel 0 */
    66. 

  66.     __IO uint32_t AES0_CNT;        /*!< Offset: 0x148:  AES Byte Count Register for Channel 0              */
    67. 

  67.     __IO uint32_t AES1_KEY0;       /*!< Offset: 0x14C:  AES Key Word 0 Register for Channel 1         */
    68. 

  68.     __IO uint32_t AES1_KEY1;       /*!< Offset: 0x150:  AES Key Word 1 Register for Channel 1         */
    69. 

  69.     __IO uint32_t AES1_KEY2;       /*!< Offset: 0x154:  AES Key Word 2 Register for Channel 1         */
    70. 

  70.     __IO uint32_t AES1_KEY3;       /*!< Offset: 0x158:  AES Key Word 3 Register for Channel 1         */
    71. 

  71.     __IO uint32_t AES1_KEY4;       /*!< Offset: 0x15C:  AES Key Word 4 Register for Channel 1         */
    72. 

  72.     __IO uint32_t AES1_KEY5;       /*!< Offset: 0x160:  AES Key Word 5 Register for Channel 1         */
    73. 

  73.     __IO uint32_t AES1_KEY6;       /*!< Offset: 0x164:  AES Key Word 6 Register for Channel 1         */
    74. 

  74.     __IO uint32_t AES1_KEY7;       /*!< Offset: 0x168:  AES Key Word 7 Register for Channel 1         */
    75. 

  75.     __IO uint32_t AES1_IV0;        /*!< Offset: 0x16C:  AES Initial Vector Word 0 Register for Channel 1   */
    76. 

  76.     __IO uint32_t AES1_IV1;        /*!< Offset: 0x170:  AES Initial Vector Word 1 Register for Channel 1   */
    77. 

  77.     __IO uint32_t AES1_IV2;        /*!< Offset: 0x174:  AES Initial Vector Word 2 Register for Channel 1   */
    78. 

  78.     __IO uint32_t AES1_IV3;        /*!< Offset: 0x178:  AES Initial Vector Word 3 Register for Channel 1   */
    79. 

  79.     __IO uint32_t AES1_SADDR;      /*!< Offset: 0x17C:  AES DMA Source Address Register for Channel 1      */
    80. 

  80.     __IO uint32_t AES1_DADDR;      /*!< Offset: 0x180:  AES DMA Destination Address Register for Channel 1 */
    81. 

  81.     __IO uint32_t AES1_CNT;        /*!< Offset: 0x184:  AES Byte Count Register for Channel 1              */
    82. 

  82.     __IO uint32_t AES2_KEY0;       /*!< Offset: 0x188:  AES Key Word 0 Register for Channel 2         */
    83. 

  83.     __IO uint32_t AES2_KEY1;       /*!< Offset: 0x18C:  AES Key Word 1 Register for Channel 2         */
    84. 

  84.     __IO uint32_t AES2_KEY2;       /*!< Offset: 0x190:  AES Key Word 2 Register for Channel 2         */
    85. 

  85.     __IO uint32_t AES2_KEY3;       /*!< Offset: 0x194:  AES Key Word 3 Register for Channel 2         */
    86. 

  86.     __IO uint32_t AES2_KEY4;       /*!< Offset: 0x198:  AES Key Word 4 Register for Channel 2         */
    87. 

  87.     __IO uint32_t AES2_KEY5;       /*!< Offset: 0x19C:  AES Key Word 5 Register for Channel 2         */
    88. 

  88.     __IO uint32_t AES2_KEY6;       /*!< Offset: 0x1A0:  AES Key Word 6 Register for Channel 2         */
    89. 

  89.     __IO uint32_t AES2_KEY7;       /*!< Offset: 0x1A4:  AES Key Word 7 Register for Channel 2         */
    90. 

  90.     __IO uint32_t AES2_IV0;        /*!< Offset: 0x1A8:  AES Initial Vector Word 0 Register for Channel 2   */
    91. 

  91.     __IO uint32_t AES2_IV1;        /*!< Offset: 0x1AC:  AES Initial Vector Word 1 Register for Channel 2   */
    92. 

  92.     __IO uint32_t AES2_IV2;        /*!< Offset: 0x1B0:  AES Initial Vector Word 2 Register for Channel 2   */
    93. 

  93.     __IO uint32_t AES2_IV3;        /*!< Offset: 0x1B4:  AES Initial Vector Word 3 Register for Channel 2   */
    94. 

  94.     __IO uint32_t AES2_SADDR;      /*!< Offset: 0x1B8:  AES DMA Source Address Register for Channel 2      */
    95. 

  95.     __IO uint32_t AES2_DADDR;      /*!< Offset: 0x1BC:  AES DMA Destination Address Register for Channel 2 */
    96. 

  96.     __IO uint32_t AES2_CNT;        /*!< Offset: 0x1C0:  AES Byte Count Register for Channel 2              */
    97. 

  97.     __IO uint32_t AES3_KEY0;       /*!< Offset: 0x1C4:  AES Key Word 0 Register for Channel 3         */
    98. 

  98.     __IO uint32_t AES3_KEY1;       /*!< Offset: 0x1C8:  AES Key Word 1 Register for Channel 3         */
    99. 

  99.     __IO uint32_t AES3_KEY2;       /*!< Offset: 0x1CC:  AES Key Word 2 Register for Channel 3         */
    100. 

  100.     __IO uint32_t AES3_KEY3;       /*!< Offset: 0x1D0:  AES Key Word 3 Register for Channel 3         */
    101. 

  101.     __IO uint32_t AES3_KEY4;       /*!< Offset: 0x1D4:  AES Key Word 4 Register for Channel 3         */
    102. 

  102.     __IO uint32_t AES3_KEY5;       /*!< Offset: 0x1D8:  AES Key Word 5 Register for Channel 3         */
    103. 

  103.     __IO uint32_t AES3_KEY6;       /*!< Offset: 0x1DC:  AES Key Word 6 Register for Channel 3         */
    104. 

  104.     __IO uint32_t AES3_KEY7;       /*!< Offset: 0x1E0:  AES Key Word 7 Register for Channel 3         */
    105. 

  105.     __IO uint32_t AES3_IV0;        /*!< Offset: 0x1E4:  AES Initial Vector Word 0 Register for Channel 3   */
    106. 

  106.     __IO uint32_t AES3_IV1;        /*!< Offset: 0x1E8:  AES Initial Vector Word 1 Register for Channel 3   */
    107. 

  107.     __IO uint32_t AES3_IV2;        /*!< Offset: 0x1EC:  AES Initial Vector Word 2 Register for Channel 3   */
    108. 

  108.     __IO uint32_t AES3_IV3;        /*!< Offset: 0x1F0:  AES Initial Vector Word 3 Register for Channel 3   */
    109. 

  109.     __IO uint32_t AES3_SADDR;      /*!< Offset: 0x1F4:  AES DMA Source Address Register for Channel 3      */
    110. 

  110.     __IO uint32_t AES3_DADDR;      /*!< Offset: 0x1F8:  AES DMA Destination Address Register for Channel 3 */
    111. 

  111.     __IO uint32_t AES3_CNT;        /*!< Offset: 0x1FC:  AES Byte Count Register for Channel 3              */
    112. 

  112.     __IO uint32_t TDES_CTL;        /*!< Offset: 0x200:  TDES/DES Control Register                     */
    113. 

  113.     __IO uint32_t TDES_STS;        /*!< Offset: 0x204:  TDES/DES Engine Flag                          */
    114. 

  114.     __IO uint32_t TDES0_KEY1H;     /*!< Offset: 0x208:  TDES/DES Key 1 High Word Register for Channel 0    */
    115. 

  115.     __IO uint32_t TDES0_KEY1L;     /*!< Offset: 0x20C:  TDES/DES Key 1 Low Word Register for Channel 0     */
    116. 

  116.     __IO uint32_t TDES0_KEY2H;     /*!< Offset: 0x210:  TDES/DES Key 2 High Word Register for Channel 0    */
    117. 

  117.     __IO uint32_t TDES0_KEY2L;     /*!< Offset: 0x214:  TDES/DES Key 2 Low Word Register for Channel 0     */
    118. 

  118.     __IO uint32_t TDES0_KEY3H;     /*!< Offset: 0x218:  TDES/DES Key 3 High Word Register for Channel 0    */
    119. 

  119.     __IO uint32_t TDES0_KEY3L;     /*!< Offset: 0x21C:  TDES/DES Key 3 Low Word Register for Channel 0     */
    120. 

  120.     __IO uint32_t TDES0_IVH;       /*!< Offset: 0x220:  TDES/DES Initial Vector High Word Register for Channel 0  */
    121. 

  121.     __IO uint32_t TDES0_IVL;       /*!< Offset: 0x224:  TDES/DES Initial Vector Low Word Register for Channel 0   */
    122. 

  122.     __IO uint32_t TDES0_SADDR;     /*!< Offset: 0x228:  TDES/DES DMA Source Address Register for Channel 0        */
    123. 

  123.     __IO uint32_t TDES0_DADDR;     /*!< Offset: 0x22C:  TDES/DES DMA Destination Address Register for Channel 0   */
    124. 

  124.     __IO uint32_t TDES0_CNT;       /*!< Offset: 0x230:  TDES/DES Byte Count Register for Channel 0    */
    125. 

  125.     __IO uint32_t TDES_DATIN;      /*!< Offset: 0x234:  TDES/DES Engine Input data Word Register      */
    126. 

  126.     __IO uint32_t TDES_DATOUT;     /*!< Offset: 0x238:  TDES/DES Engine Output data Word Register     */
    127. 

  127.     uint32_t RESERVE2[3];
    128. 

  128.     __IO uint32_t TDES1_KEY1H;     /*!< Offset: 0x248:  TDES/DES Key 1 High Word Register for Channel 1    */
    129. 

  129.     __IO uint32_t TDES1_KEY1L;     /*!< Offset: 0x24C:  TDES/DES Key 1 Low Word Register for Channel 1     */
    130. 

  130.     __IO uint32_t TDES1_KEY2H;     /*!< Offset: 0x250:  TDES/DES Key 2 High Word Register for Channel 1    */
    131. 

  131.     __IO uint32_t TDES1_KEY2L;     /*!< Offset: 0x254:  TDES/DES Key 2 Low Word Register for Channel 1     */
    132. 

  132.     __IO uint32_t TDES1_KEY3H;     /*!< Offset: 0x258:  TDES/DES Key 3 High Word Register for Channel 1    */
    133. 

  133.     __IO uint32_t TDES1_KEY3L;     /*!< Offset: 0x25C:  TDES/DES Key 3 Low Word Register for Channel 1     */
    134. 

  134.     __IO uint32_t TDES1_IVH;       /*!< Offset: 0x260:  TDES/DES Initial Vector High Word Register for Channel 1  */
    135. 

  135.     __IO uint32_t TDES1_IVL;       /*!< Offset: 0x264:  TDES/DES Initial Vector Low Word Register for Channel 1   */
    136. 

  136.     __IO uint32_t TDES1_SADDR;     /*!< Offset: 0x268:  TDES/DES DMA Source Address Register for Channel 1        */
    137. 

  137.     __IO uint32_t TDES1_DADDR;     /*!< Offset: 0x26C:  TDES/DES DMA Destination Address Register for Channel 1   */
    138. 

  138.     __IO uint32_t TDES1_CNT;       /*!< Offset: 0x270:  TDES/DES Byte Count Register for Channel 1    */
    139. 

  139.     uint32_t RESERVE3[5];
    140. 

  140.     __IO uint32_t TDES2_KEY1H;     /*!< Offset: 0x288:  TDES/DES Key 1 High Word Register for Channel 2    */
    141. 

  141.     __IO uint32_t TDES2_KEY1L;     /*!< Offset: 0x28C:  TDES/DES Key 1 Low Word Register for Channel 2     */
    142. 

  142.     __IO uint32_t TDES2_KEY2H;     /*!< Offset: 0x290:  TDES/DES Key 2 High Word Register for Channel 2    */
    143. 

  143.     __IO uint32_t TDES2_KEY2L;     /*!< Offset: 0x294:  TDES/DES Key 2 Low Word Register for Channel 2     */
    144. 

  144.     __IO uint32_t TDES2_KEY3H;     /*!< Offset: 0x298:  TDES/DES Key 3 High Word Register for Channel 2    */
    145. 

  145.     __IO uint32_t TDES2_KEY3L;     /*!< Offset: 0x29C:  TDES/DES Key 3 Low Word Register for Channel 2     */
    146. 

  146.     __IO uint32_t TDES2_IVH;       /*!< Offset: 0x2A0:  TDES/DES Initial Vector High Word Register for Channel 2  */
    147. 

  147.     __IO uint32_t TDES2_IVL;       /*!< Offset: 0x2A4:  TDES/DES Initial Vector Low Word Register for Channel 2   */
    148. 

  148.     __IO uint32_t TDES2_SADDR;     /*!< Offset: 0x2A8:  TDES/DES DMA Source Address Register for Channel 2        */
    149. 

  149.     __IO uint32_t TDES2_DADDR;     /*!< Offset: 0x2AC:  TDES/DES DMA Destination Address Register for Channel 2   */
    150. 

  150.     __IO uint32_t TDES2_CNT;       /*!< Offset: 0x2B0:  TDES/DES Byte Count Register for Channel 2    */
    151. 

  151.     uint32_t RESERVE4[5];
    152. 

  152.     __IO uint32_t TDES3_KEY1H;     /*!< Offset: 0x2C8:  TDES/DES Key 1 High Word Register for Channel 3    */
    153. 

  153.     __IO uint32_t TDES3_KEY1L;     /*!< Offset: 0x2CC:  TDES/DES Key 1 Low Word Register for Channel 3     */
    154. 

  154.     __IO uint32_t TDES3_KEY2H;     /*!< Offset: 0x2D0:  TDES/DES Key 2 High Word Register for Channel 3    */
    155. 

  155.     __IO uint32_t TDES3_KEY2L;     /*!< Offset: 0x2D4:  TDES/DES Key 2 Low Word Register for Channel 3     */
    156. 

  156.     __IO uint32_t TDES3_KEY3H;     /*!< Offset: 0x2D8:  TDES/DES Key 3 High Word Register for Channel 3    */
    157. 

  157.     __IO uint32_t TDES3_KEY3L;     /*!< Offset: 0x2DC:  TDES/DES Key 3 Low Word Register for Channel 3     */
    158. 

  158.     __IO uint32_t TDES3_IVH;       /*!< Offset: 0x2E0:  TDES/DES Initial Vector High Word Register for Channel 3  */
    159. 

  159.     __IO uint32_t TDES3_IVL;       /*!< Offset: 0x2E4:  TDES/DES Initial Vector Low Word Register for Channel 3   */
    160. 

  160.     __IO uint32_t TDES3_SADDR;     /*!< Offset: 0x2E8:  TDES/DES DMA Source Address Register for Channel 3        */
    161. 

  161.     __IO uint32_t TDES3_DADDR;     /*!< Offset: 0x2EC:  TDES/DES DMA Destination Address Register for Channel 3   */
    162. 

  162.     __IO uint32_t TDES3_CNT;       /*!< Offset: 0x2F0:  TDES/DES Byte Count Register for Channel 3    */
    163. 

  163.     uint32_t RESERVE5[3];
    164. 

  164.     __IO uint32_t HMAC_CTL;        /*!< Offset: 0x300:  SHA/HMAC Control Register                     */
    165. 

  165.     __IO uint32_t HMAC_STS;        /*!< Offset: 0x304:  SHA/HMAC Status Register                      */
    166. 

  166.     __IO uint32_t HMAC_DGST0;      /*!< Offset: 0x308:  SHA/HMAC Digest Message 0                     */
    167. 

  167.     __IO uint32_t HMAC_DGST1;      /*!< Offset: 0x30C:  SHA/HMAC Digest Message 1                     */
    168. 

  168.     __IO uint32_t HMAC_DGST2;      /*!< Offset: 0x310:  SHA/HMAC Digest Message 2                     */
    169. 

  169.     __IO uint32_t HMAC_DGST3;      /*!< Offset: 0x314:  SHA/HMAC Digest Message 3                     */
    170. 

  170.     __IO uint32_t HMAC_DGST4;      /*!< Offset: 0x318:  SHA/HMAC Digest Message 4                     */
    171. 

  171.     __IO uint32_t HMAC_DGST5;      /*!< Offset: 0x31C:  SHA/HMAC Digest Message 5                     */
    172. 

  172.     __IO uint32_t HMAC_DGST6;      /*!< Offset: 0x320:  SHA/HMAC Digest Message 6                     */
    173. 

  173.     __IO uint32_t HMAC_DGST7;      /*!< Offset: 0x324:  SHA/HMAC Digest Message 7                     */
    174. 

  174.     __IO uint32_t HMAC_DGST8;      /*!< Offset: 0x328:  SHA/HMAC Digest Message 8                     */
    175. 

  175.     __IO uint32_t HMAC_DGST9;      /*!< Offset: 0x32C:  SHA/HMAC Digest Message 9                     */
    176. 

  176.     __IO uint32_t HMAC_DGST10;     /*!< Offset: 0x330:  SHA/HMAC Digest Message 10                    */
    177. 

  177.     __IO uint32_t HMAC_DGST11;     /*!< Offset: 0x334:  SHA/HMAC Digest Message 11                    */
    178. 

  178.     __IO uint32_t HMAC_DGST12;     /*!< Offset: 0x338:  SHA/HMAC Digest Message 12                    */
    179. 

  179.     __IO uint32_t HMAC_DGST13;     /*!< Offset: 0x33C:  SHA/HMAC Digest Message 13                    */
    180. 

  180.     __IO uint32_t HMAC_DGST14;     /*!< Offset: 0x340:  SHA/HMAC Digest Message 14                    */
    181. 

  181.     __IO uint32_t HMAC_DGST15;     /*!< Offset: 0x344:  SHA/HMAC Digest Message 15                    */
    182. 

  182.     __IO uint32_t HMAC_KEYCNT;     /*!< Offset: 0x348:  SHA/HMAC Key Byte Count                       */
    183. 

  183.     __IO uint32_t HMAC_SADDR;      /*!< Offset: 0x34C:  SHA/HMAC DMA Source Address Register          */
    184. 

  184.     __IO uint32_t HMAC_DMACNT;     /*!< Offset: 0x350:  SHA/HMAC Byte Count Register                  */
    185. 

  185.     __IO uint32_t HMAC_DATIN;      /*!< Offset: 0x354:  SHA/HMAC Engine Non-DMA Mode Data Input Port Register */
    186. 

  186. } CRPT_T;
    187. 

  187. 

  188. 

  189. #define CRPT            ((CRPT_T *) CRPT_BA)
    190. 

  190. 

  191. 

  192. /**
    193. 

  193.     @addtogroup CRPT_CONST CRPT Bit Field Definition
    194. 

  194.     Constant Definitions for CRPT Controller
    195. 

  195. @{ */
    196. 

  196. 

  197. #define CRPT_INTEN_AESIEN_Pos            (0)                                               /*!< CRPT INTEN: AESIEN Position            */
    198. 

  198. #define CRPT_INTEN_AESIEN_Msk            (0x1ul << CRPT_INTEN_AESIEN_Pos)                  /*!< CRPT INTEN: AESIEN Mask                */
    199. 

  199. 

  200. #define CRPT_INTEN_AESERRIEN_Pos         (1)                                               /*!< CRPT INTEN: AESERRIEN Position         */
    201. 

  201. #define CRPT_INTEN_AESERRIEN_Msk         (0x1ul << CRPT_INTEN_AESERRIEN_Pos)               /*!< CRPT INTEN: AESERRIEN Mask             */
    202. 

  202. 

  203. #define CRPT_INTEN_TDESIEN_Pos           (8)                                               /*!< CRPT INTEN: TDESIEN Position           */
    204. 

  204. #define CRPT_INTEN_TDESIEN_Msk           (0x1ul << CRPT_INTEN_TDESIEN_Pos)                 /*!< CRPT INTEN: TDESIEN Mask               */
    205. 

  205. 

  206. #define CRPT_INTEN_TDESERRIEN_Pos        (9)                                               /*!< CRPT INTEN: TDESERRIEN Position        */
    207. 

  207. #define CRPT_INTEN_TDESERRIEN_Msk        (0x1ul << CRPT_INTEN_TDESERRIEN_Pos)              /*!< CRPT INTEN: TDESERRIEN Mask            */
    208. 

  208. 

  209. #define CRPT_INTEN_PRNGIEN_Pos           (16)                                              /*!< CRPT INTEN: PRNGIEN Position           */
    210. 

  210. #define CRPT_INTEN_PRNGIEN_Msk           (0x1ul << CRPT_INTEN_PRNGIEN_Pos)                 /*!< CRPT INTEN: PRNGIEN Mask               */
    211. 

  211. 

  212. #define CRPT_INTEN_SHAIEN_Pos            (24)                                              /*!< CRPT INTEN: SHAIEN Position            */
    213. 

  213. #define CRPT_INTEN_SHAIEN_Msk            (0x1ul << CRPT_INTEN_SHAIEN_Pos)                  /*!< CRPT INTEN: SHAIEN Mask                */
    214. 

  214. 

  215. #define CRPT_INTEN_SHAERRIEN_Pos         (25)                                              /*!< CRPT INTEN: SHAERRIEN Position         */
    216. 

  216. #define CRPT_INTEN_SHAERRIEN_Msk         (0x1ul << CRPT_INTEN_SHAERRIEN_Pos)               /*!< CRPT INTEN: SHAERRIEN Mask             */
    217. 

  217. 

  218. #define CRPT_INTSTS_AESIF_Pos            (0)                                               /*!< CRPT INTSTS: AESIF Position            */
    219. 

  219. #define CRPT_INTSTS_AESIF_Msk            (0x1ul << CRPT_INTSTS_AESIF_Pos)                  /*!< CRPT INTSTS: AESIF Mask                */
    220. 

  220. 

  221. #define CRPT_INTSTS_AESERRIF_Pos         (1)                                               /*!< CRPT INTSTS: AESERRIF Position         */
    222. 

  222. #define CRPT_INTSTS_AESERRIF_Msk         (0x1ul << CRPT_INTSTS_AESERRIF_Pos)               /*!< CRPT INTSTS: AESERRIF Mask             */
    223. 

  223. 

  224. #define CRPT_INTSTS_TDESIF_Pos           (8)                                               /*!< CRPT INTSTS: TDESIF Position           */
    225. 

  225. #define CRPT_INTSTS_TDESIF_Msk           (0x1ul << CRPT_INTSTS_TDESIF_Pos)                 /*!< CRPT INTSTS: TDESIF Mask               */
    226. 

  226. 

  227. #define CRPT_INTSTS_TDESERRIF_Pos        (9)                                               /*!< CRPT INTSTS: TDESERRIF Position        */
    228. 

  228. #define CRPT_INTSTS_TDESERRIF_Msk        (0x1ul << CRPT_INTSTS_TDESERRIF_Pos)              /*!< CRPT INTSTS: TDESERRIF Mask            */
    229. 

  229. 

  230. #define CRPT_INTSTS_PRNGIF_Pos           (16)                                              /*!< CRPT INTSTS: PRNGIF Position           */
    231. 

  231. #define CRPT_INTSTS_PRNGIF_Msk           (0x1ul << CRPT_INTSTS_PRNGIF_Pos)                 /*!< CRPT INTSTS: PRNGIF Mask               */
    232. 

  232. 

  233. #define CRPT_INTSTS_SHAIF_Pos            (24)                                              /*!< CRPT INTSTS: SHAIF Position            */
    234. 

  234. #define CRPT_INTSTS_SHAIF_Msk            (0x1ul << CRPT_INTSTS_SHAIF_Pos)                  /*!< CRPT INTSTS: SHAIF Mask                */
    235. 

  235. 

  236. #define CRPT_INTSTS_SHAERRIF_Pos         (25)                                              /*!< CRPT INTSTS: SHAERRIF Position         */
    237. 

  237. #define CRPT_INTSTS_SHAERRIF_Msk         (0x1ul << CRPT_INTSTS_SHAERRIF_Pos)               /*!< CRPT INTSTS: SHAERRIF Mask             */
    238. 

  238. 

  239. #define CRPT_PRNG_CTL_START_Pos          (0)                                               /*!< CRPT PRNG_CTL: START Position          */
    240. 

  240. #define CRPT_PRNG_CTL_START_Msk          (0x1ul << CRPT_PRNG_CTL_START_Pos)                /*!< CRPT PRNG_CTL: START Mask              */
    241. 

  241. 

  242. #define CRPT_PRNG_CTL_SEEDRLD_Pos        (1)                                               /*!< CRPT PRNG_CTL: SEEDRLD Position        */
    243. 

  243. #define CRPT_PRNG_CTL_SEEDRLD_Msk        (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos)              /*!< CRPT PRNG_CTL: SEEDRLD Mask            */
    244. 

  244. 

  245. #define CRPT_PRNG_CTL_KEYSZ_Pos          (2)                                               /*!< CRPT PRNG_CTL: KEYSZ Position          */
    246. 

  246. #define CRPT_PRNG_CTL_KEYSZ_Msk          (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos)                /*!< CRPT PRNG_CTL: KEYSZ Mask              */
    247. 

  247. 

  248. #define CRPT_PRNG_CTL_BUSY_Pos           (8)                                               /*!< CRPT PRNG_CTL: BUSY Position           */
    249. 

  249. #define CRPT_PRNG_CTL_BUSY_Msk           (0x1ul << CRPT_PRNG_CTL_BUSY_Pos)                 /*!< CRPT PRNG_CTL: BUSY Mask               */
    250. 

  250. 

  251. #define CRPT_AES_CTL_START_Pos           (0)                                               /*!< CRPT AES_CTL: START Position           */
    252. 

  252. #define CRPT_AES_CTL_START_Msk           (0x1ul << CRPT_AES_CTL_START_Pos)                 /*!< CRPT AES_CTL: START Mask               */
    253. 

  253. 

  254. #define CRPT_AES_CTL_STOP_Pos            (1)                                               /*!< CRPT AES_CTL: STOP Position            */
    255. 

  255. #define CRPT_AES_CTL_STOP_Msk            (0x1ul << CRPT_AES_CTL_STOP_Pos)                  /*!< CRPT AES_CTL: STOP Mask                */
    256. 

  256. 

  257. #define CRPT_AES_CTL_KEYSZ_Pos           (2)                                               /*!< CRPT AES_CTL: KEYSZ Position           */
    258. 

  258. #define CRPT_AES_CTL_KEYSZ_Msk           (0x3ul << CRPT_AES_CTL_KEYSZ_Pos)                 /*!< CRPT AES_CTL: KEYSZ Mask               */
    259. 

  259. 

  260. #define CRPT_AES_CTL_DMALAST_Pos         (5)                                               /*!< CRPT AES_CTL: DMALAST Position         */
    261. 

  261. #define CRPT_AES_CTL_DMALAST_Msk         (0x1ul << CRPT_AES_CTL_DMALAST_Pos)               /*!< CRPT AES_CTL: DMALAST Mask             */
    262. 

  262. 

  263. #define CRPT_AES_CTL_DMACSCAD_Pos        (6)                                               /*!< CRPT AES_CTL: DMACSCAD Position        */
    264. 

  264. #define CRPT_AES_CTL_DMACSCAD_Msk        (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos)              /*!< CRPT AES_CTL: DMACSCAD Mask            */
    265. 

  265. 

  266. #define CRPT_AES_CTL_DMAEN_Pos           (7)                                               /*!< CRPT AES_CTL: DMAEN Position           */
    267. 

  267. #define CRPT_AES_CTL_DMAEN_Msk           (0x1ul << CRPT_AES_CTL_DMAEN_Pos)                 /*!< CRPT AES_CTL: DMAEN Mask               */
    268. 

  268. 

  269. #define CRPT_AES_CTL_OPMODE_Pos          (8)                                               /*!< CRPT AES_CTL: OPMODE Position          */
    270. 

  270. #define CRPT_AES_CTL_OPMODE_Msk          (0xfful << CRPT_AES_CTL_OPMODE_Pos)               /*!< CRPT AES_CTL: OPMODE Mask              */
    271. 

  271. 

  272. #define CRPT_AES_CTL_ENCRPT_Pos          (16)                                              /*!< CRPT AES_CTL: ENCRPT Position          */
    273. 

  273. #define CRPT_AES_CTL_ENCRPT_Msk          (0x1ul << CRPT_AES_CTL_ENCRPT_Pos)                /*!< CRPT AES_CTL: ENCRPT Mask              */
    274. 

  274. 

  275. #define CRPT_AES_CTL_OUTSWAP_Pos         (22)                                              /*!< CRPT AES_CTL: OUTSWAP Position         */
    276. 

  276. #define CRPT_AES_CTL_OUTSWAP_Msk         (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos)               /*!< CRPT AES_CTL: OUTSWAP Mask             */
    277. 

  277. 

  278. #define CRPT_AES_CTL_INSWAP_Pos          (23)                                              /*!< CRPT AES_CTL: INSWAP Position          */
    279. 

  279. #define CRPT_AES_CTL_INSWAP_Msk          (0x1ul << CRPT_AES_CTL_INSWAP_Pos)                /*!< CRPT AES_CTL: INSWAP Mask              */
    280. 

  280. 

  281. #define CRPT_AES_CTL_CHANNEL_Pos         (24)                                              /*!< CRPT AES_CTL: CHANNEL Position         */
    282. 

  282. #define CRPT_AES_CTL_CHANNEL_Msk         (0x3ul << CRPT_AES_CTL_CHANNEL_Pos)               /*!< CRPT AES_CTL: CHANNEL Mask             */
    283. 

  283. 

  284. #define CRPT_AES_CTL_KEYUNPRT_Pos        (26)                                              /*!< CRPT AES_CTL: KEYUNPRT Position        */
    285. 

  285. #define CRPT_AES_CTL_KEYUNPRT_Msk        (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos)             /*!< CRPT AES_CTL: KEYUNPRT Mask            */
    286. 

  286. 

  287. #define CRPT_AES_CTL_KEYPRT_Pos          (31)                                              /*!< CRPT AES_CTL: KEYPRT Position          */
    288. 

  288. #define CRPT_AES_CTL_KEYPRT_Msk          (0x1ul << CRPT_AES_CTL_KEYPRT_Pos)                /*!< CRPT AES_CTL: KEYPRT Mask              */
    289. 

  289. 

  290. #define CRPT_AES_STS_BUSY_Pos            (0)                                               /*!< CRPT AES_STS: BUSY Position            */
    291. 

  291. #define CRPT_AES_STS_BUSY_Msk            (0x1ul << CRPT_AES_STS_BUSY_Pos)                  /*!< CRPT AES_STS: BUSY Mask                */
    292. 

  292. 

  293. #define CRPT_AES_STS_INBUFEMPTY_Pos      (8)                                               /*!< CRPT AES_STS: INBUFEMPTY Position      */
    294. 

  294. #define CRPT_AES_STS_INBUFEMPTY_Msk      (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos)            /*!< CRPT AES_STS: INBUFEMPTY Mask          */
    295. 

  295. 

  296. #define CRPT_AES_STS_INBUFFULL_Pos       (9)                                               /*!< CRPT AES_STS: INBUFFULL Position       */
    297. 

  297. #define CRPT_AES_STS_INBUFFULL_Msk       (0x1ul << CRPT_AES_STS_INBUFFULL_Pos)             /*!< CRPT AES_STS: INBUFFULL Mask           */
    298. 

  298. 

  299. #define CRPT_AES_STS_INBUFERR_Pos        (10)                                              /*!< CRPT AES_STS: INBUFERR Position        */
    300. 

  300. #define CRPT_AES_STS_INBUFERR_Msk        (0x1ul << CRPT_AES_STS_INBUFERR_Pos)              /*!< CRPT AES_STS: INBUFERR Mask            */
    301. 

  301. 

  302. #define CRPT_AES_STS_CNTERR_Pos          (12)                                              /*!< CRPT AES_STS: CNTERR Position          */
    303. 

  303. #define CRPT_AES_STS_CNTERR_Msk          (0x1ul << CRPT_AES_STS_CNTERR_Pos)                /*!< CRPT AES_STS: CNTERR Mask              */
    304. 

  304. 

  305. #define CRPT_AES_STS_OUTBUFEMPTY_Pos     (16)                                              /*!< CRPT AES_STS: OUTBUFEMPTY Position     */
    306. 

  306. #define CRPT_AES_STS_OUTBUFEMPTY_Msk     (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos)           /*!< CRPT AES_STS: OUTBUFEMPTY Mask         */
    307. 

  307. 

  308. #define CRPT_AES_STS_OUTBUFFULL_Pos      (17)                                              /*!< CRPT AES_STS: OUTBUFFULL Position      */
    309. 

  309. #define CRPT_AES_STS_OUTBUFFULL_Msk      (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos)            /*!< CRPT AES_STS: OUTBUFFULL Mask          */
    310. 

  310. 

  311. #define CRPT_AES_STS_OUTBUFERR_Pos       (18)                                              /*!< CRPT AES_STS: OUTBUFERR Position       */
    312. 

  312. #define CRPT_AES_STS_OUTBUFERR_Msk       (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos)             /*!< CRPT AES_STS: OUTBUFERR Mask           */
    313. 

  313. 

  314. #define CRPT_AES_STS_BUSERR_Pos          (20)                                              /*!< CRPT AES_STS: BUSERR Position          */
    315. 

  315. #define CRPT_AES_STS_BUSERR_Msk          (0x1ul << CRPT_AES_STS_BUSERR_Pos)                /*!< CRPT AES_STS: BUSERR Mask              */
    316. 

  316. 

  317. #define CRPT_TDES_CTL_START_Pos          (0)                                               /*!< CRPT TDES_CTL: START Position          */
    318. 

  318. #define CRPT_TDES_CTL_START_Msk          (0x1ul << CRPT_TDES_CTL_START_Pos)                /*!< CRPT TDES_CTL: START Mask              */
    319. 

  319. 

  320. #define CRPT_TDES_CTL_STOP_Pos           (1)                                               /*!< CRPT TDES_CTL: STOP Position           */
    321. 

  321. #define CRPT_TDES_CTL_STOP_Msk           (0x1ul << CRPT_TDES_CTL_STOP_Pos)                 /*!< CRPT TDES_CTL: STOP Mask               */
    322. 

  322. 

  323. #define CRPT_TDES_CTL_TMODE_Pos          (2)                                               /*!< CRPT TDES_CTL: TMODE Position          */
    324. 

  324. #define CRPT_TDES_CTL_TMODE_Msk          (0x1ul << CRPT_TDES_CTL_TMODE_Pos)                /*!< CRPT TDES_CTL: TMODE Mask              */
    325. 

  325. 

  326. #define CRPT_TDES_CTL_3KEYS_Pos          (3)                                               /*!< CRPT TDES_CTL: 3KEYS Position          */
    327. 

  327. #define CRPT_TDES_CTL_3KEYS_Msk          (0x1ul << CRPT_TDES_CTL_3KEYS_Pos)                /*!< CRPT TDES_CTL: 3KEYS Mask              */
    328. 

  328. 

  329. #define CRPT_TDES_CTL_DMALAST_Pos        (5)                                               /*!< CRPT TDES_CTL: DMALAST Position        */
    330. 

  330. #define CRPT_TDES_CTL_DMALAST_Msk        (0x1ul << CRPT_TDES_CTL_DMALAST_Pos)              /*!< CRPT TDES_CTL: DMALAST Mask            */
    331. 

  331. 

  332. #define CRPT_TDES_CTL_DMACSCAD_Pos       (6)                                               /*!< CRPT TDES_CTL: DMACSCAD Position       */
    333. 

  333. #define CRPT_TDES_CTL_DMACSCAD_Msk       (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos)             /*!< CRPT TDES_CTL: DMACSCAD Mask           */
    334. 

  334. 

  335. #define CRPT_TDES_CTL_DMAEN_Pos          (7)                                               /*!< CRPT TDES_CTL: DMAEN Position          */
    336. 

  336. #define CRPT_TDES_CTL_DMAEN_Msk          (0x1ul << CRPT_TDES_CTL_DMAEN_Pos)                /*!< CRPT TDES_CTL: DMAEN Mask              */
    337. 

  337. 

  338. #define CRPT_TDES_CTL_OPMODE_Pos         (8)                                               /*!< CRPT TDES_CTL: OPMODE Position         */
    339. 

  339. #define CRPT_TDES_CTL_OPMODE_Msk         (0x7ul << CRPT_TDES_CTL_OPMODE_Pos)               /*!< CRPT TDES_CTL: OPMODE Mask             */
    340. 

  340. 

  341. #define CRPT_TDES_CTL_ENCRPT_Pos         (16)                                              /*!< CRPT TDES_CTL: ENCRPT Position         */
    342. 

  342. #define CRPT_TDES_CTL_ENCRPT_Msk         (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos)               /*!< CRPT TDES_CTL: ENCRPT Mask             */
    343. 

  343. 

  344. #define CRPT_TDES_CTL_BLKSWAP_Pos        (21)                                              /*!< CRPT TDES_CTL: BLKSWAP Position        */
    345. 

  345. #define CRPT_TDES_CTL_BLKSWAP_Msk        (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos)              /*!< CRPT TDES_CTL: BLKSWAP Mask            */
    346. 

  346. 

  347. #define CRPT_TDES_CTL_OUTSWAP_Pos        (22)                                              /*!< CRPT TDES_CTL: OUTSWAP Position        */
    348. 

  348. #define CRPT_TDES_CTL_OUTSWAP_Msk        (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos)              /*!< CRPT TDES_CTL: OUTSWAP Mask            */
    349. 

  349. 

  350. #define CRPT_TDES_CTL_INSWAP_Pos         (23)                                              /*!< CRPT TDES_CTL: INSWAP Position         */
    351. 

  351. #define CRPT_TDES_CTL_INSWAP_Msk         (0x1ul << CRPT_TDES_CTL_INSWAP_Pos)               /*!< CRPT TDES_CTL: INSWAP Mask             */
    352. 

  352. 

  353. #define CRPT_TDES_CTL_CHANNEL_Pos        (24)                                              /*!< CRPT TDES_CTL: CHANNEL Position        */
    354. 

  354. #define CRPT_TDES_CTL_CHANNEL_Msk        (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos)              /*!< CRPT TDES_CTL: CHANNEL Mask            */
    355. 

  355. 

  356. #define CRPT_TDES_CTL_KEYUNPRT_Pos       (26)                                              /*!< CRPT TDES_CTL: KEYUNPRT Position       */
    357. 

  357. #define CRPT_TDES_CTL_KEYUNPRT_Msk       (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos)            /*!< CRPT TDES_CTL: KEYUNPRT Mask           */
    358. 

  358. 

  359. #define CRPT_TDES_CTL_KEYPRT_Pos         (31)                                              /*!< CRPT TDES_CTL: KEYPRT Position         */
    360. 

  360. #define CRPT_TDES_CTL_KEYPRT_Msk         (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos)               /*!< CRPT TDES_CTL: KEYPRT Mask             */
    361. 

  361. 

  362. #define CRPT_TDES_STS_BUSY_Pos           (0)                                               /*!< CRPT TDES_STS: BUSY Position           */
    363. 

  363. #define CRPT_TDES_STS_BUSY_Msk           (0x1ul << CRPT_TDES_STS_BUSY_Pos)                 /*!< CRPT TDES_STS: BUSY Mask               */
    364. 

  364. 

  365. #define CRPT_TDES_STS_INBUFEMPTY_Pos     (8)                                               /*!< CRPT TDES_STS: INBUFEMPTY Position     */
    366. 

  366. #define CRPT_TDES_STS_INBUFEMPTY_Msk     (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos)           /*!< CRPT TDES_STS: INBUFEMPTY Mask         */
    367. 

  367. 

  368. #define CRPT_TDES_STS_INBUFFULL_Pos      (9)                                               /*!< CRPT TDES_STS: INBUFFULL Position      */
    369. 

  369. #define CRPT_TDES_STS_INBUFFULL_Msk      (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos)            /*!< CRPT TDES_STS: INBUFFULL Mask          */
    370. 

  370. 

  371. #define CRPT_TDES_STS_INBUFERR_Pos       (10)                                              /*!< CRPT TDES_STS: INBUFERR Position       */
    372. 

  372. #define CRPT_TDES_STS_INBUFERR_Msk       (0x1ul << CRPT_TDES_STS_INBUFERR_Pos)             /*!< CRPT TDES_STS: INBUFERR Mask           */
    373. 

  373. 

  374. #define CRPT_TDES_STS_OUTBUFEMPTY_Pos    (16)                                              /*!< CRPT TDES_STS: OUTBUFEMPTY Position    */
    375. 

  375. #define CRPT_TDES_STS_OUTBUFEMPTY_Msk    (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos)          /*!< CRPT TDES_STS: OUTBUFEMPTY Mask        */
    376. 

  376. 

  377. #define CRPT_TDES_STS_OUTBUFFULL_Pos     (17)                                              /*!< CRPT TDES_STS: OUTBUFFULL Position     */
    378. 

  378. #define CRPT_TDES_STS_OUTBUFFULL_Msk     (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos)           /*!< CRPT TDES_STS: OUTBUFFULL Mask         */
    379. 

  379. 

  380. #define CRPT_TDES_STS_OUTBUFERR_Pos      (18)                                              /*!< CRPT TDES_STS: OUTBUFERR Position      */
    381. 

  381. #define CRPT_TDES_STS_OUTBUFERR_Msk      (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos)            /*!< CRPT TDES_STS: OUTBUFERR Mask          */
    382. 

  382. 

  383. #define CRPT_TDES_STS_BUSERR_Pos         (20)                                              /*!< CRPT TDES_STS: BUSERR Position         */
    384. 

  384. #define CRPT_TDES_STS_BUSERR_Msk         (0x1ul << CRPT_TDES_STS_BUSERR_Pos)               /*!< CRPT TDES_STS: BUSERR Mask             */
    385. 

  385. 

  386. #define CRPT_HMAC_CTL_START_Pos          (0)                                               /*!< CRPT HMAC_CTL: START Position           */
    387. 

  387. #define CRPT_HMAC_CTL_START_Msk          (0x1ul << CRPT_HMAC_CTL_START_Pos)                /*!< CRPT HMAC_CTL: START Mask               */
    388. 

  388. 

  389. #define CRPT_HMAC_CTL_STOP_Pos           (1)                                               /*!< CRPT HMAC_CTL: STOP Position            */
    390. 

  390. #define CRPT_HMAC_CTL_STOP_Msk           (0x1ul << CRPT_HMAC_CTL_STOP_Pos)                 /*!< CRPT HMAC_CTL: STOP Mask                */
    391. 

  391. 

  392. #define CRPT_HMAC_CTL_HMACEN_Pos         (4)                                               /*!< CRPT HMAC_CTL: HMACEN Position          */
    393. 

  393. #define CRPT_HMAC_CTL_HMACEN_Msk         (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos)               /*!< CRPT HMAC_CTL: HMACEN Mask              */
    394. 

  394. 

  395. #define CRPT_HMAC_CTL_DMALAST_Pos        (5)                                               /*!< CRPT HMAC_CTL: DMALAST Position         */
    396. 

  396. #define CRPT_HMAC_CTL_DMALAST_Msk        (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos)              /*!< CRPT HMAC_CTL: DMALAST Mask             */
    397. 

  397. 

  398. #define CRPT_HMAC_CTL_DMAEN_Pos          (7)                                               /*!< CRPT HMAC_CTL: DMAEN Position           */
    399. 

  399. #define CRPT_HMAC_CTL_DMAEN_Msk          (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos)                /*!< CRPT HMAC_CTL: DMAEN Mask               */
    400. 

  400. 

  401. #define CRPT_HMAC_CTL_OPMODE_Pos         (8)                                               /*!< CRPT HMAC_CTL: OPMODE Position          */
    402. 

  402. #define CRPT_HMAC_CTL_OPMODE_Msk         (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos)               /*!< CRPT HMAC_CTL: OPMODE Mask              */
    403. 

  403. 

  404. #define CRPT_HMAC_CTL_COMPEN_Pos         (15)                                              /*!< CRPT HMAC_CTL: COMPEN Position          */
    405. 

  405. #define CRPT_HMAC_CTL_COMPEN_Msk         (0x1ul << CRPT_HMAC_CTL_COMPEN_Pos)               /*!< CRPT HMAC_CTL: COMPEN Mask              */
    406. 

  406. 

  407. #define CRPT_HMAC_CTL_OUTSWAP_Pos        (22)                                              /*!< CRPT HMAC_CTL: OUTSWAP Position         */
    408. 

  408. #define CRPT_HMAC_CTL_OUTSWAP_Msk        (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos)              /*!< CRPT HMAC_CTL: OUTSWAP Mask             */
    409. 

  409. 

  410. #define CRPT_HMAC_CTL_INSWAP_Pos         (23)                                              /*!< CRPT HMAC_CTL: INSWAP Position          */
    411. 

  411. #define CRPT_HMAC_CTL_INSWAP_Msk         (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos)               /*!< CRPT HMAC_CTL: INSWAP Mask              */
    412. 

  412. 

  413. #define CRPT_HMAC_STS_BUSY_Pos           (0)                                               /*!< CRPT HMAC_STS: BUSY Position            */
    414. 

  414. #define CRPT_HMAC_STS_BUSY_Msk           (0x1ul << CRPT_HMAC_STS_BUSY_Pos)                 /*!< CRPT HMAC_STS: BUSY Mask                */
    415. 

  415. 

  416. #define CRPT_HMAC_STS_DMABUSY_Pos        (1)                                               /*!< CRPT HMAC_STS: DMABUSY Position         */
    417. 

  417. #define CRPT_HMAC_STS_DMABUSY_Msk        (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos)              /*!< CRPT HMAC_STS: DMABUSY Mask             */
    418. 

  418. 

  419. #define CRPT_HMAC_STS_DMAERR_Pos         (8)                                               /*!< CRPT HMAC_STS: DMAERR Position          */
    420. 

  420. #define CRPT_HMAC_STS_DMAERR_Msk         (0x1ul << CRPT_HMAC_STS_DMAERR_Pos)               /*!< CRPT HMAC_STS: DMAERR Mask              */
    421. 

  421. 

  422. #define CRPT_HMAC_STS_COMPRES_Pos        (15)                                              /*!< CRPT HMAC_STS: COMPRES Position         */
    423. 

  423. #define CRPT_HMAC_STS_COMPRES_Msk        (0x1ul << CRPT_HMAC_STS_COMPRES_Pos)              /*!< CRPT HMAC_STS: COMPRES Mask             */
    424. 

  424. 

  425. #define CRPT_HMAC_STS_DATINREQ_Pos       (16)                                              /*!< CRPT HMAC_STS: DATINREQ Position        */
    426. 

  426. #define CRPT_HMAC_STS_DATINREQ_Msk       (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos)             /*!< CRPT HMAC_STS: DATINREQ Mask            */
    427. 

  427. 

  428. /// @endcond HIDDEN_SYMBOLS
    429. 

  429. 

  430. 

  431. 

  432. /** @addtogroup N9H30_CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants
    433. 

  433.   @{
    434. 

  434. */
    435. 

  435. 

  436. #define PRNG_KEY_SIZE_64        0       /*!< Select to generate 64-bit random key    \hideinitializer */
    437. 

  437. #define PRNG_KEY_SIZE_128       1       /*!< Select to generate 128-bit random key   \hideinitializer */
    438. 

  438. #define PRNG_KEY_SIZE_192       2       /*!< Select to generate 192-bit random key   \hideinitializer */
    439. 

  439. #define PRNG_KEY_SIZE_256       3       /*!< Select to generate 256-bit random key   \hideinitializer */
    440. 

  440. 

  441. #define PRNG_SEED_CONT          0       /*!< PRNG using current seed                 \hideinitializer */
    442. 

  442. #define PRNG_SEED_RELOAD        1       /*!< PRNG reload new seed                    \hideinitializer */
    443. 

  443. 

  444. #define AES_KEY_SIZE_128        0       /*!< AES select 128-bit key length           \hideinitializer */
    445. 

  445. #define AES_KEY_SIZE_192        1       /*!< AES select 192-bit key length           \hideinitializer */
    446. 

  446. #define AES_KEY_SIZE_256        2       /*!< AES select 256-bit key length           \hideinitializer */
    447. 

  447. 

  448. #define AES_MODE_ECB            0       /*!< AES select ECB mode                     \hideinitializer */
    449. 

  449. #define AES_MODE_CBC            1       /*!< AES select CBC mode                     \hideinitializer */
    450. 

  450. #define AES_MODE_CFB            2       /*!< AES select CFB mode                     \hideinitializer */
    451. 

  451. #define AES_MODE_OFB            3       /*!< AES select OFB mode                     \hideinitializer */
    452. 

  452. #define AES_MODE_CTR            4       /*!< AES select CTR mode                     \hideinitializer */
    453. 

  453. #define AES_MODE_CBC_CS1        0x10    /*!< AES select CBC CS1 mode                 \hideinitializer */
    454. 

  454. #define AES_MODE_CBC_CS2        0x11    /*!< AES select CBC CS2 mode                 \hideinitializer */
    455. 

  455. #define AES_MODE_CBC_CS3        0x12    /*!< AES select CBC CS3 mode                 \hideinitializer */
    456. 

  456. 

  457. #define AES_NO_SWAP             0       /*!< AES do not swap input and output data   \hideinitializer */
    458. 

  458. #define AES_OUT_SWAP            1       /*!< AES swap output data                    \hideinitializer */
    459. 

  459. #define AES_IN_SWAP             2       /*!< AES swap input data                     \hideinitializer */
    460. 

  460. #define AES_IN_OUT_SWAP         3       /*!< AES swap both input and output data     \hideinitializer */
    461. 

  461. 

  462. #define DES_MODE_ECB            0x000   /*!< DES select ECB mode                     \hideinitializer */
    463. 

  463. #define DES_MODE_CBC            0x100   /*!< DES select CBC mode                     \hideinitializer */
    464. 

  464. #define DES_MODE_CFB            0x200   /*!< DES select CFB mode                     \hideinitializer */
    465. 

  465. #define DES_MODE_OFB            0x300   /*!< DES select OFB mode                     \hideinitializer */
    466. 

  466. #define DES_MODE_CTR            0x400   /*!< DES select CTR mode                     \hideinitializer */
    467. 

  467. #define TDES_MODE_ECB           0x004   /*!< TDES select ECB mode                    \hideinitializer */
    468. 

  468. #define TDES_MODE_CBC           0x104   /*!< TDES select CBC mode                    \hideinitializer */
    469. 

  469. #define TDES_MODE_CFB           0x204   /*!< TDES select CFB mode                    \hideinitializer */
    470. 

  470. #define TDES_MODE_OFB           0x304   /*!< TDES select OFB mode                    \hideinitializer */
    471. 

  471. #define TDES_MODE_CTR           0x404   /*!< TDES select CTR mode                    \hideinitializer */
    472. 

  472. 

  473. #define TDES_NO_SWAP            0       /*!< TDES do not swap data                       \hideinitializer */
    474. 

  474. #define TDES_WHL_SWAP           1       /*!< TDES swap high-low word                     \hideinitializer */
    475. 

  475. #define TDES_OUT_SWAP           2       /*!< TDES swap output data                       \hideinitializer */
    476. 

  476. #define TDES_OUT_WHL_SWAP       3       /*!< TDES swap output data and high-low word     \hideinitializer */
    477. 

  477. #define TDES_IN_SWAP            4       /*!< TDES swap input data                        \hideinitializer */
    478. 

  478. #define TDES_IN_WHL_SWAP        5       /*!< TDES swap input data and high-low word      \hideinitializer */
    479. 

  479. #define TDES_IN_OUT_SWAP        6       /*!< TDES swap both input and output data        \hideinitializer */
    480. 

  480. #define TDES_IN_OUT_WHL_SWAP    7       /*!< TDES swap input, output and high-low word   \hideinitializer */
    481. 

  481. 

  482. #define SHA_MODE_SHA1           0       /*!< SHA select SHA-1 160-bit                \hideinitializer */
    483. 

  483. #define SHA_MODE_SHA224         5       /*!< SHA select SHA-224 224-bit              \hideinitializer */
    484. 

  484. #define SHA_MODE_SHA256         4       /*!< SHA select SHA-256 256-bit              \hideinitializer */
    485. 

  485. #define SHA_MODE_SHA384         7       /*!< SHA select SHA-384 384-bit              \hideinitializer */
    486. 

  486. #define SHA_MODE_SHA512         6       /*!< SHA select SHA-512 512-bit              \hideinitializer */
    487. 

  487. 

  488. #define SHA_NO_SWAP             0       /*!< SHA do not swap input and output data   \hideinitializer */
    489. 

  489. #define SHA_OUT_SWAP            1       /*!< SHA swap output data                    \hideinitializer */
    490. 

  490. #define SHA_IN_SWAP             2       /*!< SHA swap input data                     \hideinitializer */
    491. 

  491. #define SHA_IN_OUT_SWAP         3       /*!< SHA swap both input and output data     \hideinitializer */
    492. 

  492. 

  493. #define CRYPTO_DMA_FIRST        0x4     /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */
    494. 

  494. #define CRYPTO_DMA_ONE_SHOT     0x5     /*!< Do one shot encrypt/decrypt with DMA      \hideinitializer */
    495. 

  495. #define CRYPTO_DMA_CONTINUE     0x6     /*!< Do one continuous encrypt/decrypt with DMA \hideinitializer */
    496. 

  496. #define CRYPTO_DMA_LAST         0x7     /*!< Do last encrypt/decrypt with DMA          \hideinitializer */
    497. 

  497. 

  498. /*@}*/ /* end of group N9H30_CRYPTO_EXPORTED_CONSTANTS */
    499. 

  499. 

  500. 

  501. 

  502. 

  503. /** @addtogroup N9H30_CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
    504. 

  504.   @{
    505. 

  505. */
    506. 

  506. 

  507. /*----------------------------------------------------------------------------------------------*/
    508. 

  508. /*  Macros                                                                                      */
    509. 

  509. /*----------------------------------------------------------------------------------------------*/
    510. 

  510. 

  511. /**
    512. 

  512.   * @brief This macro enables PRNG interrupt.
    513. 

  513.   * @return None
    514. 

  514.   * \hideinitializer
    515. 

  515.   */
    516. 

  516. #define PRNG_ENABLE_INT()       (CRPT->INTEN |= CRPT_INTEN_PRNGIEN_Msk)
    517. 

  517. 

  518. /**
    519. 

  519.   * @brief This macro disables PRNG interrupt.
    520. 

  520.   * @return None
    521. 

  521.   * \hideinitializer
    522. 

  522.   */
    523. 

  523. #define PRNG_DISABLE_INT()      (CRPT->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)
    524. 

  524. 

  525. /**
    526. 

  526.   * @brief This macro gets PRNG interrupt flag.
    527. 

  527.   * @return PRNG interrupt flag.
    528. 

  528.   * \hideinitializer
    529. 

  529.   */
    530. 

  530. #define PRNG_GET_INT_FLAG()     (CRPT->INTSTS & CRPT_INTSTS_PRNGIF_Msk)
    531. 

  531. 

  532. /**
    533. 

  533.   * @brief This macro clears PRNG interrupt flag.
    534. 

  534.   * @return None
    535. 

  535.   * \hideinitializer
    536. 

  536.   */
    537. 

  537. #define PRNG_CLR_INT_FLAG()     (CRPT->INTSTS = CRPT_INTSTS_PRNGIF_Msk)
    538. 

  538. 

  539. /**
    540. 

  540.   * @brief This macro enables AES interrupt.
    541. 

  541.   * @return None
    542. 

  542.   * \hideinitializer
    543. 

  543.   */
    544. 

  544. #define AES_ENABLE_INT()        (CRPT->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESERRIEN_Msk))
    545. 

  545. 

  546. /**
    547. 

  547.   * @brief This macro disables AES interrupt.
    548. 

  548.   * @return None
    549. 

  549.   * \hideinitializer
    550. 

  550.   */
    551. 

  551. #define AES_DISABLE_INT()       (CRPT->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESERRIEN_Msk))
    552. 

  552. 

  553. /**
    554. 

  554.   * @brief This macro gets AES interrupt flag.
    555. 

  555.   * @return AES interrupt flag.
    556. 

  556.   * \hideinitializer
    557. 

  557.   */
    558. 

  558. #define AES_GET_INT_FLAG()      (CRPT->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESERRIF_Msk))
    559. 

  559. 

  560. /**
    561. 

  561.   * @brief This macro clears AES interrupt flag.
    562. 

  562.   * @return None
    563. 

  563.   * \hideinitializer
    564. 

  564.   */
    565. 

  565. #define AES_CLR_INT_FLAG()      (CRPT->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESERRIF_Msk))
    566. 

  566. 

  567. /**
    568. 

  568.   * @brief This macro enables AES key protection.
    569. 

  569.   * @return None
    570. 

  570.   * \hideinitializer
    571. 

  571.   */
    572. 

  572. #define AES_ENABLE_KEY_PROTECT()  (CRPT->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)
    573. 

  573. 

  574. /**
    575. 

  575.   * @brief This macro disables AES key protection.
    576. 

  576.   * @return None
    577. 

  577.   * \hideinitializer
    578. 

  578.   */
    579. 

  579. #define AES_DISABLE_KEY_PROTECT() (CRPT->AES_CTL = (CRPT->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16<<CRPT_AES_CTL_KEYUNPRT_Pos))
    580. 

  580. 

  581. /**
    582. 

  582.   * @brief This macro enables TDES interrupt.
    583. 

  583.   * @return None
    584. 

  584.   * \hideinitializer
    585. 

  585.   */
    586. 

  586. #define TDES_ENABLE_INT()       (CRPT->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESERRIEN_Msk))
    587. 

  587. 

  588. /**
    589. 

  589.   * @brief This macro disables TDES interrupt.
    590. 

  590.   * @return None
    591. 

  591.   * \hideinitializer
    592. 

  592.   */
    593. 

  593. #define TDES_DISABLE_INT()      (CRPT->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESERRIEN_Msk))
    594. 

  594. 

  595. /**
    596. 

  596.   * @brief This macro gets TDES interrupt flag.
    597. 

  597.   * @return TDES interrupt flag.
    598. 

  598.   * \hideinitializer
    599. 

  599.   */
    600. 

  600. #define TDES_GET_INT_FLAG()     (CRPT->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESERRIF_Msk))
    601. 

  601. 

  602. /**
    603. 

  603.   * @brief This macro clears TDES interrupt flag.
    604. 

  604.   * @return None
    605. 

  605.   * \hideinitializer
    606. 

  606.   */
    607. 

  607. #define TDES_CLR_INT_FLAG()     (CRPT->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESERRIF_Msk))
    608. 

  608. 

  609. /**
    610. 

  610.   * @brief This macro enables TDES key protection.
    611. 

  611.   * @return None
    612. 

  612.   * \hideinitializer
    613. 

  613.   */
    614. 

  614. #define TDES_ENABLE_KEY_PROTECT()  (CRPT->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk)
    615. 

  615. 

  616. /**
    617. 

  617.   * @brief This macro disables TDES key protection.
    618. 

  618.   * @return None
    619. 

  619.   * \hideinitializer
    620. 

  620.   */
    621. 

  621. #define TDES_DISABLE_KEY_PROTECT() (CRPT->TDES_CTL = (CRPT->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16<<CRPT_TDES_CTL_KEYUNPRT_Pos))
    622. 

  622. 

  623. /**
    624. 

  624.   * @brief This macro enables SHA interrupt.
    625. 

  625.   * @return None
    626. 

  626.   * \hideinitializer
    627. 

  627.   */
    628. 

  628. #define SHA_ENABLE_INT()        (CRPT->INTEN |= (CRPT_INTEN_SHAIEN_Msk|CRPT_INTEN_SHAERRIEN_Msk))
    629. 

  629. 

  630. /**
    631. 

  631.   * @brief This macro disables SHA interrupt.
    632. 

  632.   * @return None
    633. 

  633.   * \hideinitializer
    634. 

  634.   */
    635. 

  635. #define SHA_DISABLE_INT()       (CRPT->INTEN &= ~(CRPT_INTEN_SHAIEN_Msk|CRPT_INTEN_SHAERRIEN_Msk))
    636. 

  636. 

  637. /**
    638. 

  638.   * @brief This macro gets SHA interrupt flag.
    639. 

  639.   * @return SHA interrupt flag.
    640. 

  640.   * \hideinitializer
    641. 

  641.   */
    642. 

  642. #define SHA_GET_INT_FLAG()      (CRPT->INTSTS & (CRPT_INTSTS_SHAIF_Msk|CRPT_INTSTS_SHAERRIF_Msk))
    643. 

  643. 

  644. /**
    645. 

  645.   * @brief This macro clears SHA interrupt flag.
    646. 

  646.   * @return None
    647. 

  647.   * \hideinitializer
    648. 

  648.   */
    649. 

  649. #define SHA_CLR_INT_FLAG()      (CRPT->INTSTS = (CRPT_INTSTS_SHAIF_Msk|CRPT_INTSTS_SHAERRIF_Msk))
    650. 

  650. 

  651. 

  652. 

  653. /*---------------------------------------------------------------------------------------------------------*/
    654. 

  654. /*  Functions                                                                                      */
    655. 

  655. /*---------------------------------------------------------------------------------------------------------*/
    656. 

  656. 

  657. void PRNG_Open(uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);
    658. 

  658. void PRNG_Start(void);
    659. 

  659. void PRNG_Read(uint32_t u32RandKey[]);
    660. 

  660. void AES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
    661. 

  661. void AES_Start(int32_t u32Channel, uint32_t u32DMAMode);
    662. 

  662. void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
    663. 

  663. void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]);
    664. 

  664. void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
    665. 

  665. void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType);
    666. 

  666. void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode);
    667. 

  667. void TDES_SetKey(uint32_t u32Channel, uint32_t au32Keys[3][2]);
    668. 

  668. void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL);
    669. 

  669. void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
    670. 

  670. void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType, int hmac_key_len);
    671. 

  671. void SHA_Start(uint32_t u32DMAMode);
    672. 

  672. void SHA_SetDMATransfer(uint32_t u32SrcAddr, uint32_t u32TransCnt);
    673. 

  673. void SHA_Read(uint32_t u32Digest[]);
    674. 

  674. 

  675. 

  676. /*@}*/ /* end of group N9H30_CRYPTO_EXPORTED_FUNCTIONS */
    677. 

  677. 

  678. /*@}*/ /* end of group N9H30_CRYPTO_Driver */
    679. 

  679. 

  680. /*@}*/ /* end of group N9H30_Device_Driver */
    681. 

  681. 

  682. #ifdef __cplusplus
    683. 

  683. }
    684. 

  684. #endif
    685. 

  685. 

  686. #endif  // __NU_CRYPTO_H__
    687. 

  687. 

  688. /*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
    689. 

  689.