drv_sys.h 5.0 KB

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  1. #ifndef __PLAT_INTERRUPT_H__
  2. #define __PLAT_INTERRUPT_H__
  3. #include "rthw.h"
  4. #include <rtconfig.h>
  5. #if defined(BSP_USING_MMU)
  6. #include "mmu.h"
  7. #define NONCACHEABLE BIT31
  8. #else
  9. #define NONCACHEABLE 0
  10. #endif
  11. #define sysprintf rt_kprintf
  12. typedef enum
  13. {
  14. SYS_IPRST_NA = -1,
  15. /* SYS_AHBIPRST, SYS_BA + 0x060 */
  16. CHIPRST,
  17. AHBIPRST_Reserved_1,
  18. CPURST,
  19. GDMARST,
  20. AHBIPRST_Reserved_4,
  21. AHBIPRST_Reserved_5,
  22. AHBIPRST_Reserved_6,
  23. AHBIPRST_Reserved_7,
  24. I2SRST,
  25. LCDRST,
  26. CAPRST,
  27. AHBIPRST_Reserved_11,
  28. AHBIPRST_Reserved_12,
  29. AHBIPRST_Reserved_13,
  30. AHBIPRST_Reserved_14,
  31. AHBIPRST_Reserved_15,
  32. EMAC0RST,
  33. EMAC1RST,
  34. USBHRST,
  35. USBDRST,
  36. FMIRST,
  37. GE2DRST,
  38. JPEGRST,
  39. CRYPTORST,
  40. SDIORST,
  41. AHBIPRST_Reserved_25,
  42. AHBIPRST_Reserved_26,
  43. AHBIPRST_Reserved_27,
  44. AHBIPRST_Reserved_28,
  45. AHBIPRST_Reserved_29,
  46. AHBIPRST_Reserved_30,
  47. AHBIPRST_Reserved_31,
  48. /* SYS_APBIPRST0, SYS_BA + 0x064 */
  49. APBIPRST0_Reserved_0,
  50. APBIPRST0_Reserved_1,
  51. APBIPRST0_Reserved_2,
  52. GPIORST,
  53. ETIMER0RST,
  54. ETIMER1RST,
  55. ETIMER2RST,
  56. ETIMER3RST,
  57. TIMER0RST,
  58. TIMER1RST,
  59. TIMER2RST,
  60. TIMER3RST,
  61. TIMER4RST,
  62. APBIPRST0_Reserved_13,
  63. APBIPRST0_Reserved_14,
  64. APBIPRST0_Reserved_15,
  65. UART0RST,
  66. UART1RST,
  67. UART2RST,
  68. UART3RST,
  69. UART4RST,
  70. UART5RST,
  71. UART6RST,
  72. UART7RST,
  73. UART8RST,
  74. UART9RST,
  75. UART10RST,
  76. APBIPRST0_Reserved_27,
  77. APBIPRST0_Reserved_28,
  78. APBIPRST0_Reserved_29,
  79. APBIPRST0_Reserved_30,
  80. APBIPRST0_Reserved_31,
  81. /* SYS_APBIPRST1, SYS_BA + 0x068 */
  82. I2C0RST,
  83. I2C1RST,
  84. APBIPRST1_Reserved_2,
  85. APBIPRST1_Reserved_3,
  86. SPI0RST,
  87. SPI1RST,
  88. APBIPRST1_Reserved_6,
  89. APBIPRST1_Reserved_7,
  90. CAN0RST,
  91. CAN1RST,
  92. APBIPRST1_Reserved_10,
  93. APBIPRST1_Reserved_11,
  94. SMC0RST,
  95. SMC1RST,
  96. APBIPRST1_Reserved_14,
  97. APBIPRST1_Reserved_15,
  98. APBIPRST1_Reserved_16,
  99. APBIPRST1_Reserved_17,
  100. APBIPRST1_Reserved_18,
  101. APBIPRST1_Reserved_19,
  102. APBIPRST1_Reserved_20,
  103. APBIPRST1_Reserved_21,
  104. APBIPRST1_Reserved_22,
  105. APBIPRST1_Reserved_23,
  106. ADCRST,
  107. APBIPRST1_Reserved_25,
  108. MTPCRST,
  109. PWMRST,
  110. APBIPRST1_Reserved_28,
  111. APBIPRST1_Reserved_29,
  112. APBIPRST1_Reserved_30,
  113. APBIPRST1_Reserved_31,
  114. SYS_IPRST_CNT
  115. } E_SYS_IPRST;
  116. typedef enum
  117. {
  118. SYS_IPCLK_NA = -1,
  119. /* CLK_HCLKEN, CLK_BA + 0x010 */
  120. CPUCKEN,
  121. HCLKCKEN,
  122. HCLK1CKEN,
  123. HCLK3CKEN,
  124. HCLK4CKEN,
  125. PCLKCKEN,
  126. HCLKEN_Reserved_6,
  127. TICCKEN,
  128. SRAMCKEN,
  129. EBICKEN,
  130. DDRCKEN,
  131. HCLKEN_Reserved_11,
  132. GDMACKEN,
  133. HCLKEN_Reserved_13,
  134. HCLKEN_Reserved_14,
  135. CKOCKEN,
  136. EMAC0CKEN,
  137. EMAC1CKEN,
  138. USBHCKEN,
  139. USBDCKEN,
  140. FMICKEN,
  141. NANDCKEN,
  142. EMMCCKEN,
  143. CRYPTOCKEN,
  144. I2SCKEN,
  145. LCDCKEN,
  146. CAPCKEN,
  147. SENSORCKEN,
  148. GE2DCKEN,
  149. JPEGCKEN,
  150. SDHCKEN,
  151. HCLKEN_Reserved_31,
  152. CLK_HCLKEN_END,
  153. /* CLK_BA+0x014 */
  154. /* CLK_PCLKEN0 CLK_BA+0x018 */
  155. CLK_PCLKEN0_BEGIN = CLK_HCLKEN_END + 32,
  156. WDTCKEN = CLK_PCLKEN0_BEGIN,
  157. WWDTCKEN,
  158. RTCCKEN,
  159. GPIOCKEN,
  160. ETIMER0CKEN,
  161. ETIMER1CKEN,
  162. ETIMER2CKEN,
  163. ETIMER3CKEN,
  164. TIMER0CKEN,
  165. TIMER1CKEN,
  166. TIMER2CKEN,
  167. TIMER3CKEN,
  168. TIMER4CKEN,
  169. PCLKEN0_Reserved_14,
  170. PCLKEN0_Reserved_15,
  171. PCLKEN0_Reserved_16,
  172. UART0CKEN,
  173. UART1CKEN,
  174. UART2CKEN,
  175. UART3CKEN,
  176. UART4CKEN,
  177. UART5CKEN,
  178. UART6CKEN,
  179. UART7CKEN,
  180. UART8CKEN,
  181. UART9CKEN,
  182. UART10CKEN,
  183. PCLKEN0_Reserved_27,
  184. PCLKEN0_Reserved_28,
  185. PCLKEN0_Reserved_29,
  186. PCLKEN0_Reserved_30,
  187. PCLKEN0_Reserved_31,
  188. /* CLK_PCLKEN1, CLK_BA + 0x01C */
  189. I2C0CKEN,
  190. I2C1CKEN,
  191. PCLKEN1_Reserved_2,
  192. PCLKEN1_Reserved_3,
  193. SPI0CKEN,
  194. SPI1CKEN,
  195. PCLKEN1_Reserved_6,
  196. PCLKEN1_Reserved_7,
  197. CAN0CKEN,
  198. CAN1CKEN,
  199. PCLKEN1_Reserved_10,
  200. PCLKEN1_Reserved_11,
  201. SMC0CKEN,
  202. SMC1CKEN,
  203. PCLKEN1_Reserved_14,
  204. PCLKEN1_Reserved_15,
  205. PCLKEN1_Reserved_16,
  206. PCLKEN1_Reserved_17,
  207. PCLKEN1_Reserved_18,
  208. PCLKEN1_Reserved_19,
  209. PCLKEN1_Reserved_20,
  210. PCLKEN1_Reserved_21,
  211. PCLKEN1_Reserved_22,
  212. PCLKEN1_Reserved_23,
  213. ADCCKEN,
  214. PCLKEN1_Reserved_25,
  215. MTPCCKEN,
  216. PWMCKEN,
  217. PCLKEN1_Reserved_28,
  218. PCLKEN1_Reserved_29,
  219. PCLKEN1_Reserved_30,
  220. PCLKEN1_Reserved_31,
  221. SYS_IPCLK_CNT
  222. } E_SYS_IPCLK;
  223. typedef enum
  224. {
  225. USB0_ID_DEVICE,
  226. USB0_ID_HOST,
  227. USB0_ID_CNT
  228. } E_SYS_USB0_ID;
  229. void rt_hw_interrupt_init(void);
  230. void rt_hw_interrupt_set_priority(int vector, int priority);
  231. void rt_hw_interrupt_set_type(int vector, int type);
  232. rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
  233. void rt_hw_systick_init(void);
  234. void nu_clock_base_init(void);
  235. void nu_systick_udelay(uint32_t delay_us);
  236. void nu_sys_ip_reset(E_SYS_IPRST eIPRstIdx);
  237. void nu_sys_ipclk_enable(E_SYS_IPCLK eIPClkIdx);
  238. void nu_sys_ipclk_disable(E_SYS_IPCLK eIPClkIdx);
  239. E_SYS_USB0_ID nu_sys_usb0_role(void);
  240. #endif