hal_pl330.h 6.8 KB

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  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
  4. */
  5. #include "hal_conf.h"
  6. #ifdef HAL_PL330_MODULE_ENABLED
  7. /** @addtogroup RK_HAL_Driver
  8. * @{
  9. */
  10. /** @addtogroup PL330
  11. * @{
  12. */
  13. #ifndef _HAL_PL330_H
  14. #define _HAL_PL330_H
  15. #include "hal_def.h"
  16. /** @defgroup PL330_Exported_Definition_Group1 Basic Definition
  17. * @{
  18. */
  19. /***************************** MACRO Definition ******************************/
  20. /** PL330 status */
  21. #define PL330_STATE_STOPPED HAL_BIT(0)
  22. #define PL330_STATE_EXECUTING HAL_BIT(1)
  23. #define PL330_STATE_WFE HAL_BIT(2)
  24. #define PL330_STATE_FAULTING HAL_BIT(3)
  25. #define PL330_STATE_COMPLETING HAL_BIT(4)
  26. #define PL330_STATE_WFP HAL_BIT(5)
  27. #define PL330_STATE_KILLING HAL_BIT(6)
  28. #define PL330_STATE_FAULT_COMPLETE HAL_BIT(7)
  29. #define PL330_STATE_CACHEMISS HAL_BIT(8)
  30. #define PL330_STATE_UPDTPC HAL_BIT(9)
  31. #define PL330_STATE_ATBARRIER HAL_BIT(10)
  32. #define PL330_STATE_QUEUEBUSY HAL_BIT(11)
  33. #define PL330_STATE_INVALID HAL_BIT(15)
  34. #define PL330_STABLE_STATES \
  35. (PL330_STATE_STOPPED | PL330_STATE_EXECUTING | PL330_STATE_WFE | \
  36. PL330_STATE_FAULTING)
  37. #define PL330_MAX_CHAN 8
  38. #define PL330_MAX_IRQS 32
  39. #define PL330_MAX_PERI 32
  40. #define PL330_MAX_BURST 16
  41. /*
  42. * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
  43. * at 1byte/burst for P<->M and M<->M respectively.
  44. * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
  45. * should be enough for P<->M and M<->M respectively.
  46. */
  47. #define MCODE_BUFF_PER_REQ 256
  48. #define PL330_MAX_CHAN_BUFS 2
  49. #define PL330_CHAN_BUF_LEN 128
  50. #define PL330_CHANNELS_PER_DEV 8
  51. #define PL330_NR_IRQS 2
  52. /***************************** Structure Definition **************************/
  53. /** enum PL330_CACHECTRL - pl330 cache control */
  54. typedef enum {
  55. CCTRL0, /**< Noncacheable and nonbufferable */
  56. CCTRL1, /**< Bufferable only */
  57. CCTRL2, /**< Cacheable, but do not allocate */
  58. CCTRL3, /**< Cacheable and bufferable, but do not allocate */
  59. INVALID1, /**< AWCACHE = 0x1000 */
  60. INVALID2,
  61. CCTRL6, /**< Cacheable write-through, allocate on writes only */
  62. CCTRL7, /**< Cacheable write-back, allocate on writes only */
  63. } ePL330_CACHECTRL;
  64. /** enum PL330_BYTESWAP - pl330 byte swap control */
  65. typedef enum {
  66. SWAP_NO,
  67. SWAP_2,
  68. SWAP_4,
  69. SWAP_8,
  70. SWAP_16,
  71. } ePL330_BYTESWAP;
  72. /**
  73. * enum PL330_COND - dma transfer mode
  74. */
  75. typedef enum {
  76. SINGLE,
  77. BURST,
  78. ALWAYS,
  79. } ePL330_COND;
  80. /** PL330 soc configuration */
  81. struct PL330_CONFIG {
  82. uint32_t periphId;
  83. uint32_t mode;
  84. uint32_t dataBusWidth; /**< In number of bits */
  85. uint32_t dataBufDep;
  86. uint32_t numChan;
  87. uint32_t numPeri;
  88. uint32_t periNs;
  89. uint32_t numEvents;
  90. uint32_t irqNs;
  91. };
  92. /** PL330 request config */
  93. struct PL330_REQCFG {
  94. /* Address Incrementing */
  95. uint32_t dstInc;
  96. uint32_t srcInc;
  97. /*
  98. * For now, the SRC & DST protection levels
  99. * and burst size/length are assumed same.
  100. */
  101. bool nonsecure;
  102. bool privileged;
  103. bool insnaccess;
  104. uint32_t brstLen;
  105. uint32_t brstSize; /**< bytes */
  106. ePL330_CACHECTRL dcctl;
  107. ePL330_CACHECTRL scctl;
  108. ePL330_BYTESWAP swap;
  109. };
  110. /** DMA block descriptor struct. */
  111. struct PL330_XFER {
  112. uint32_t srcAddr; /**< Source starting address */
  113. uint32_t dstAddr; /**< Destination starting address */
  114. uint32_t length; /**< Number of bytes for the xfer */
  115. };
  116. /**
  117. * It's the done callback a user can set for a desc
  118. */
  119. typedef void (*PL330_Callback)(void *cparam);
  120. /**
  121. * A DMA Desc consisits of a request config struct, a xfer descriptor,
  122. * a pointer pointing to generated DMA program, and execution result.
  123. */
  124. struct PL330_DESC {
  125. struct PL330_REQCFG rqcfg;
  126. struct PL330_XFER px;
  127. uint8_t peri;
  128. eDMA_TRANSFER_DIRECTION dir;
  129. bool cyclic;
  130. uint32_t numPeriods;
  131. uint32_t bytesReq;
  132. uint16_t srcInterlaceSize;
  133. uint16_t dstInterlaceSize;
  134. void *mcBuf;
  135. PL330_Callback callback;
  136. void *cparam;
  137. };
  138. struct PL330_XFER_SPEC {
  139. uint32_t ccr;
  140. struct PL330_DESC *desc;
  141. };
  142. struct HAL_PL330_DEV;
  143. /**
  144. * The PL330_CHAN Data is a struct to book keep individual channel of
  145. * the DMAC.
  146. */
  147. struct PL330_CHAN {
  148. uint16_t periId;
  149. uint16_t chanId;
  150. uint32_t fifoAddr;
  151. uint32_t brstSz;
  152. uint32_t brstLen;
  153. uint16_t srcInterlaceSize;
  154. uint16_t dstInterlaceSize;
  155. struct PL330_DESC desc;
  156. struct HAL_PL330_DEV *pl330;
  157. void *mcBuf;
  158. bool used;
  159. };
  160. /**
  161. * The PL330 driver instance data structure. A pointer to an instance data
  162. * structure is passed around by functions to refer to a specific driver
  163. * instance.
  164. */
  165. struct HAL_PL330_DEV {
  166. struct DMA_REG *pReg;
  167. struct PL330_CHAN chans[PL330_CHANNELS_PER_DEV];
  168. struct PL330_CONFIG pcfg;
  169. ePL330_COND peripReqType;
  170. IRQn_Type irq[PL330_NR_IRQS];
  171. ePD_Id pd;
  172. void *priv;
  173. };
  174. /** @} */
  175. /***************************** Function Declare ******************************/
  176. /** @defgroup PL330_Public_Function_Declare Public Function Declare
  177. * @{
  178. */
  179. HAL_Status HAL_PL330_Init(struct HAL_PL330_DEV *pl330);
  180. HAL_Status HAL_PL330_DeInit(struct HAL_PL330_DEV *pl330);
  181. HAL_Status HAL_PL330_Start(struct PL330_CHAN *pchan);
  182. HAL_Status HAL_PL330_Stop(struct PL330_CHAN *pchan);
  183. struct PL330_CHAN *HAL_PL330_RequestChannel(struct HAL_PL330_DEV *pl330, DMA_REQ_Type id);
  184. HAL_Status HAL_PL330_ReleaseChannel(struct PL330_CHAN *pchan);
  185. HAL_Status HAL_PL330_Config(struct PL330_CHAN *pchan, struct DMA_SLAVE_CONFIG *config);
  186. HAL_Status HAL_PL330_PrepDmaMemcpy(struct PL330_CHAN *pchan, uint32_t dst,
  187. uint32_t src, uint32_t len,
  188. PL330_Callback callback, void *cparam);
  189. HAL_Status HAL_PL330_PrepDmaCyclic(struct PL330_CHAN *pchan, uint32_t dmaAddr,
  190. uint32_t len, uint32_t periodLen,
  191. eDMA_TRANSFER_DIRECTION direction,
  192. PL330_Callback callback, void *cparam);
  193. HAL_Status HAL_PL330_PrepDmaSingle(struct PL330_CHAN *pchan, uint32_t dmaAddr,
  194. uint32_t len,
  195. eDMA_TRANSFER_DIRECTION direction,
  196. PL330_Callback callback, void *cparam);
  197. int HAL_PL330_GetPosition(struct PL330_CHAN *pchan);
  198. uint32_t HAL_PL330_IrqHandler(struct HAL_PL330_DEV *pl330);
  199. uint32_t HAL_PL330_GetRawIrqStatus(struct HAL_PL330_DEV *pl330);
  200. HAL_Status HAL_PL330_ClearIrq(struct HAL_PL330_DEV *pl330, uint32_t irq);
  201. HAL_Status HAL_PL330_SetMcBuf(struct PL330_CHAN *pchan, void *buf);
  202. void *HAL_PL330_GetMcBuf(struct PL330_CHAN *pchan);
  203. const struct PL330_DESC *HAL_PL330_GetDesc(struct PL330_CHAN *pchan);
  204. /** @} */
  205. #endif
  206. /** @} */
  207. /** @} */
  208. #endif
  209. /* HAL_PL330_MODULE_ENABLED */