spi.h 50 KB

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  1. /**
  2. * \file
  3. *
  4. * \brief SAM Serial Peripheral Interface Driver
  5. *
  6. * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
  7. *
  8. * \asf_license_start
  9. *
  10. * \page License
  11. *
  12. * Redistribution and use in source and binary forms, with or without
  13. * modification, are permitted provided that the following conditions are met:
  14. *
  15. * 1. Redistributions of source code must retain the above copyright notice,
  16. * this list of conditions and the following disclaimer.
  17. *
  18. * 2. Redistributions in binary form must reproduce the above copyright notice,
  19. * this list of conditions and the following disclaimer in the documentation
  20. * and/or other materials provided with the distribution.
  21. *
  22. * 3. The name of Atmel may not be used to endorse or promote products derived
  23. * from this software without specific prior written permission.
  24. *
  25. * 4. This software may only be redistributed and used in connection with an
  26. * Atmel microcontroller product.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
  29. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  30. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  31. * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
  32. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  37. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38. * POSSIBILITY OF SUCH DAMAGE.
  39. *
  40. * \asf_license_stop
  41. *
  42. */
  43. /*
  44. * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
  45. */
  46. #ifndef SPI_H_INCLUDED
  47. #define SPI_H_INCLUDED
  48. /**
  49. * \defgroup asfdoc_sam0_sercom_spi_group SAM Serial Peripheral Interface (SERCOM SPI) Driver
  50. *
  51. * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
  52. * an interface for the configuration and management of the SERCOM module in
  53. * its SPI mode to transfer SPI data frames. The following driver API modes
  54. * are covered by this manual:
  55. *
  56. * - Polled APIs
  57. * \if SPI_CALLBACK_MODE
  58. * - Callback APIs
  59. * \endif
  60. *
  61. * The following peripheral is used by this module:
  62. * - SERCOM (Serial Communication Interface)
  63. *
  64. * The following devices can use this module:
  65. * - Atmel | SMART SAM D20/D21
  66. * - Atmel | SMART SAM R21
  67. * - Atmel | SMART SAM D09/D10/D11
  68. * - Atmel | SMART SAM L21/L22
  69. * - Atmel | SMART SAM DA1
  70. * - Atmel | SMART SAM C20/C21
  71. * - Atmel | SMART SAM HA1
  72. * - Atmel | SMART SAM R30
  73. *
  74. * The outline of this documentation is as follows:
  75. * - \ref asfdoc_sam0_sercom_spi_prerequisites
  76. * - \ref asfdoc_sam0_sercom_spi_module_overview
  77. * - \ref asfdoc_sam0_sercom_spi_special_considerations
  78. * - \ref asfdoc_sam0_sercom_spi_extra_info
  79. * - \ref asfdoc_sam0_sercom_spi_examples
  80. * - \ref asfdoc_sam0_sercom_spi_api_overview
  81. *
  82. * \section asfdoc_sam0_sercom_spi_prerequisites Prerequisites
  83. * There are no prerequisites.
  84. *
  85. *
  86. * \section asfdoc_sam0_sercom_spi_module_overview Module Overview
  87. * The Serial Peripheral Interface (SPI) is a high-speed synchronous data
  88. * transfer interface using three or four pins. It allows fast communication
  89. * between a master device and one or more peripheral devices.
  90. *
  91. * A device connected to the bus must act as a master or a slave. The master
  92. * initiates and controls all data transactions.
  93. * The SPI master initiates a communication cycle by pulling low the Slave
  94. * Select (SS) pin of the desired slave. The Slave Select pin is active low.
  95. * Master and slave prepare data to be sent in their respective shift
  96. * registers, and the master generates the required clock pulses on the SCK
  97. * line to interchange data. Data is always shifted from master to slave on
  98. * the Master Out - Slave In (MOSI) line, and from slave to master on the
  99. * Master In - Slave Out (MISO) line. After each data transfer, the master can
  100. * synchronize to the slave by pulling the SS line high.
  101. *
  102. * \subsection asfdoc_sam0_sercom_spi_module_features Driver Feature Macro Definition
  103. * <table>
  104. * <tr>
  105. * <th>Driver feature macro</th>
  106. * <th>Supported devices</th>
  107. * </tr>
  108. * <tr>
  109. * <td>FEATURE_SPI_SLAVE_SELECT_LOW_DETECT</td>
  110. * <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30</td>
  111. * </tr>
  112. * <tr>
  113. * <td>FEATURE_SPI_HARDWARE_SLAVE_SELECT</td>
  114. * <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30</td>
  115. * </tr>
  116. * <tr>
  117. * <td>FEATURE_SPI_ERROR_INTERRUPT</td>
  118. * <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30</td>
  119. * </tr>
  120. * <tr>
  121. * <td>FEATURE_SPI_SYNC_SCHEME_VERSION_2</td>
  122. * <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30</td>
  123. * </tr>
  124. * </table>
  125. * \note The specific features are only available in the driver when the
  126. * selected device supports those features.
  127. *
  128. * \subsection asfdoc_sam0_sercom_spi_bus SPI Bus Connection
  129. * In \ref asfdoc_sam0_spi_connection_example "the figure below", the
  130. * connection between one master and one slave is shown.
  131. *
  132. * \anchor asfdoc_sam0_spi_connection_example
  133. * \dot
  134. * digraph spi_slaves_par {
  135. * subgraph cluster_spi_master {
  136. * shift_reg [label="Shift register", shape=box];
  137. * mosi_m [label="MOSI", shape=none];
  138. * miso_m [label="MISO", shape=none];
  139. * sck_m [label="SCK", shape=none];
  140. * ss_m [label="GPIO pin", shape=none];
  141. * {rank=same; mosi_m miso_m sck_m ss_m}
  142. * label="SPI Master";
  143. * }
  144. * subgraph cluster_spi_slave {
  145. * mosi_s [label="MOSI", shape=none];
  146. * miso_s [label="MISO", shape=none];
  147. * sck_s [label="SCK", shape=none];
  148. * ss_s [label="SS", shape=none];
  149. * shift_reg_s [label="Shift register", shape=box];
  150. * {rank=same; mosi_s miso_s sck_s ss_s}
  151. * label="SPI Slave";
  152. * rankdir=LR;
  153. * }
  154. * shift_reg:e -> mosi_m:w [label=""];
  155. * mosi_m:e -> mosi_s:w [label=""];
  156. * mosi_s:e -> shift_reg_s:w [label=""];
  157. * miso_s:w -> miso_m:e [label=""];
  158. * sck_m -> sck_s;
  159. * ss_m -> ss_s;
  160. * shift_reg_s:se -> miso_s:e [label=""];
  161. * miso_m:w -> shift_reg:sw [label=""];
  162. * rankdir=LR;
  163. * }
  164. * \enddot
  165. *
  166. * The different lines are as follows:
  167. * - \b MISO Master Input Slave Output. The line where the data is shifted
  168. * out from the slave and into the master.
  169. * - \b MOSI Master Output Slave Input. The line where the data is shifted
  170. * out from the master and into the slave.
  171. * - \b SCK Serial Clock. Generated by the master device.
  172. * - \b SS Slave Select. To initiate a transaction, the master must pull this
  173. * line low.
  174. *
  175. * If the bus consists of several SPI slaves, they can be connected in parallel
  176. * and the SPI master can use general I/O pins to control separate SS lines to
  177. * each slave on the bus.
  178. *
  179. * It is also possible to connect all slaves in series. In this configuration,
  180. * a common SS is provided to \c N slaves, enabling them simultaneously. The
  181. * MISO from the \c N-1 slaves is connected to the MOSI on the next slave. The
  182. * \c N<SUP>th</SUP> slave connects its MISO back to the master. For a
  183. * complete transaction, the master must shift \c N+1 characters.
  184. *
  185. * \subsection asfdoc_sam0_sercom_spi_chsize SPI Character Size
  186. * The SPI character size is configurable to eight or nine bits.
  187. *
  188. * \subsection asfdoc_sam0_sercom_spi_master_mode Master Mode
  189. * When configured as a master, the SS pin will be configured as an output.
  190. *
  191. * \subsubsection asfdoc_sam0_sercom_spi_master_mode_data_transfer Data Transfer
  192. * Writing a character will start the SPI clock generator, and
  193. * the character is transferred to the shift register when the shift
  194. * register is empty.
  195. * Once this is done, a new character can be written.
  196. * As each character is shifted out from the master, a character is shifted in
  197. * from the slave. If the receiver is enabled, the data is moved to the receive
  198. * buffer at the completion of the frame and can be read.
  199. *
  200. * \subsection asfdoc_sam0_sercom_spi_slave_mode Slave Mode
  201. * When configured as a slave, the SPI interface will remain inactive with MISO
  202. * tri-stated as long as the SS pin is driven high.
  203. *
  204. * \subsubsection asfdoc_sam0_sercom_spi_slave_mode_data_transfer_slave Data Transfer
  205. * The data register can be updated at any time.
  206. * As the SPI slave shift register is clocked by SCK, a minimum of three SCK
  207. * cycles are needed from the time new data is written, until the character is
  208. * ready to be shifted out. If the shift register has not been loaded with
  209. * data, the current contents will be transmitted.
  210. *
  211. * If constant transmission of data is needed in SPI slave mode, the system
  212. * clock should be faster than SCK.
  213. * If the receiver is enabled, the received character can be read from the
  214. * receive buffer. When SS line is driven high, the slave will not receive any
  215. * additional data.
  216. *
  217. * \subsubsection asfdoc_sam0_sercom_spi_slave_mode_addr_recognition Address Recognition
  218. * When the SPI slave is configured with address recognition, the first
  219. * character in a transaction is checked for an address match. If there is a
  220. * match, the MISO output is enabled and the transaction is processed.
  221. * If the address does not match, the complete transaction is ignored.
  222. *
  223. * If the device is asleep, it can be woken up by an address match in order
  224. * to process the transaction.
  225. *
  226. * \note In master mode, an address packet is written by the
  227. * \ref spi_select_slave function if the address_enabled configuration is
  228. * set in the \ref spi_slave_inst_config struct.
  229. *
  230. * \subsection asfdoc_sam0_sercom_spi_data_modes Data Modes
  231. * There are four combinations of SCK phase and polarity with respect to
  232. * serial data. \ref asfdoc_sam0_spi_mode_table "The table below" shows the
  233. * clock polarity (CPOL) and clock phase (CPHA) in the different modes.
  234. * <i>Leading edge</i> is the first clock edge in a clock cycle and
  235. * <i>trailing edge</i> is the last clock edge in a clock cycle.
  236. *
  237. * \anchor asfdoc_sam0_spi_mode_table
  238. * <table>
  239. * <caption>SPI Data Modes</caption>
  240. * <tr>
  241. * <th>Mode</th>
  242. * <th>CPOL</th>
  243. * <th>CPHA</th>
  244. * <th>Leading Edge</th>
  245. * <th>Trailing Edge</th>
  246. * </tr>
  247. * <tr>
  248. * <td> 0 </td>
  249. * <td> 0 </td>
  250. * <td> 0 </td>
  251. * <td> Rising, Sample </td>
  252. * <td> Falling, Setup </td>
  253. * </tr>
  254. * <tr>
  255. * <td> 1 </td>
  256. * <td> 0 </td>
  257. * <td> 1 </td>
  258. * <td> Rising, Setup </td>
  259. * <td> Falling, Sample </td>
  260. * </tr>
  261. * <tr>
  262. * <td> 2 </td>
  263. * <td> 1 </td>
  264. * <td> 0 </td>
  265. * <td> Falling, Sample </td>
  266. * <td> Rising, Setup </td>
  267. * </tr>
  268. * <tr>
  269. * <td> 3 </td>
  270. * <td> 1 </td>
  271. * <td> 1 </td>
  272. * <td> Falling, Setup </td>
  273. * <td> Rising, Sample </td>
  274. * </tr>
  275. * </table>
  276. *
  277. *
  278. * \subsection asfdoc_sam0_sercom_spi_pads SERCOM Pads
  279. * The SERCOM pads are automatically configured as seen in
  280. * \ref asfdoc_sam0_spi_sercom_pad_table "the table below". If the receiver
  281. * is disabled, the data input (MISO for master, MOSI for slave) can be used
  282. * for other purposes.
  283. *
  284. * In master mode, the SS pin(s) must be configured using the \ref spi_slave_inst
  285. * struct.
  286. *
  287. * \anchor asfdoc_sam0_spi_sercom_pad_table
  288. * <table>
  289. * <caption>SERCOM SPI Pad Usages</caption>
  290. * <tr>
  291. * <th> Pin </th>
  292. * <th> Master SPI </th>
  293. * <th> Slave SPI </th>
  294. * </tr>
  295. * <tr>
  296. * <td> MOSI </td>
  297. * <td> Output </td>
  298. * <td> Input </td>
  299. * </tr>
  300. * <tr>
  301. * <td> MISO </td>
  302. * <td> Input </td>
  303. * <td> Output </td>
  304. * </tr>
  305. * <tr>
  306. * <td> SCK </td>
  307. * <td> Output </td>
  308. * <td> Input </td>
  309. * </tr>
  310. * <tr>
  311. * <td> SS </td>
  312. * <td> User defined output enable </td>
  313. * <td> Input </td>
  314. * </tr>
  315. * </table>
  316. *
  317. * \subsection asfdoc_sam0_sercom_spi_sleep_modes Operation in Sleep Modes
  318. * The SPI module can operate in all sleep modes by setting the run_in_standby
  319. * option in the \ref spi_config struct. The operation in slave and master mode
  320. * is shown in the table below.
  321. * <table>
  322. * <tr>
  323. * <th> run_in_standby </th>
  324. * <th> Slave </th>
  325. * <th> Master </th>
  326. * </tr>
  327. * <tr>
  328. * <td> false </td>
  329. * <td> Disabled, all reception is dropped </td>
  330. * <td> GCLK is disabled when master is idle, wake on transmit complete </td>
  331. * </tr>
  332. * <tr>
  333. * <td> true </td>
  334. * <td> Wake on reception </td>
  335. * <td> GCLK is enabled while in sleep modes, wake on all interrupts </td>
  336. * </tr>
  337. * </table>
  338. *
  339. * \subsection asfdoc_sam0_sercom_spi_clock_generation Clock Generation
  340. * In SPI master mode, the clock (SCK) is generated internally using the
  341. * SERCOM baudrate generator. In SPI slave mode, the clock is provided by
  342. * an external master on the SCK pin. This clock is used to directly clock
  343. * the SPI shift register.
  344. *
  345. * \section asfdoc_sam0_sercom_spi_special_considerations Special Considerations
  346. * \subsection pin_mux pinmux Settings
  347. * The pin MUX settings must be configured properly, as not all settings
  348. * can be used in different modes of operation.
  349. *
  350. * \section asfdoc_sam0_sercom_spi_extra_info Extra Information
  351. * For extra information, see \ref asfdoc_sam0_sercom_spi_extra. This includes:
  352. * - \ref asfdoc_sam0_sercom_spi_extra_acronyms
  353. * - \ref asfdoc_sam0_sercom_spi_extra_dependencies
  354. * - \ref asfdoc_sam0_sercom_spi_extra_workarounds
  355. * - \ref asfdoc_sam0_sercom_spi_extra_history
  356. *
  357. * \section asfdoc_sam0_sercom_spi_examples Examples
  358. *
  359. * For a list of examples related to this driver, see
  360. * \ref asfdoc_sam0_sercom_spi_exqsg.
  361. *
  362. * \section asfdoc_sam0_sercom_spi_api_overview API Overview
  363. * @{
  364. */
  365. #include <compiler.h>
  366. #include <port.h>
  367. #include <sercom.h>
  368. #include <pinmux.h>
  369. #include <string.h>
  370. #include <conf_spi.h>
  371. # if SPI_CALLBACK_MODE == true
  372. # include <sercom_interrupt.h>
  373. # endif
  374. #ifdef __cplusplus
  375. extern "C" {
  376. #endif
  377. #if (CONF_SPI_MASTER_ENABLE == false) && (CONF_SPI_SLAVE_ENABLE == false)
  378. #error "Not possible compile SPI driver, invalid driver configuration. Make sure that either/both CONF_SPI_MASTER_ENABLE/CONF_SPI_SLAVE_ENABLE is set to true."
  379. #endif
  380. /**
  381. * \name Driver Feature Definition
  382. * Define SERCOM SPI features set according to different device family.
  383. * @{
  384. */
  385. # if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAML21) || (SAMDA1) || (SAMHA1) ||\
  386. (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__)
  387. /** SPI slave select low detection. */
  388. # define FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
  389. /** Slave select can be controlled by hardware. */
  390. # define FEATURE_SPI_HARDWARE_SLAVE_SELECT
  391. /** SPI with error detect feature. */
  392. # define FEATURE_SPI_ERROR_INTERRUPT
  393. /** SPI sync scheme version 2. */
  394. # define FEATURE_SPI_SYNC_SCHEME_VERSION_2
  395. # endif
  396. /*@}*/
  397. # ifndef PINMUX_DEFAULT
  398. /** Default pinmux. */
  399. # define PINMUX_DEFAULT 0
  400. # endif
  401. # ifndef PINMUX_UNUSED
  402. /** Unused pinmux. */
  403. # define PINMUX_UNUSED 0xFFFFFFFF
  404. # endif
  405. # ifndef SPI_TIMEOUT
  406. /** SPI timeout value. */
  407. # define SPI_TIMEOUT 10000
  408. # endif
  409. # if SPI_CALLBACK_MODE == true
  410. /**
  411. * \brief SPI Callback enum
  412. *
  413. * Callbacks for SPI callback driver.
  414. *
  415. * \note For slave mode, these callbacks will be called when a transaction
  416. * is ended by the master pulling Slave Select high.
  417. *
  418. */
  419. enum spi_callback {
  420. /** Callback for buffer transmitted */
  421. SPI_CALLBACK_BUFFER_TRANSMITTED,
  422. /** Callback for buffer received */
  423. SPI_CALLBACK_BUFFER_RECEIVED,
  424. /** Callback for buffers transceived */
  425. SPI_CALLBACK_BUFFER_TRANSCEIVED,
  426. /** Callback for error */
  427. SPI_CALLBACK_ERROR,
  428. /**
  429. * Callback for transmission ended by master before the entire buffer was
  430. * read or written from slave
  431. */
  432. SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE,
  433. # ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
  434. /** Callback for slave select low */
  435. SPI_CALLBACK_SLAVE_SELECT_LOW,
  436. # endif
  437. # ifdef FEATURE_SPI_ERROR_INTERRUPT
  438. /** Callback for combined error happen */
  439. SPI_CALLBACK_COMBINED_ERROR,
  440. # endif
  441. # if !defined(__DOXYGEN__)
  442. /** Number of available callbacks */
  443. SPI_CALLBACK_N,
  444. # endif
  445. };
  446. # endif
  447. #if SPI_CALLBACK_MODE == true
  448. # if !defined(__DOXYGEN__)
  449. /**
  450. * \internal SPI transfer directions
  451. */
  452. enum _spi_direction {
  453. /** Transfer direction is read */
  454. SPI_DIRECTION_READ,
  455. /** Transfer direction is write */
  456. SPI_DIRECTION_WRITE,
  457. /** Transfer direction is read and write */
  458. SPI_DIRECTION_BOTH,
  459. /** No transfer */
  460. SPI_DIRECTION_IDLE,
  461. };
  462. # endif
  463. #endif
  464. /**
  465. * \brief SPI Interrupt Flags
  466. *
  467. * Interrupt flags for the SPI module.
  468. *
  469. */
  470. enum spi_interrupt_flag {
  471. /**
  472. * This flag is set when the contents of the data register has been moved
  473. * to the shift register and the data register is ready for new data
  474. */
  475. SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY = SERCOM_SPI_INTFLAG_DRE,
  476. /**
  477. * This flag is set when the contents of the shift register has been
  478. * shifted out
  479. */
  480. SPI_INTERRUPT_FLAG_TX_COMPLETE = SERCOM_SPI_INTFLAG_TXC,
  481. /** This flag is set when data has been shifted into the data register */
  482. SPI_INTERRUPT_FLAG_RX_COMPLETE = SERCOM_SPI_INTFLAG_RXC,
  483. # ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
  484. /** This flag is set when slave select low */
  485. SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW = SERCOM_SPI_INTFLAG_SSL,
  486. # endif
  487. # ifdef FEATURE_SPI_ERROR_INTERRUPT
  488. /** This flag is set when combined error happen */
  489. SPI_INTERRUPT_FLAG_COMBINED_ERROR = SERCOM_SPI_INTFLAG_ERROR,
  490. # endif
  491. };
  492. /**
  493. * \brief SPI transfer modes enum
  494. *
  495. * SPI transfer mode.
  496. */
  497. enum spi_transfer_mode {
  498. /** Mode 0. Leading edge: rising, sample. Trailing edge: falling, setup */
  499. SPI_TRANSFER_MODE_0 = 0,
  500. /** Mode 1. Leading edge: rising, setup. Trailing edge: falling, sample */
  501. SPI_TRANSFER_MODE_1 = SERCOM_SPI_CTRLA_CPHA,
  502. /** Mode 2. Leading edge: falling, sample. Trailing edge: rising, setup */
  503. SPI_TRANSFER_MODE_2 = SERCOM_SPI_CTRLA_CPOL,
  504. /** Mode 3. Leading edge: falling, setup. Trailing edge: rising, sample */
  505. SPI_TRANSFER_MODE_3 = SERCOM_SPI_CTRLA_CPHA | SERCOM_SPI_CTRLA_CPOL,
  506. };
  507. /**
  508. * \brief SPI frame format enum
  509. *
  510. * Frame format for slave mode.
  511. */
  512. enum spi_frame_format {
  513. /** SPI frame */
  514. SPI_FRAME_FORMAT_SPI_FRAME = SERCOM_SPI_CTRLA_FORM(0),
  515. /** SPI frame with address */
  516. SPI_FRAME_FORMAT_SPI_FRAME_ADDR = SERCOM_SPI_CTRLA_FORM(2),
  517. };
  518. /**
  519. * \brief SPI signal MUX settings
  520. *
  521. * Set the functionality of the SERCOM pins. As not all combinations can be used
  522. * in different modes of operation, proper combinations must be chosen according
  523. * to the rest of the configuration.
  524. *
  525. * \note In master operation: DI is MISO, DO is MOSI.
  526. * In slave operation: DI is MOSI, DO is MISO.
  527. *
  528. * See \ref asfdoc_sam0_sercom_spi_mux_settings for a description of the
  529. * various MUX setting options.
  530. */
  531. enum spi_signal_mux_setting {
  532. /** SPI MUX combination A. DOPO: 0x0, DIPO: 0x0 */
  533. SPI_SIGNAL_MUX_SETTING_A =
  534. (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  535. (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
  536. /** SPI MUX combination B. DOPO: 0x0, DIPO: 0x1 */
  537. SPI_SIGNAL_MUX_SETTING_B =
  538. (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  539. (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
  540. /** SPI MUX combination C. DOPO: 0x0, DIPO: 0x2 */
  541. SPI_SIGNAL_MUX_SETTING_C =
  542. (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  543. (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
  544. /** SPI MUX combination D. DOPO: 0x0, DIPO: 0x3 */
  545. SPI_SIGNAL_MUX_SETTING_D =
  546. (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  547. (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
  548. /** SPI MUX combination E. DOPO: 0x1, DIPO: 0x0 */
  549. SPI_SIGNAL_MUX_SETTING_E =
  550. (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  551. (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
  552. /** SPI MUX combination F. DOPO: 0x1, DIPO: 0x1 */
  553. SPI_SIGNAL_MUX_SETTING_F =
  554. (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  555. (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
  556. /** SPI MUX combination G. DOPO: 0x1, DIPO: 0x2 */
  557. SPI_SIGNAL_MUX_SETTING_G =
  558. (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  559. (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
  560. /** SPI MUX combination H. DOPO: 0x1, DIPO: 0x3 */
  561. SPI_SIGNAL_MUX_SETTING_H =
  562. (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  563. (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
  564. /** SPI MUX combination I. DOPO: 0x2, DIPO: 0x0 */
  565. SPI_SIGNAL_MUX_SETTING_I =
  566. (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  567. (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
  568. /** SPI MUX combination J. DOPO: 0x2, DIPO: 0x1 */
  569. SPI_SIGNAL_MUX_SETTING_J =
  570. (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  571. (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
  572. /** SPI MUX combination K. DOPO: 0x2, DIPO: 0x2 */
  573. SPI_SIGNAL_MUX_SETTING_K =
  574. (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  575. (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
  576. /** SPI MUX combination L. DOPO: 0x2, DIPO: 0x3 */
  577. SPI_SIGNAL_MUX_SETTING_L =
  578. (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  579. (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
  580. /** SPI MUX combination M. DOPO: 0x3, DIPO: 0x0 */
  581. SPI_SIGNAL_MUX_SETTING_M =
  582. (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  583. (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
  584. /** SPI MUX combination N. DOPO: 0x3, DIPO: 0x1 */
  585. SPI_SIGNAL_MUX_SETTING_N =
  586. (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  587. (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
  588. /** SPI MUX combination O. DOPO: 0x3, DIPO: 0x2 */
  589. SPI_SIGNAL_MUX_SETTING_O =
  590. (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  591. (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
  592. /** SPI MUX combination P. DOPO: 0x3, DIPO: 0x3 */
  593. SPI_SIGNAL_MUX_SETTING_P =
  594. (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
  595. (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
  596. };
  597. /**
  598. * \brief SPI address modes enum
  599. *
  600. * For slave mode when using the SPI frame with address format.
  601. *
  602. */
  603. enum spi_addr_mode {
  604. /**
  605. * \c address_mask in the \ref spi_config struct is used as a mask to the register
  606. */
  607. SPI_ADDR_MODE_MASK = SERCOM_SPI_CTRLB_AMODE(0),
  608. /**
  609. * The slave responds to the two unique addresses in \c address and
  610. * \c address_mask in the \ref spi_config struct
  611. */
  612. SPI_ADDR_MODE_UNIQUE = SERCOM_SPI_CTRLB_AMODE(1),
  613. /**
  614. * The slave responds to the range of addresses between and including \c address
  615. * and \c address_mask in the \ref spi_config struct
  616. */
  617. SPI_ADDR_MODE_RANGE = SERCOM_SPI_CTRLB_AMODE(2),
  618. };
  619. /**
  620. * \brief SPI modes enum
  621. *
  622. * SPI mode selection.
  623. */
  624. enum spi_mode {
  625. /** Master mode */
  626. SPI_MODE_MASTER = 1,
  627. /** Slave mode */
  628. SPI_MODE_SLAVE = 0,
  629. };
  630. /**
  631. * \brief SPI data order enum
  632. *
  633. * SPI data order.
  634. *
  635. */
  636. enum spi_data_order {
  637. /** The LSB of the data is transmitted first */
  638. SPI_DATA_ORDER_LSB = SERCOM_SPI_CTRLA_DORD,
  639. /** The MSB of the data is transmitted first */
  640. SPI_DATA_ORDER_MSB = 0,
  641. };
  642. /**
  643. * \brief SPI character size enum
  644. *
  645. * SPI character size.
  646. *
  647. */
  648. enum spi_character_size {
  649. /** 8-bit character */
  650. SPI_CHARACTER_SIZE_8BIT = SERCOM_SPI_CTRLB_CHSIZE(0),
  651. /** 9-bit character */
  652. SPI_CHARACTER_SIZE_9BIT = SERCOM_SPI_CTRLB_CHSIZE(1),
  653. };
  654. # if SPI_CALLBACK_MODE == true
  655. /** Prototype for the device instance */
  656. struct spi_module;
  657. /** Type of the callback functions */
  658. typedef void (*spi_callback_t)(struct spi_module *const module);
  659. # if !defined(__DOXYGEN__)
  660. /** Prototype for the interrupt handler */
  661. extern void _spi_interrupt_handler(uint8_t instance);
  662. # endif
  663. # endif
  664. /**
  665. * \brief SERCOM SPI driver software device instance structure.
  666. *
  667. * SERCOM SPI driver software instance structure, used to retain software state
  668. * information of an associated hardware module instance.
  669. *
  670. * \note The fields of this structure should not be altered by the user
  671. * application; they are reserved for module-internal use only.
  672. */
  673. struct spi_module {
  674. # if !defined(__DOXYGEN__)
  675. /** SERCOM hardware module */
  676. Sercom *hw;
  677. /** Module lock */
  678. volatile bool locked;
  679. /** SPI mode */
  680. enum spi_mode mode;
  681. /** SPI character size */
  682. enum spi_character_size character_size;
  683. /** Receiver enabled */
  684. bool receiver_enabled;
  685. # ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
  686. /** Enable Hardware Slave Select */
  687. bool master_slave_select_enable;
  688. # endif
  689. # if SPI_CALLBACK_MODE == true
  690. /** Direction of transaction */
  691. volatile enum _spi_direction dir;
  692. /** Array to store callback function pointers in */
  693. spi_callback_t callback[SPI_CALLBACK_N];
  694. /** Buffer pointer to where the next received character will be put */
  695. volatile uint8_t *rx_buffer_ptr;
  696. /** Buffer pointer to where the next character will be transmitted from
  697. **/
  698. volatile uint8_t *tx_buffer_ptr;
  699. /** Remaining characters to receive */
  700. volatile uint16_t remaining_rx_buffer_length;
  701. /** Remaining dummy characters to send when reading */
  702. volatile uint16_t remaining_dummy_buffer_length;
  703. /** Remaining characters to transmit */
  704. volatile uint16_t remaining_tx_buffer_length;
  705. /** Bit mask for callbacks registered */
  706. uint8_t registered_callback;
  707. /** Bit mask for callbacks enabled */
  708. uint8_t enabled_callback;
  709. /** Holds the status of the ongoing or last operation */
  710. volatile enum status_code status;
  711. # endif
  712. # endif
  713. };
  714. /**
  715. * \brief SPI peripheral slave instance structure
  716. *
  717. * SPI peripheral slave software instance structure, used to configure the
  718. * correct SPI transfer mode settings for an attached slave. See
  719. * \ref spi_select_slave.
  720. */
  721. struct spi_slave_inst {
  722. /** Pin to use as slave select */
  723. uint8_t ss_pin;
  724. /** Address recognition enabled in slave device */
  725. bool address_enabled;
  726. /** Address of slave device */
  727. uint8_t address;
  728. };
  729. /**
  730. * \brief SPI peripheral slave configuration structure
  731. *
  732. * SPI Peripheral slave configuration structure.
  733. */
  734. struct spi_slave_inst_config {
  735. /** Pin to use as slave select */
  736. uint8_t ss_pin;
  737. /** Enable address */
  738. bool address_enabled;
  739. /** Address of slave */
  740. uint8_t address;
  741. };
  742. /**
  743. * \brief SPI Master configuration structure
  744. *
  745. * SPI Master configuration structure.
  746. */
  747. struct spi_master_config {
  748. /** Baud rate */
  749. uint32_t baudrate;
  750. };
  751. /**
  752. * \brief SPI slave configuration structure
  753. *
  754. * SPI slave configuration structure.
  755. */
  756. struct spi_slave_config {
  757. /** Frame format */
  758. enum spi_frame_format frame_format;
  759. /** Address mode */
  760. enum spi_addr_mode address_mode;
  761. /** Address */
  762. uint8_t address;
  763. /** Address mask */
  764. uint8_t address_mask;
  765. /** Preload data to the shift register while SS is high */
  766. bool preload_enable;
  767. };
  768. /**
  769. * \brief SPI configuration structure
  770. *
  771. * Configuration structure for an SPI instance. This structure should be
  772. * initialized by the \ref spi_get_config_defaults function before being
  773. * modified by the user application.
  774. */
  775. struct spi_config {
  776. /** SPI mode */
  777. enum spi_mode mode;
  778. /** Data order */
  779. enum spi_data_order data_order;
  780. /** Transfer mode */
  781. enum spi_transfer_mode transfer_mode;
  782. /** MUX setting */
  783. enum spi_signal_mux_setting mux_setting;
  784. /** SPI character size */
  785. enum spi_character_size character_size;
  786. /** Enabled in sleep modes */
  787. bool run_in_standby;
  788. /** Enable receiver */
  789. bool receiver_enable;
  790. # ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
  791. /** Enable Slave Select Low Detect */
  792. bool select_slave_low_detect_enable;
  793. # endif
  794. # ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
  795. /** Enable Master Slave Select */
  796. bool master_slave_select_enable;
  797. # endif
  798. /** Union for slave or master specific configuration */
  799. union {
  800. /** Slave specific configuration */
  801. struct spi_slave_config slave;
  802. /** Master specific configuration */
  803. struct spi_master_config master;
  804. } mode_specific;
  805. /** GCLK generator to use as clock source */
  806. enum gclk_generator generator_source;
  807. /** PAD0 pinmux */
  808. uint32_t pinmux_pad0;
  809. /** PAD1 pinmux */
  810. uint32_t pinmux_pad1;
  811. /** PAD2 pinmux */
  812. uint32_t pinmux_pad2;
  813. /** PAD3 pinmux */
  814. uint32_t pinmux_pad3;
  815. };
  816. /**
  817. * \brief Determines if the SPI module is currently synchronizing to the bus.
  818. *
  819. * This function will check if the underlying hardware peripheral module is
  820. * currently synchronizing across multiple clock domains to the hardware bus.
  821. * This function can be used to delay further operations on the module until it
  822. * is ready.
  823. *
  824. * \param[in] module SPI hardware module
  825. *
  826. * \return Synchronization status of the underlying hardware module.
  827. * \retval true Module synchronization is ongoing
  828. * \retval false Module synchronization is not ongoing
  829. *
  830. */
  831. static inline bool spi_is_syncing(
  832. struct spi_module *const module)
  833. {
  834. /* Sanity check arguments */
  835. Assert(module);
  836. Assert(module->hw);
  837. SercomSpi *const spi_module = &(module->hw->SPI);
  838. # ifdef FEATURE_SPI_SYNC_SCHEME_VERSION_2
  839. /* Return synchronization status */
  840. return (spi_module->SYNCBUSY.reg);
  841. # else
  842. /* Return synchronization status */
  843. return (spi_module->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY);
  844. # endif
  845. }
  846. /**
  847. * \name Driver Initialization and Configuration
  848. * @{
  849. */
  850. /**
  851. * \brief Initializes an SPI configuration structure to default values
  852. *
  853. * This function will initialize a given SPI configuration structure to a set
  854. * of known default values. This function should be called on any new
  855. * instance of the configuration structures before being modified by the
  856. * user application.
  857. *
  858. * The default configuration is as follows:
  859. * \li Master mode enabled
  860. * \li MSB of the data is transmitted first
  861. * \li Transfer mode 0
  862. * \li MUX Setting D
  863. * \li Character size eight bits
  864. * \li Not enabled in sleep mode
  865. * \li Receiver enabled
  866. * \li Baudrate 100000
  867. * \li Default pinmux settings for all pads
  868. * \li GCLK generator 0
  869. *
  870. * \param[out] config Configuration structure to initialize to default values
  871. */
  872. static inline void spi_get_config_defaults(
  873. struct spi_config *const config)
  874. {
  875. /* Sanity check arguments */
  876. Assert(config);
  877. /* Default configuration values */
  878. config->mode = SPI_MODE_MASTER;
  879. config->data_order = SPI_DATA_ORDER_MSB;
  880. config->transfer_mode = SPI_TRANSFER_MODE_0;
  881. config->mux_setting = SPI_SIGNAL_MUX_SETTING_D;
  882. config->character_size = SPI_CHARACTER_SIZE_8BIT;
  883. config->run_in_standby = false;
  884. config->receiver_enable = true;
  885. # ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
  886. config->select_slave_low_detect_enable= true;
  887. # endif
  888. # ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
  889. config->master_slave_select_enable= false;
  890. # endif
  891. config->generator_source = GCLK_GENERATOR_0;
  892. /* Clear mode specific config */
  893. memset(&(config->mode_specific), 0, sizeof(config->mode_specific));
  894. /* Master config defaults */
  895. config->mode_specific.master.baudrate = 100000;
  896. /* pinmux config defaults */
  897. config->pinmux_pad0 = PINMUX_DEFAULT;
  898. config->pinmux_pad1 = PINMUX_DEFAULT;
  899. config->pinmux_pad2 = PINMUX_DEFAULT;
  900. config->pinmux_pad3 = PINMUX_DEFAULT;
  901. };
  902. /**
  903. * \brief Initializes an SPI peripheral slave device configuration structure to default values
  904. *
  905. * This function will initialize a given SPI slave device configuration
  906. * structure to a set of known default values. This function should be called
  907. * on any new instance of the configuration structures before being modified by
  908. * the user application.
  909. *
  910. * The default configuration is as follows:
  911. * \li Slave Select on GPIO pin 10
  912. * \li Addressing not enabled
  913. *
  914. * \param[out] config Configuration structure to initialize to default values
  915. */
  916. static inline void spi_slave_inst_get_config_defaults(
  917. struct spi_slave_inst_config *const config)
  918. {
  919. Assert(config);
  920. config->ss_pin = 10;
  921. config->address_enabled = false;
  922. config->address = 0;
  923. }
  924. /**
  925. * \brief Attaches an SPI peripheral slave
  926. *
  927. * This function will initialize the software SPI peripheral slave, based on
  928. * the values of the config struct. The slave can then be selected and
  929. * optionally addressed by the \ref spi_select_slave function.
  930. *
  931. * \param[out] slave Pointer to the software slave instance struct
  932. * \param[in] config Pointer to the config struct
  933. *
  934. */
  935. static inline void spi_attach_slave(
  936. struct spi_slave_inst *const slave,
  937. const struct spi_slave_inst_config *const config)
  938. {
  939. Assert(slave);
  940. Assert(config);
  941. slave->ss_pin = config->ss_pin;
  942. slave->address_enabled = config->address_enabled;
  943. slave->address = config->address;
  944. /* Get default config for pin */
  945. struct port_config pin_conf;
  946. port_get_config_defaults(&pin_conf);
  947. /* Edit config to set the pin as output */
  948. pin_conf.direction = PORT_PIN_DIR_OUTPUT;
  949. /* Set config on Slave Select pin */
  950. port_pin_set_config(slave->ss_pin, &pin_conf);
  951. port_pin_set_output_level(slave->ss_pin, true);
  952. }
  953. enum status_code spi_init(
  954. struct spi_module *const module,
  955. Sercom *const hw,
  956. const struct spi_config *const config);
  957. /** @} */
  958. /**
  959. * \name Enable/Disable
  960. * @{
  961. */
  962. /**
  963. * \brief Enables the SERCOM SPI module
  964. *
  965. * This function will enable the SERCOM SPI module.
  966. *
  967. * \param[in,out] module Pointer to the software instance struct
  968. */
  969. static inline void spi_enable(
  970. struct spi_module *const module)
  971. {
  972. /* Sanity check arguments */
  973. Assert(module);
  974. Assert(module->hw);
  975. SercomSpi *const spi_module = &(module->hw->SPI);
  976. # if SPI_CALLBACK_MODE == true
  977. system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
  978. # endif
  979. while (spi_is_syncing(module)) {
  980. /* Wait until the synchronization is complete */
  981. }
  982. /* Enable SPI */
  983. spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
  984. }
  985. /**
  986. * \brief Disables the SERCOM SPI module
  987. *
  988. * This function will disable the SERCOM SPI module.
  989. *
  990. * \param[in,out] module Pointer to the software instance struct
  991. */
  992. static inline void spi_disable(
  993. struct spi_module *const module)
  994. {
  995. /* Sanity check arguments */
  996. Assert(module);
  997. Assert(module->hw);
  998. SercomSpi *const spi_module = &(module->hw->SPI);
  999. # if SPI_CALLBACK_MODE == true
  1000. system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
  1001. # endif
  1002. while (spi_is_syncing(module)) {
  1003. /* Wait until the synchronization is complete */
  1004. }
  1005. /* Disbale interrupt */
  1006. spi_module->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK;
  1007. /* Clear interrupt flag */
  1008. spi_module->INTFLAG.reg = SERCOM_SPI_INTFLAG_MASK;
  1009. /* Disable SPI */
  1010. spi_module->CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
  1011. }
  1012. void spi_reset(
  1013. struct spi_module *const module);
  1014. /** @} */
  1015. enum status_code spi_set_baudrate(
  1016. struct spi_module *const module,
  1017. uint32_t baudrate);
  1018. /**
  1019. * \name Lock/Unlock
  1020. * @{
  1021. */
  1022. /**
  1023. * \brief Attempt to get lock on driver instance
  1024. *
  1025. * This function checks the instance's lock, which indicates whether or not it
  1026. * is currently in use, and sets the lock if it was not already set.
  1027. *
  1028. * The purpose of this is to enable exclusive access to driver instances, so
  1029. * that, e.g., transactions by different services will not interfere with each
  1030. * other.
  1031. *
  1032. * \param[in,out] module Pointer to the driver instance to lock
  1033. *
  1034. * \retval STATUS_OK If the module was locked
  1035. * \retval STATUS_BUSY If the module was already locked
  1036. */
  1037. static inline enum status_code spi_lock(struct spi_module *const module)
  1038. {
  1039. enum status_code status;
  1040. system_interrupt_enter_critical_section();
  1041. if (module->locked) {
  1042. status = STATUS_BUSY;
  1043. } else {
  1044. module->locked = true;
  1045. status = STATUS_OK;
  1046. }
  1047. system_interrupt_leave_critical_section();
  1048. return status;
  1049. }
  1050. /**
  1051. * \brief Unlock driver instance
  1052. *
  1053. * This function clears the instance lock, indicating that it is available for
  1054. * use.
  1055. *
  1056. * \param[in,out] module Pointer to the driver instance to lock
  1057. *
  1058. * \retval STATUS_OK If the module was locked
  1059. * \retval STATUS_BUSY If the module was already locked
  1060. */
  1061. static inline void spi_unlock(struct spi_module *const module)
  1062. {
  1063. module->locked = false;
  1064. }
  1065. /** @} */
  1066. /**
  1067. * \name Ready to Write/Read
  1068. * @{
  1069. */
  1070. /**
  1071. * \brief Checks if the SPI in master mode has shifted out last data, or if the master has ended the transfer in slave mode.
  1072. *
  1073. * This function will check if the SPI master module has shifted out last data,
  1074. * or if the slave select pin has been drawn high by the master for the SPI
  1075. * slave module.
  1076. *
  1077. * \param[in] module Pointer to the software instance struct
  1078. *
  1079. * \return Indication of whether any writes are ongoing.
  1080. * \retval true If the SPI master module has shifted out data, or slave select
  1081. * has been drawn high for SPI slave
  1082. * \retval false If the SPI master module has not shifted out data
  1083. */
  1084. static inline bool spi_is_write_complete(
  1085. struct spi_module *const module)
  1086. {
  1087. /* Sanity check arguments */
  1088. Assert(module);
  1089. Assert(module->hw);
  1090. SercomSpi *const spi_module = &(module->hw->SPI);
  1091. /* Check interrupt flag */
  1092. return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC);
  1093. }
  1094. /**
  1095. * \brief Checks if the SPI module is ready to write data
  1096. *
  1097. * This function will check if the SPI module is ready to write data.
  1098. *
  1099. * \param[in] module Pointer to the software instance struct
  1100. *
  1101. * \return Indication of whether the module is ready to read data or not.
  1102. * \retval true If the SPI module is ready to write data
  1103. * \retval false If the SPI module is not ready to write data
  1104. */
  1105. static inline bool spi_is_ready_to_write(
  1106. struct spi_module *const module)
  1107. {
  1108. /* Sanity check arguments */
  1109. Assert(module);
  1110. Assert(module->hw);
  1111. SercomSpi *const spi_module = &(module->hw->SPI);
  1112. /* Check interrupt flag */
  1113. return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE);
  1114. }
  1115. /**
  1116. * \brief Checks if the SPI module is ready to read data
  1117. *
  1118. * This function will check if the SPI module is ready to read data.
  1119. *
  1120. * \param[in] module Pointer to the software instance struct
  1121. *
  1122. * \return Indication of whether the module is ready to read data or not.
  1123. * \retval true If the SPI module is ready to read data
  1124. * \retval false If the SPI module is not ready to read data
  1125. */
  1126. static inline bool spi_is_ready_to_read(
  1127. struct spi_module *const module)
  1128. {
  1129. /* Sanity check arguments */
  1130. Assert(module);
  1131. Assert(module->hw);
  1132. SercomSpi *const spi_module = &(module->hw->SPI);
  1133. /* Check interrupt flag */
  1134. return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC);
  1135. }
  1136. /** @} */
  1137. /**
  1138. * \name Read/Write
  1139. * @{
  1140. */
  1141. /**
  1142. * \brief Transfers a single SPI character
  1143. *
  1144. * This function will send a single SPI character via SPI and ignore any data
  1145. * shifted in by the connected device. To both send and receive data, use the
  1146. * \ref spi_transceive_wait function or use the \ref spi_read function after
  1147. * writing a character. The \ref spi_is_ready_to_write function
  1148. * should be called before calling this function.
  1149. *
  1150. * Note that this function does not handle the SS (Slave Select)
  1151. * pin(s) in master mode; this must be handled from the user application.
  1152. *
  1153. * \note In slave mode, the data will not be transferred before a master
  1154. * initiates a transaction.
  1155. *
  1156. * \param[in] module Pointer to the software instance struct
  1157. * \param[in] tx_data Data to transmit
  1158. *
  1159. * \return Status of the procedure.
  1160. * \retval STATUS_OK If the data was written
  1161. * \retval STATUS_BUSY If the last write was not completed
  1162. */
  1163. static inline enum status_code spi_write(
  1164. struct spi_module *module,
  1165. uint16_t tx_data)
  1166. {
  1167. /* Sanity check arguments */
  1168. Assert(module);
  1169. Assert(module->hw);
  1170. SercomSpi *const spi_module = &(module->hw->SPI);
  1171. /* Check if the data register has been copied to the shift register */
  1172. if (!spi_is_ready_to_write(module)) {
  1173. /* Data register has not been copied to the shift register, return */
  1174. return STATUS_BUSY;
  1175. }
  1176. /* Write the character to the DATA register */
  1177. spi_module->DATA.reg = tx_data & SERCOM_SPI_DATA_MASK;
  1178. return STATUS_OK;
  1179. }
  1180. enum status_code spi_write_buffer_wait(
  1181. struct spi_module *const module,
  1182. const uint8_t *tx_data,
  1183. uint16_t length);
  1184. /**
  1185. * \brief Reads last received SPI character
  1186. *
  1187. * This function will return the last SPI character shifted into the receive
  1188. * register by the \ref spi_write function.
  1189. *
  1190. * \note The \ref spi_is_ready_to_read function should be called before calling
  1191. * this function.
  1192. *
  1193. * \note Receiver must be enabled in the configuration.
  1194. *
  1195. * \param[in] module Pointer to the software instance struct
  1196. * \param[out] rx_data Pointer to store the received data
  1197. *
  1198. * \returns Status of the read operation.
  1199. * \retval STATUS_OK If data was read
  1200. * \retval STATUS_ERR_IO If no data is available
  1201. * \retval STATUS_ERR_OVERFLOW If the data is overflown
  1202. */
  1203. static inline enum status_code spi_read(
  1204. struct spi_module *const module,
  1205. uint16_t *rx_data)
  1206. {
  1207. /* Sanity check arguments */
  1208. Assert(module);
  1209. Assert(module->hw);
  1210. SercomSpi *const spi_module = &(module->hw->SPI);
  1211. /* Check if data is ready to be read */
  1212. if (!spi_is_ready_to_read(module)) {
  1213. /* No data has been received, return */
  1214. return STATUS_ERR_IO;
  1215. }
  1216. /* Return value */
  1217. enum status_code retval = STATUS_OK;
  1218. /* Check if data is overflown */
  1219. if (spi_module->STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) {
  1220. retval = STATUS_ERR_OVERFLOW;
  1221. /* Clear overflow flag */
  1222. spi_module->STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
  1223. }
  1224. /* Read the character from the DATA register */
  1225. if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
  1226. *rx_data = (spi_module->DATA.reg & SERCOM_SPI_DATA_MASK);
  1227. } else {
  1228. *rx_data = (uint8_t)spi_module->DATA.reg;
  1229. }
  1230. return retval;
  1231. }
  1232. enum status_code spi_read_buffer_wait(
  1233. struct spi_module *const module,
  1234. uint8_t *rx_data,
  1235. uint16_t length,
  1236. uint16_t dummy);
  1237. enum status_code spi_transceive_wait(
  1238. struct spi_module *const module,
  1239. uint16_t tx_data,
  1240. uint16_t *rx_data);
  1241. enum status_code spi_transceive_buffer_wait(
  1242. struct spi_module *const module,
  1243. uint8_t *tx_data,
  1244. uint8_t *rx_data,
  1245. uint16_t length);
  1246. enum status_code spi_select_slave(
  1247. struct spi_module *const module,
  1248. struct spi_slave_inst *const slave,
  1249. bool select);
  1250. /** @} */
  1251. #ifdef __cplusplus
  1252. }
  1253. #endif
  1254. /** @} */
  1255. /**
  1256. * \page asfdoc_sam0_sercom_spi_extra Extra Information for SERCOM SPI Driver
  1257. *
  1258. * \section asfdoc_sam0_sercom_spi_extra_acronyms Acronyms
  1259. * Below is a table listing the acronyms used in this module, along with their
  1260. * intended meanings.
  1261. *
  1262. * <table>
  1263. * <tr>
  1264. * <th>Acronym</th>
  1265. * <th>Description</th>
  1266. * </tr>
  1267. * <tr>
  1268. * <td>SERCOM</td>
  1269. * <td>Serial Communication Interface</td>
  1270. * </tr>
  1271. * <tr>
  1272. * <td>SPI</td>
  1273. * <td>Serial Peripheral Interface</td>
  1274. * </tr>
  1275. * <tr>
  1276. * <td>SCK</td>
  1277. * <td>Serial Clock</td>
  1278. * </tr>
  1279. * <tr>
  1280. * <td>MOSI</td>
  1281. * <td>Master Output Slave Input</td>
  1282. * </tr>
  1283. * <tr>
  1284. * <td>MISO</td>
  1285. * <td>Master Input Slave Output</td>
  1286. * </tr>
  1287. * <tr>
  1288. * <td>SS</td>
  1289. * <td>Slave Select</td>
  1290. * </tr>
  1291. * <tr>
  1292. * <td>DIO</td>
  1293. * <td>Data Input Output</td>
  1294. * </tr>
  1295. * <tr>
  1296. * <td>DO</td>
  1297. * <td>Data Output</td>
  1298. * </tr>
  1299. * <tr>
  1300. * <td>DI</td>
  1301. * <td>Data Input</td>
  1302. * </tr>
  1303. * <tr>
  1304. * <td>DMA</td>
  1305. * <td>Direct Memory Access</td>
  1306. * </tr>
  1307. * </table>
  1308. *
  1309. * \section asfdoc_sam0_sercom_spi_extra_dependencies Dependencies
  1310. * The SPI driver has the following dependencies:
  1311. * \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
  1312. *
  1313. *
  1314. * \section asfdoc_sam0_sercom_spi_extra_workarounds Workarounds Implemented by Driver
  1315. * No workarounds in driver.
  1316. *
  1317. * \section asfdoc_sam0_sercom_spi_extra_history Module History
  1318. * An overview of the module history is presented in the table below, with
  1319. * details on the enhancements and fixes made to the module since its first
  1320. * release. The current version of this corresponds to the newest version in the table.
  1321. *
  1322. * <table>
  1323. * <tr>
  1324. * <th>Changelog</th>
  1325. * </tr>
  1326. * <tr>
  1327. * <td>Added new features as below:
  1328. * \li Slave select low detect
  1329. * \li Hardware slave select
  1330. * \li DMA support </td>
  1331. * </tr>
  1332. * <tr>
  1333. * <td>Edited slave part of write and transceive buffer functions to ensure
  1334. * that second character is sent at the right time</td>
  1335. * </tr>
  1336. * <tr>
  1337. * <td>Renamed the anonymous union in \c struct spi_config to
  1338. * \c mode_specific</td>
  1339. * </tr>
  1340. * <tr>
  1341. * <td>Initial Release</td>
  1342. * </tr>
  1343. * </table>
  1344. */
  1345. /**
  1346. * \page asfdoc_sam0_sercom_spi_exqsg Examples for SERCOM SPI Driver
  1347. *
  1348. * This is a list of the available Quick Start guides (QSGs) and example
  1349. * applications for \ref asfdoc_sam0_sercom_spi_group. QSGs are simple examples with
  1350. * step-by-step instructions to configure and use this driver in a selection of
  1351. * use cases. Note that a QSG can be compiled as a standalone application or be
  1352. * added to the user application.
  1353. *
  1354. * - \subpage asfdoc_sam0_sercom_spi_master_basic_use
  1355. * - \subpage asfdoc_sam0_sercom_spi_slave_basic_use
  1356. * \if SPI_CALLBACK_MODE
  1357. * - \subpage asfdoc_sam0_sercom_spi_master_callback_use
  1358. * - \subpage asfdoc_sam0_sercom_spi_slave_callback_use
  1359. * \endif
  1360. * - \subpage asfdoc_sam0_sercom_spi_dma_use_case
  1361. */
  1362. /**
  1363. * \page asfdoc_sam0_sercom_spi_mux_settings MUX Settings
  1364. *
  1365. * The following lists the possible internal SERCOM module pad function
  1366. * assignments for the four SERCOM pads in both SPI Master and SPI Slave
  1367. * modes. They are combinations of DOPO and DIPO in CTRLA.
  1368. * Note that this is in addition to the physical GPIO pin MUX of the device,
  1369. * and can be used in conjunction to optimize the serial data pin-out.
  1370. *
  1371. * \section asfdoc_sam0_sercom_spi_mux_settings_master Master Mode Settings
  1372. * The following table describes the SERCOM pin functionalities for the various
  1373. * MUX settings, whilst in SPI Master mode.
  1374. *
  1375. * \note If MISO is unlisted, the SPI receiver must not be enabled for the
  1376. * given MUX setting.
  1377. *
  1378. * <table>
  1379. * <tr>
  1380. * <th>Combination</th>
  1381. * <th>DOPO / DIPO</th>
  1382. * <th>SERCOM PAD[0]</th>
  1383. * <th>SERCOM PAD[1]</th>
  1384. * <th>SERCOM PAD[2]</th>
  1385. * <th>SERCOM PAD[3]</th>
  1386. * </tr>
  1387. * <tr>
  1388. * <td>A</td>
  1389. * <td>0x0 / 0x0</td>
  1390. * <td>MOSI</td>
  1391. * <td>SCK</td>
  1392. * <td>-</td>
  1393. * <td>-</td>
  1394. * </tr>
  1395. * <tr>
  1396. * <td>B</td>
  1397. * <td>0x0 / 0x1</td>
  1398. * <td>MOSI</td>
  1399. * <td>SCK</td>
  1400. * <td>-</td>
  1401. * <td>-</td>
  1402. * </tr>
  1403. * <tr>
  1404. * <td>C</td>
  1405. * <td>0x0 / 0x2</td>
  1406. * <td>MOSI</td>
  1407. * <td>SCK</td>
  1408. * <td>MISO</td>
  1409. * <td>-</td>
  1410. * </tr>
  1411. * <tr>
  1412. * <td>D</td>
  1413. * <td>0x0 / 0x3</td>
  1414. * <td>MOSI</td>
  1415. * <td>SCK</td>
  1416. * <td>-</td>
  1417. * <td>MISO</td>
  1418. * </tr>
  1419. * <tr>
  1420. * <td>E</td>
  1421. * <td>0x1 / 0x0</td>
  1422. * <td>MISO</td>
  1423. * <td>-</td>
  1424. * <td>MOSI</td>
  1425. * <td>SCK</td>
  1426. * </tr>
  1427. * <tr>
  1428. * <td>F</td>
  1429. * <td>0x1 / 0x1</td>
  1430. * <td>-</td>
  1431. * <td>MISO</td>
  1432. * <td>MOSI</td>
  1433. * <td>SCK</td>
  1434. * </tr>
  1435. * <tr>
  1436. * <td>G</td>
  1437. * <td>0x1 / 0x2</td>
  1438. * <td>-</td>
  1439. * <td>-</td>
  1440. * <td>MOSI</td>
  1441. * <td>SCK</td>
  1442. * </tr>
  1443. * <tr>
  1444. * <td>H</td>
  1445. * <td>0x1 / 0x3</td>
  1446. * <td>-</td>
  1447. * <td>-</td>
  1448. * <td>MOSI</td>
  1449. * <td>SCK</td>
  1450. * </tr>
  1451. * <tr>
  1452. * <td>I</td>
  1453. * <td>0x2 / 0x0</td>
  1454. * <td>MISO</td>
  1455. * <td>SCK</td>
  1456. * <td>-</td>
  1457. * <td>MOSI</td>
  1458. * </tr>
  1459. * <tr>
  1460. * <td>J</td>
  1461. * <td>0x2 / 0x1</td>
  1462. * <td>-</td>
  1463. * <td>SCK</td>
  1464. * <td>-</td>
  1465. * <td>MOSI</td>
  1466. * </tr>
  1467. * <tr>
  1468. * <td>K</td>
  1469. * <td>0x2 / 0x2</td>
  1470. * <td>-</td>
  1471. * <td>SCK</td>
  1472. * <td>MISO</td>
  1473. * <td>MOSI</td>
  1474. * </tr>
  1475. * <tr>
  1476. * <td>L</td>
  1477. * <td>0x2 / 0x3</td>
  1478. * <td>-</td>
  1479. * <td>SCK</td>
  1480. * <td>-</td>
  1481. * <td>MOSI</td>
  1482. * </tr>
  1483. * <tr>
  1484. * <td>M</td>
  1485. * <td>0x3 / 0x0</td>
  1486. * <td>MOSI</td>
  1487. * <td>-</td>
  1488. * <td>-</td>
  1489. * <td>SCK</td>
  1490. * </tr>
  1491. * <tr>
  1492. * <td>N</td>
  1493. * <td>0x3 / 0x1</td>
  1494. * <td>MOSI</td>
  1495. * <td>MISO</td>
  1496. * <td>-</td>
  1497. * <td>SCK</td>
  1498. * </tr>
  1499. * <tr>
  1500. * <td>O</td>
  1501. * <td>0x3 / 0x2</td>
  1502. * <td>MOSI</td>
  1503. * <td>-</td>
  1504. * <td>MISO</td>
  1505. * <td>SCK</td>
  1506. * </tr>
  1507. * <tr>
  1508. * <td>P</td>
  1509. * <td>0x3 / 0x3</td>
  1510. * <td>MOSI</td>
  1511. * <td>-</td>
  1512. * <td>-</td>
  1513. * <td>SCK</td>
  1514. * </tr>
  1515. * </table>
  1516. *
  1517. *
  1518. * \section asfdoc_sam0_sercom_spi_mux_settings_slave Slave Mode Settings
  1519. * The following table describes the SERCOM pin functionalities for the various
  1520. * MUX settings, whilst in SPI Slave mode.
  1521. *
  1522. * \note If MISO is unlisted, the SPI receiver must not be enabled for the
  1523. * given MUX setting.
  1524. *
  1525. * <table>
  1526. * <tr>
  1527. * <th>Combination</th>
  1528. * <th>DOPO / DIPO</th>
  1529. * <th>SERCOM PAD[0]</th>
  1530. * <th>SERCOM PAD[1]</th>
  1531. * <th>SERCOM PAD[2]</th>
  1532. * <th>SERCOM PAD[3]</th>
  1533. * </tr>
  1534. * <tr>
  1535. * <td>A</td>
  1536. * <td>0x0 / 0x0</td>
  1537. * <td>MISO</td>
  1538. * <td>SCK</td>
  1539. * <td>/SS</td>
  1540. * <td>-</td>
  1541. * </tr>
  1542. * <tr>
  1543. * <td>B</td>
  1544. * <td>0x0 / 0x1</td>
  1545. * <td>MISO</td>
  1546. * <td>SCK</td>
  1547. * <td>/SS</td>
  1548. * <td>-</td>
  1549. * </tr>
  1550. * <tr>
  1551. * <td>C</td>
  1552. * <td>0x0 / 0x2</td>
  1553. * <td>MISO</td>
  1554. * <td>SCK</td>
  1555. * <td>/SS</td>
  1556. * <td>-</td>
  1557. * </tr>
  1558. * <tr>
  1559. * <td>D</td>
  1560. * <td>0x0 / 0x3</td>
  1561. * <td>MISO</td>
  1562. * <td>SCK</td>
  1563. * <td>/SS</td>
  1564. * <td>MOSI</td>
  1565. * </tr>
  1566. * <tr>
  1567. * <td>E</td>
  1568. * <td>0x1 / 0x0</td>
  1569. * <td>MOSI</td>
  1570. * <td>/SS</td>
  1571. * <td>MISO</td>
  1572. * <td>SCK</td>
  1573. * </tr>
  1574. * <tr>
  1575. * <td>F</td>
  1576. * <td>0x1 / 0x1</td>
  1577. * <td>-</td>
  1578. * <td>/SS</td>
  1579. * <td>MISO</td>
  1580. * <td>SCK</td>
  1581. * </tr>
  1582. * <tr>
  1583. * <td>G</td>
  1584. * <td>0x1 / 0x2</td>
  1585. * <td>-</td>
  1586. * <td>/SS</td>
  1587. * <td>MISO</td>
  1588. * <td>SCK</td>
  1589. * </tr>
  1590. * <tr>
  1591. * <td>H</td>
  1592. * <td>0x1 / 0x3</td>
  1593. * <td>-</td>
  1594. * <td>/SS</td>
  1595. * <td>MISO</td>
  1596. * <td>SCK</td>
  1597. * </tr>
  1598. * <tr>
  1599. * <td>I</td>
  1600. * <td>0x2 / 0x0</td>
  1601. * <td>MOSI</td>
  1602. * <td>SCK</td>
  1603. * <td>/SS</td>
  1604. * <td>MISO</td>
  1605. * </tr>
  1606. * <tr>
  1607. * <td>J</td>
  1608. * <td>0x2 / 0x1</td>
  1609. * <td>-</td>
  1610. * <td>SCK</td>
  1611. * <td>/SS</td>
  1612. * <td>MISO</td>
  1613. * </tr>
  1614. * <tr>
  1615. * <td>K</td>
  1616. * <td>0x2 / 0x2</td>
  1617. * <td>-</td>
  1618. * <td>SCK</td>
  1619. * <td>/SS</td>
  1620. * <td>MISO</td>
  1621. * </tr>
  1622. * <tr>
  1623. * <td>L</td>
  1624. * <td>0x2 / 0x3</td>
  1625. * <td>-</td>
  1626. * <td>SCK</td>
  1627. * <td>/SS</td>
  1628. * <td>MISO</td>
  1629. * </tr>
  1630. * <tr>
  1631. * <td>M</td>
  1632. * <td>0x3 / 0x0</td>
  1633. * <td>MISO</td>
  1634. * <td>/SS</td>
  1635. * <td>-</td>
  1636. * <td>SCK</td>
  1637. * </tr>
  1638. * <tr>
  1639. * <td>N</td>
  1640. * <td>0x3 / 0x1</td>
  1641. * <td>MISO</td>
  1642. * <td>/SS</td>
  1643. * <td>-</td>
  1644. * <td>SCK</td>
  1645. * </tr>
  1646. * <tr>
  1647. * <td>O</td>
  1648. * <td>0x3 / 0x2</td>
  1649. * <td>MISO</td>
  1650. * <td>/SS</td>
  1651. * <td>MOSI</td>
  1652. * <td>SCK</td>
  1653. * </tr>
  1654. * <tr>
  1655. * <td>P</td>
  1656. * <td>0x3 / 0x3</td>
  1657. * <td>MISO</td>
  1658. * <td>/SS</td>
  1659. * <td>-</td>
  1660. * <td>SCK</td>
  1661. * </tr>
  1662. * </table>
  1663. *
  1664. *
  1665. *
  1666. * \page asfdoc_sam0_sercom_spi_document_revision_history Document Revision History
  1667. *
  1668. * <table>
  1669. * <tr>
  1670. * <th>Doc. Rev.</th>
  1671. * <th>Date</th>
  1672. * <th>Comments</th>
  1673. * </tr>
  1674. * <tr>
  1675. * <td>42115E</td>
  1676. * <td>12/2015</td>
  1677. * <td>Add SAM L21/L22, SAM DA1, SAM D09, SAMR30 and SAM C21 support</td>
  1678. * </tr>
  1679. * <tr>
  1680. * <td>42115D</td>
  1681. * <td>12/2014</td>
  1682. * <td>Add SAM R21/D10/D11 support</td>
  1683. * </tr>
  1684. * <tr>
  1685. * <td>42115C</td>
  1686. * <td>01/2014</td>
  1687. * <td>Add SAM D21 support</td>
  1688. * </tr>
  1689. * <tr>
  1690. * <td>42115B</td>
  1691. * <td>11/2013</td>
  1692. * <td>Replaced the pad multiplexing documentation with a condensed table</td>
  1693. * </tr>
  1694. * <tr>
  1695. * <td>42115A</td>
  1696. * <td>06/2013</td>
  1697. * <td>Initial release</td>
  1698. * </tr>
  1699. * </table>
  1700. */
  1701. #endif /* SPI_H_INCLUDED */