drv_pulse_encoder.c 8.8 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-08-23 balanceTWK first version
  9. */
  10. #include "board.h"
  11. #include "drv_config.h"
  12. #ifdef RT_USING_PULSE_ENCODER
  13. //#define DRV_DEBUG
  14. #define LOG_TAG "drv.pulse_encoder"
  15. #include <drv_log.h>
  16. #if !defined(BSP_USING_PULSE_ENCODER1) && !defined(BSP_USING_PULSE_ENCODER2) && !defined(BSP_USING_PULSE_ENCODER3) \
  17. && !defined(BSP_USING_PULSE_ENCODER4) && !defined(BSP_USING_PULSE_ENCODER5) && !defined(BSP_USING_PULSE_ENCODER6)
  18. #error "Please define at least one BSP_USING_PULSE_ENCODERx"
  19. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  20. #endif
  21. #define AUTO_RELOAD_VALUE 0x7FFF
  22. enum
  23. {
  24. #ifdef BSP_USING_PULSE_ENCODER1
  25. PULSE_ENCODER1_INDEX,
  26. #endif
  27. #ifdef BSP_USING_PULSE_ENCODER2
  28. PULSE_ENCODER2_INDEX,
  29. #endif
  30. #ifdef BSP_USING_PULSE_ENCODER3
  31. PULSE_ENCODER3_INDEX,
  32. #endif
  33. #ifdef BSP_USING_PULSE_ENCODER4
  34. PULSE_ENCODER4_INDEX,
  35. #endif
  36. #ifdef BSP_USING_PULSE_ENCODER5
  37. PULSE_ENCODER5_INDEX,
  38. #endif
  39. #ifdef BSP_USING_PULSE_ENCODER6
  40. PULSE_ENCODER6_INDEX,
  41. #endif
  42. };
  43. struct stm32_pulse_encoder_device
  44. {
  45. struct rt_pulse_encoder_device pulse_encoder;
  46. TIM_HandleTypeDef tim_handler;
  47. IRQn_Type encoder_irqn;
  48. rt_int32_t over_under_flowcount;
  49. char *name;
  50. };
  51. static struct stm32_pulse_encoder_device stm32_pulse_encoder_obj[] =
  52. {
  53. #ifdef BSP_USING_PULSE_ENCODER1
  54. PULSE_ENCODER1_CONFIG,
  55. #endif
  56. #ifdef BSP_USING_PULSE_ENCODER2
  57. PULSE_ENCODER2_CONFIG,
  58. #endif
  59. #ifdef BSP_USING_PULSE_ENCODER3
  60. PULSE_ENCODER3_CONFIG,
  61. #endif
  62. #ifdef BSP_USING_PULSE_ENCODER4
  63. PULSE_ENCODER4_CONFIG,
  64. #endif
  65. #ifdef BSP_USING_PULSE_ENCODER5
  66. PULSE_ENCODER5_CONFIG,
  67. #endif
  68. #ifdef BSP_USING_PULSE_ENCODER6
  69. PULSE_ENCODER6_CONFIG,
  70. #endif
  71. };
  72. rt_err_t pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
  73. {
  74. TIM_Encoder_InitTypeDef sConfig;
  75. TIM_MasterConfigTypeDef sMasterConfig;
  76. struct stm32_pulse_encoder_device *stm32_device;
  77. stm32_device = (struct stm32_pulse_encoder_device*)pulse_encoder;
  78. stm32_device->tim_handler.Init.Prescaler = 0;
  79. stm32_device->tim_handler.Init.CounterMode = TIM_COUNTERMODE_UP;
  80. stm32_device->tim_handler.Init.Period = AUTO_RELOAD_VALUE;
  81. stm32_device->tim_handler.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  82. stm32_device->tim_handler.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
  83. sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
  84. sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
  85. sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
  86. sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
  87. sConfig.IC1Filter = 3;
  88. sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
  89. sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
  90. sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
  91. sConfig.IC2Filter = 3;
  92. if (HAL_TIM_Encoder_Init(&stm32_device->tim_handler, &sConfig) != HAL_OK)
  93. {
  94. LOG_E("pulse_encoder init failed");
  95. return -RT_ERROR;
  96. }
  97. sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
  98. sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  99. if (HAL_TIMEx_MasterConfigSynchronization(&stm32_device->tim_handler, &sMasterConfig))
  100. {
  101. LOG_E("TIMx master config failed");
  102. return -RT_ERROR;
  103. }
  104. else
  105. {
  106. HAL_NVIC_SetPriority(stm32_device->encoder_irqn, 3, 0);
  107. /* enable the TIMx global Interrupt */
  108. HAL_NVIC_EnableIRQ(stm32_device->encoder_irqn);
  109. /* clear update flag */
  110. __HAL_TIM_CLEAR_FLAG(&stm32_device->tim_handler, TIM_FLAG_UPDATE);
  111. /* enable update request source */
  112. __HAL_TIM_URS_ENABLE(&stm32_device->tim_handler);
  113. }
  114. return RT_EOK;
  115. }
  116. rt_err_t pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
  117. {
  118. struct stm32_pulse_encoder_device *stm32_device;
  119. stm32_device = (struct stm32_pulse_encoder_device*)pulse_encoder;
  120. stm32_device->over_under_flowcount = 0;
  121. __HAL_TIM_SET_COUNTER(&stm32_device->tim_handler, 0);
  122. return RT_EOK;
  123. }
  124. rt_int32_t pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
  125. {
  126. struct stm32_pulse_encoder_device *stm32_device;
  127. stm32_device = (struct stm32_pulse_encoder_device*)pulse_encoder;
  128. return (rt_int32_t)((rt_int16_t)__HAL_TIM_GET_COUNTER(&stm32_device->tim_handler) + stm32_device->over_under_flowcount * AUTO_RELOAD_VALUE);
  129. }
  130. rt_err_t pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
  131. {
  132. rt_err_t result;
  133. struct stm32_pulse_encoder_device *stm32_device;
  134. stm32_device = (struct stm32_pulse_encoder_device*)pulse_encoder;
  135. result = RT_EOK;
  136. switch (cmd)
  137. {
  138. case PULSE_ENCODER_CMD_ENABLE:
  139. HAL_TIM_Encoder_Start(&stm32_device->tim_handler, TIM_CHANNEL_ALL);
  140. HAL_TIM_Encoder_Start_IT(&stm32_device->tim_handler, TIM_CHANNEL_ALL);
  141. break;
  142. case PULSE_ENCODER_CMD_DISABLE:
  143. HAL_TIM_Encoder_Stop(&stm32_device->tim_handler, TIM_CHANNEL_ALL);
  144. HAL_TIM_Encoder_Stop_IT(&stm32_device->tim_handler, TIM_CHANNEL_ALL);
  145. break;
  146. default:
  147. result = -RT_ENOSYS;
  148. break;
  149. }
  150. return result;
  151. }
  152. void pulse_encoder_update_isr(struct stm32_pulse_encoder_device *device)
  153. {
  154. /* TIM Update event */
  155. if (__HAL_TIM_GET_FLAG(&device->tim_handler, TIM_FLAG_UPDATE) != RESET)
  156. {
  157. __HAL_TIM_CLEAR_IT(&device->tim_handler, TIM_IT_UPDATE);
  158. if (__HAL_TIM_IS_TIM_COUNTING_DOWN(&device->tim_handler))
  159. {
  160. device->over_under_flowcount--;
  161. }
  162. else
  163. {
  164. device->over_under_flowcount++;
  165. }
  166. }
  167. /* Capture compare 1 event */
  168. if (__HAL_TIM_GET_FLAG(&device->tim_handler, TIM_FLAG_CC1) != RESET)
  169. {
  170. __HAL_TIM_CLEAR_IT(&device->tim_handler, TIM_IT_CC1);
  171. }
  172. /* Capture compare 2 event */
  173. if (__HAL_TIM_GET_FLAG(&device->tim_handler, TIM_FLAG_CC2) != RESET)
  174. {
  175. __HAL_TIM_CLEAR_IT(&device->tim_handler, TIM_IT_CC2);
  176. }
  177. /* Capture compare 3 event */
  178. if (__HAL_TIM_GET_FLAG(&device->tim_handler, TIM_FLAG_CC3) != RESET)
  179. {
  180. __HAL_TIM_CLEAR_IT(&device->tim_handler, TIM_IT_CC3);
  181. }
  182. /* Capture compare 4 event */
  183. if (__HAL_TIM_GET_FLAG(&device->tim_handler, TIM_FLAG_CC4) != RESET)
  184. {
  185. __HAL_TIM_CLEAR_IT(&device->tim_handler, TIM_IT_CC4);
  186. }
  187. /* TIM Break input event */
  188. if (__HAL_TIM_GET_FLAG(&device->tim_handler, TIM_FLAG_BREAK) != RESET)
  189. {
  190. __HAL_TIM_CLEAR_IT(&device->tim_handler, TIM_IT_BREAK);
  191. }
  192. /* TIM Trigger detection event */
  193. if (__HAL_TIM_GET_FLAG(&device->tim_handler, TIM_FLAG_TRIGGER) != RESET)
  194. {
  195. __HAL_TIM_CLEAR_IT(&device->tim_handler, TIM_IT_TRIGGER);
  196. }
  197. /* TIM commutation event */
  198. if (__HAL_TIM_GET_FLAG(&device->tim_handler, TIM_FLAG_COM) != RESET)
  199. {
  200. __HAL_TIM_CLEAR_IT(&device->tim_handler, TIM_FLAG_COM);
  201. }
  202. }
  203. #ifdef BSP_USING_PULSE_ENCODER1
  204. #if defined(SOC_SERIES_STM32F4)
  205. void TIM1_UP_TIM10_IRQHandler(void)
  206. #elif defined(SOC_SERIES_STM32F1)
  207. void TIM1_UP_IRQHandler(void)
  208. #else
  209. #error "Please check TIM1's IRQHandler"
  210. #endif
  211. {
  212. /* enter interrupt */
  213. rt_interrupt_enter();
  214. pulse_encoder_update_isr(&stm32_pulse_encoder_obj[PULSE_ENCODER1_INDEX]);
  215. /* leave interrupt */
  216. rt_interrupt_leave();
  217. }
  218. #endif
  219. #ifdef BSP_USING_PULSE_ENCODER2
  220. void TIM2_IRQHandler(void)
  221. {
  222. /* enter interrupt */
  223. rt_interrupt_enter();
  224. pulse_encoder_update_isr(&stm32_pulse_encoder_obj[PULSE_ENCODER2_INDEX]);
  225. /* leave interrupt */
  226. rt_interrupt_leave();
  227. }
  228. #endif
  229. #ifdef BSP_USING_PULSE_ENCODER3
  230. void TIM3_IRQHandler(void)
  231. {
  232. /* enter interrupt */
  233. rt_interrupt_enter();
  234. pulse_encoder_update_isr(&stm32_pulse_encoder_obj[PULSE_ENCODER3_INDEX]);
  235. /* leave interrupt */
  236. rt_interrupt_leave();
  237. }
  238. #endif
  239. #ifdef BSP_USING_PULSE_ENCODER4
  240. void TIM4_IRQHandler(void)
  241. {
  242. /* enter interrupt */
  243. rt_interrupt_enter();
  244. pulse_encoder_update_isr(&stm32_pulse_encoder_obj[PULSE_ENCODER4_INDEX]);
  245. /* leave interrupt */
  246. rt_interrupt_leave();
  247. }
  248. #endif
  249. static const struct rt_pulse_encoder_ops _ops =
  250. {
  251. .init = pulse_encoder_init,
  252. .get_count = pulse_encoder_get_count,
  253. .clear_count = pulse_encoder_clear_count,
  254. .control = pulse_encoder_control,
  255. };
  256. int hw_pulse_encoder_init(void)
  257. {
  258. int i;
  259. int result;
  260. result = RT_EOK;
  261. for (i = 0; i < sizeof(stm32_pulse_encoder_obj) / sizeof(stm32_pulse_encoder_obj[0]); i++)
  262. {
  263. stm32_pulse_encoder_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
  264. stm32_pulse_encoder_obj[i].pulse_encoder.ops = &_ops;
  265. if (rt_device_pulse_encoder_register(&stm32_pulse_encoder_obj[i].pulse_encoder, stm32_pulse_encoder_obj[i].name, RT_NULL) != RT_EOK)
  266. {
  267. LOG_E("%s register failed", stm32_pulse_encoder_obj[i].name);
  268. result = -RT_ERROR;
  269. }
  270. }
  271. return result;
  272. }
  273. INIT_BOARD_EXPORT(hw_pulse_encoder_init);
  274. #endif