drv_pwm.c 19 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-13 zylx first version
  9. * 2021-01-23 thread-liu Fix the timer clock frequency doubling problem
  10. */
  11. #include <board.h>
  12. #ifdef RT_USING_PWM
  13. #include "drv_config.h"
  14. #include <drivers/rt_drv_pwm.h>
  15. //#define DRV_DEBUG
  16. #define LOG_TAG "drv.pwm"
  17. #include <drv_log.h>
  18. #define MAX_PERIOD 65535
  19. #define MIN_PERIOD 3
  20. #define MIN_PULSE 2
  21. extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
  22. enum
  23. {
  24. #ifdef BSP_USING_PWM1
  25. PWM1_INDEX,
  26. #endif
  27. #ifdef BSP_USING_PWM2
  28. PWM2_INDEX,
  29. #endif
  30. #ifdef BSP_USING_PWM3
  31. PWM3_INDEX,
  32. #endif
  33. #ifdef BSP_USING_PWM4
  34. PWM4_INDEX,
  35. #endif
  36. #ifdef BSP_USING_PWM5
  37. PWM5_INDEX,
  38. #endif
  39. #ifdef BSP_USING_PWM6
  40. PWM6_INDEX,
  41. #endif
  42. #ifdef BSP_USING_PWM7
  43. PWM7_INDEX,
  44. #endif
  45. #ifdef BSP_USING_PWM8
  46. PWM8_INDEX,
  47. #endif
  48. #ifdef BSP_USING_PWM9
  49. PWM9_INDEX,
  50. #endif
  51. #ifdef BSP_USING_PWM10
  52. PWM10_INDEX,
  53. #endif
  54. #ifdef BSP_USING_PWM11
  55. PWM11_INDEX,
  56. #endif
  57. #ifdef BSP_USING_PWM12
  58. PWM12_INDEX,
  59. #endif
  60. #ifdef BSP_USING_PWM13
  61. PWM13_INDEX,
  62. #endif
  63. #ifdef BSP_USING_PWM14
  64. PWM14_INDEX,
  65. #endif
  66. #ifdef BSP_USING_PWM15
  67. PWM15_INDEX,
  68. #endif
  69. #ifdef BSP_USING_PWM16
  70. PWM16_INDEX,
  71. #endif
  72. #ifdef BSP_USING_PWM17
  73. PWM17_INDEX,
  74. #endif
  75. };
  76. struct stm32_pwm
  77. {
  78. struct rt_device_pwm pwm_device;
  79. TIM_HandleTypeDef tim_handle;
  80. rt_uint8_t channel;
  81. char *name;
  82. };
  83. static struct stm32_pwm stm32_pwm_obj[] =
  84. {
  85. #ifdef BSP_USING_PWM1
  86. PWM1_CONFIG,
  87. #endif
  88. #ifdef BSP_USING_PWM2
  89. PWM2_CONFIG,
  90. #endif
  91. #ifdef BSP_USING_PWM3
  92. PWM3_CONFIG,
  93. #endif
  94. #ifdef BSP_USING_PWM4
  95. PWM4_CONFIG,
  96. #endif
  97. #ifdef BSP_USING_PWM5
  98. PWM5_CONFIG,
  99. #endif
  100. #ifdef BSP_USING_PWM6
  101. PWM6_CONFIG,
  102. #endif
  103. #ifdef BSP_USING_PWM7
  104. PWM7_CONFIG,
  105. #endif
  106. #ifdef BSP_USING_PWM8
  107. PWM8_CONFIG,
  108. #endif
  109. #ifdef BSP_USING_PWM9
  110. PWM9_CONFIG,
  111. #endif
  112. #ifdef BSP_USING_PWM10
  113. PWM10_CONFIG,
  114. #endif
  115. #ifdef BSP_USING_PWM11
  116. PWM11_CONFIG,
  117. #endif
  118. #ifdef BSP_USING_PWM12
  119. PWM12_CONFIG,
  120. #endif
  121. #ifdef BSP_USING_PWM13
  122. PWM13_CONFIG,
  123. #endif
  124. #ifdef BSP_USING_PWM14
  125. PWM14_CONFIG,
  126. #endif
  127. #ifdef BSP_USING_PWM15
  128. PWM15_CONFIG,
  129. #endif
  130. #ifdef BSP_USING_PWM16
  131. PWM16_CONFIG,
  132. #endif
  133. #ifdef BSP_USING_PWM17
  134. PWM17_CONFIG,
  135. #endif
  136. };
  137. /* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
  138. static void pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
  139. {
  140. uint32_t flatency = 0;
  141. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  142. RT_ASSERT(pclk1_doubler != RT_NULL);
  143. RT_ASSERT(pclk1_doubler != RT_NULL);
  144. HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
  145. *pclk1_doubler = 1;
  146. *pclk2_doubler = 1;
  147. #if defined(SOC_SERIES_STM32MP1)
  148. if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
  149. {
  150. *pclk1_doubler = 2;
  151. }
  152. if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
  153. {
  154. *pclk2_doubler = 2;
  155. }
  156. #else
  157. if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
  158. {
  159. *pclk1_doubler = 2;
  160. }
  161. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  162. if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
  163. {
  164. *pclk2_doubler = 2;
  165. }
  166. #endif
  167. #endif
  168. }
  169. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
  170. static struct rt_pwm_ops drv_ops =
  171. {
  172. drv_pwm_control
  173. };
  174. static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
  175. {
  176. /* Converts the channel number to the channel number of Hal library */
  177. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  178. if (!configuration->complementary)
  179. {
  180. if (!enable)
  181. {
  182. HAL_TIM_PWM_Stop(htim, channel);
  183. }
  184. else
  185. {
  186. HAL_TIM_PWM_Start(htim, channel);
  187. }
  188. }
  189. else if (configuration->complementary)
  190. {
  191. if (!enable)
  192. {
  193. HAL_TIMEx_PWMN_Stop(htim, channel);
  194. }
  195. else
  196. {
  197. HAL_TIMEx_PWMN_Start(htim, channel);
  198. }
  199. }
  200. return RT_EOK;
  201. }
  202. static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  203. {
  204. /* Converts the channel number to the channel number of Hal library */
  205. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  206. rt_uint64_t tim_clock;
  207. rt_uint32_t pclk1_doubler, pclk2_doubler;
  208. pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  209. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  210. if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
  211. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)
  212. if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
  213. #elif defined(SOC_SERIES_STM32MP1)
  214. if (htim->Instance == TIM4)
  215. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  216. if (0)
  217. #endif
  218. {
  219. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  220. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler);
  221. #endif
  222. }
  223. else
  224. {
  225. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler);
  226. }
  227. if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2)
  228. {
  229. tim_clock = tim_clock / 2;
  230. }
  231. else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4)
  232. {
  233. tim_clock = tim_clock / 4;
  234. }
  235. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  236. tim_clock /= 1000000UL;
  237. configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  238. configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  239. return RT_EOK;
  240. }
  241. static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  242. {
  243. rt_uint32_t period, pulse;
  244. rt_uint64_t tim_clock, psc;
  245. rt_uint32_t pclk1_doubler, pclk2_doubler;
  246. /* Converts the channel number to the channel number of Hal library */
  247. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  248. pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  249. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  250. if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
  251. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)|| defined(SOC_SERIES_STM32F3)
  252. if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
  253. #elif defined(SOC_SERIES_STM32MP1)
  254. if (htim->Instance == TIM4)
  255. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  256. if (0)
  257. #endif
  258. {
  259. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  260. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler);
  261. #endif
  262. }
  263. else
  264. {
  265. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler);
  266. }
  267. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  268. tim_clock /= 1000000UL;
  269. period = (unsigned long long)configuration->period * tim_clock / 1000ULL ;
  270. psc = period / MAX_PERIOD + 1;
  271. period = period / psc;
  272. __HAL_TIM_SET_PRESCALER(htim, psc - 1);
  273. if (period < MIN_PERIOD)
  274. {
  275. period = MIN_PERIOD;
  276. }
  277. __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
  278. pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL;
  279. if (pulse < MIN_PULSE)
  280. {
  281. pulse = MIN_PULSE;
  282. }
  283. else if (pulse > period)
  284. {
  285. pulse = period;
  286. }
  287. __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
  288. /* If you want the PWM setting to take effect immediately,
  289. please uncommon the following code, but it will cause the last PWM cycle not complete. */
  290. //__HAL_TIM_SET_COUNTER(htim, 0);
  291. //HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE); /* Update frequency value */
  292. return RT_EOK;
  293. }
  294. static rt_err_t drv_pwm_set_period(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  295. {
  296. rt_uint32_t period;
  297. rt_uint64_t tim_clock, psc;
  298. rt_uint32_t pclk1_doubler, pclk2_doubler;
  299. pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  300. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  301. if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
  302. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)|| defined(SOC_SERIES_STM32F3)
  303. if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
  304. #elif defined(SOC_SERIES_STM32MP1)
  305. if (htim->Instance == TIM4)
  306. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  307. if (0)
  308. #endif
  309. {
  310. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  311. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler);
  312. #endif
  313. }
  314. else
  315. {
  316. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler);
  317. }
  318. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  319. tim_clock /= 1000000UL;
  320. period = (unsigned long long)configuration->period * tim_clock / 1000ULL ;
  321. psc = period / MAX_PERIOD + 1;
  322. period = period / psc;
  323. __HAL_TIM_SET_PRESCALER(htim, psc - 1);
  324. if (period < MIN_PERIOD)
  325. {
  326. period = MIN_PERIOD;
  327. }
  328. __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
  329. return RT_EOK;
  330. }
  331. static rt_err_t drv_pwm_set_pulse(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
  332. {
  333. rt_uint32_t period, pulse;
  334. rt_uint64_t tim_clock;
  335. rt_uint32_t pclk1_doubler, pclk2_doubler;
  336. /* Converts the channel number to the channel number of Hal library */
  337. rt_uint32_t channel = 0x04 * (configuration->channel - 1);
  338. pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  339. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  340. if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
  341. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)|| defined(SOC_SERIES_STM32F3)
  342. if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
  343. #elif defined(SOC_SERIES_STM32MP1)
  344. if (htim->Instance == TIM4)
  345. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  346. if (0)
  347. #endif
  348. {
  349. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  350. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler);
  351. #endif
  352. }
  353. else
  354. {
  355. tim_clock = (rt_uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler);
  356. }
  357. /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
  358. tim_clock /= 1000000UL;
  359. period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
  360. pulse = (unsigned long long)configuration->pulse * (__HAL_TIM_GET_AUTORELOAD(htim) + 1) / period;
  361. if (pulse < MIN_PULSE)
  362. {
  363. pulse = MIN_PULSE;
  364. }
  365. else if (pulse > period)
  366. {
  367. pulse = period;
  368. }
  369. __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
  370. return RT_EOK;
  371. }
  372. static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
  373. {
  374. struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
  375. TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data;
  376. switch (cmd)
  377. {
  378. case PWMN_CMD_ENABLE:
  379. configuration->complementary = RT_TRUE;
  380. case PWM_CMD_ENABLE:
  381. return drv_pwm_enable(htim, configuration, RT_TRUE);
  382. case PWMN_CMD_DISABLE:
  383. configuration->complementary = RT_FALSE;
  384. case PWM_CMD_DISABLE:
  385. return drv_pwm_enable(htim, configuration, RT_FALSE);
  386. case PWM_CMD_SET:
  387. return drv_pwm_set(htim, configuration);
  388. case PWM_CMD_SET_PERIOD:
  389. return drv_pwm_set_period(htim, configuration);
  390. case PWM_CMD_SET_PULSE:
  391. return drv_pwm_set_pulse(htim, configuration);
  392. case PWM_CMD_GET:
  393. return drv_pwm_get(htim, configuration);
  394. default:
  395. return RT_EINVAL;
  396. }
  397. }
  398. static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
  399. {
  400. rt_err_t result = RT_EOK;
  401. TIM_HandleTypeDef *tim = RT_NULL;
  402. TIM_OC_InitTypeDef oc_config = {0};
  403. TIM_MasterConfigTypeDef master_config = {0};
  404. TIM_ClockConfigTypeDef clock_config = {0};
  405. RT_ASSERT(device != RT_NULL);
  406. tim = (TIM_HandleTypeDef *)&device->tim_handle;
  407. /* configure the timer to pwm mode */
  408. tim->Init.Prescaler = 0;
  409. tim->Init.CounterMode = TIM_COUNTERMODE_UP;
  410. tim->Init.Period = 0;
  411. tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  412. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
  413. tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  414. #endif
  415. if (HAL_TIM_Base_Init(tim) != HAL_OK)
  416. {
  417. LOG_E("%s pwm init failed", device->name);
  418. result = -RT_ERROR;
  419. goto __exit;
  420. }
  421. if (HAL_TIM_PWM_Init(tim) != HAL_OK)
  422. {
  423. LOG_E("%s pwm init failed", device->name);
  424. result = -RT_ERROR;
  425. goto __exit;
  426. }
  427. clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
  428. if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK)
  429. {
  430. LOG_E("%s clock init failed", device->name);
  431. result = -RT_ERROR;
  432. goto __exit;
  433. }
  434. master_config.MasterOutputTrigger = TIM_TRGO_RESET;
  435. master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
  436. if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
  437. {
  438. LOG_E("%s master config failed", device->name);
  439. result = -RT_ERROR;
  440. goto __exit;
  441. }
  442. oc_config.OCMode = TIM_OCMODE_PWM1;
  443. oc_config.Pulse = 0;
  444. oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
  445. oc_config.OCFastMode = TIM_OCFAST_DISABLE;
  446. oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
  447. oc_config.OCIdleState = TIM_OCIDLESTATE_RESET;
  448. /* config pwm channel */
  449. if (device->channel & 0x01)
  450. {
  451. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK)
  452. {
  453. LOG_E("%s channel1 config failed", device->name);
  454. result = -RT_ERROR;
  455. goto __exit;
  456. }
  457. }
  458. if (device->channel & 0x02)
  459. {
  460. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK)
  461. {
  462. LOG_E("%s channel2 config failed", device->name);
  463. result = -RT_ERROR;
  464. goto __exit;
  465. }
  466. }
  467. if (device->channel & 0x04)
  468. {
  469. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK)
  470. {
  471. LOG_E("%s channel3 config failed", device->name);
  472. result = -RT_ERROR;
  473. goto __exit;
  474. }
  475. }
  476. if (device->channel & 0x08)
  477. {
  478. if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK)
  479. {
  480. LOG_E("%s channel4 config failed", device->name);
  481. result = -RT_ERROR;
  482. goto __exit;
  483. }
  484. }
  485. /* pwm pin configuration */
  486. HAL_TIM_MspPostInit(tim);
  487. /* enable update request source */
  488. __HAL_TIM_URS_ENABLE(tim);
  489. __exit:
  490. return result;
  491. }
  492. static void pwm_get_channel(void)
  493. {
  494. #ifdef BSP_USING_PWM1_CH1
  495. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
  496. #endif
  497. #ifdef BSP_USING_PWM1_CH2
  498. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
  499. #endif
  500. #ifdef BSP_USING_PWM1_CH3
  501. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
  502. #endif
  503. #ifdef BSP_USING_PWM1_CH4
  504. stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
  505. #endif
  506. #ifdef BSP_USING_PWM2_CH1
  507. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
  508. #endif
  509. #ifdef BSP_USING_PWM2_CH2
  510. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
  511. #endif
  512. #ifdef BSP_USING_PWM2_CH3
  513. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
  514. #endif
  515. #ifdef BSP_USING_PWM2_CH4
  516. stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
  517. #endif
  518. #ifdef BSP_USING_PWM3_CH1
  519. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
  520. #endif
  521. #ifdef BSP_USING_PWM3_CH2
  522. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
  523. #endif
  524. #ifdef BSP_USING_PWM3_CH3
  525. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
  526. #endif
  527. #ifdef BSP_USING_PWM3_CH4
  528. stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
  529. #endif
  530. #ifdef BSP_USING_PWM4_CH1
  531. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
  532. #endif
  533. #ifdef BSP_USING_PWM4_CH2
  534. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
  535. #endif
  536. #ifdef BSP_USING_PWM4_CH3
  537. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
  538. #endif
  539. #ifdef BSP_USING_PWM4_CH4
  540. stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
  541. #endif
  542. #ifdef BSP_USING_PWM5_CH1
  543. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
  544. #endif
  545. #ifdef BSP_USING_PWM5_CH2
  546. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
  547. #endif
  548. #ifdef BSP_USING_PWM5_CH3
  549. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
  550. #endif
  551. #ifdef BSP_USING_PWM5_CH4
  552. stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
  553. #endif
  554. #ifdef BSP_USING_PWM6_CH1
  555. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
  556. #endif
  557. #ifdef BSP_USING_PWM6_CH2
  558. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
  559. #endif
  560. #ifdef BSP_USING_PWM6_CH3
  561. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
  562. #endif
  563. #ifdef BSP_USING_PWM6_CH4
  564. stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
  565. #endif
  566. #ifdef BSP_USING_PWM7_CH1
  567. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
  568. #endif
  569. #ifdef BSP_USING_PWM7_CH2
  570. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
  571. #endif
  572. #ifdef BSP_USING_PWM7_CH3
  573. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
  574. #endif
  575. #ifdef BSP_USING_PWM7_CH4
  576. stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
  577. #endif
  578. #ifdef BSP_USING_PWM8_CH1
  579. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
  580. #endif
  581. #ifdef BSP_USING_PWM8_CH2
  582. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
  583. #endif
  584. #ifdef BSP_USING_PWM8_CH3
  585. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
  586. #endif
  587. #ifdef BSP_USING_PWM8_CH4
  588. stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
  589. #endif
  590. #ifdef BSP_USING_PWM9_CH1
  591. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
  592. #endif
  593. #ifdef BSP_USING_PWM9_CH2
  594. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
  595. #endif
  596. #ifdef BSP_USING_PWM9_CH3
  597. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
  598. #endif
  599. #ifdef BSP_USING_PWM9_CH4
  600. stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
  601. #endif
  602. #ifdef BSP_USING_PWM10_CH1
  603. stm32_pwm_obj[PWM10_INDEX].channel |= 1 << 0;
  604. #endif
  605. #ifdef BSP_USING_PWM11_CH1
  606. stm32_pwm_obj[PWM11_INDEX].channel |= 1 << 0;
  607. #endif
  608. #ifdef BSP_USING_PWM12_CH1
  609. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
  610. #endif
  611. #ifdef BSP_USING_PWM12_CH2
  612. stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
  613. #endif
  614. #ifdef BSP_USING_PWM16_CH1
  615. stm32_pwm_obj[PWM16_INDEX].channel |= 1 << 0;
  616. #endif
  617. #ifdef BSP_USING_PWM17_CH1
  618. stm32_pwm_obj[PWM17_INDEX].channel |= 1 << 0;
  619. #endif
  620. }
  621. static int stm32_pwm_init(void)
  622. {
  623. int i = 0;
  624. int result = RT_EOK;
  625. pwm_get_channel();
  626. for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++)
  627. {
  628. /* pwm init */
  629. if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK)
  630. {
  631. LOG_E("%s init failed", stm32_pwm_obj[i].name);
  632. result = -RT_ERROR;
  633. goto __exit;
  634. }
  635. else
  636. {
  637. LOG_D("%s init success", stm32_pwm_obj[i].name);
  638. /* register pwm device */
  639. if (rt_device_pwm_register(&stm32_pwm_obj[i].pwm_device, stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK)
  640. {
  641. LOG_D("%s register success", stm32_pwm_obj[i].name);
  642. }
  643. else
  644. {
  645. LOG_E("%s register failed", stm32_pwm_obj[i].name);
  646. result = -RT_ERROR;
  647. }
  648. }
  649. }
  650. __exit:
  651. return result;
  652. }
  653. INIT_DEVICE_EXPORT(stm32_pwm_init);
  654. #endif /* RT_USING_PWM */