drv_usart_v2.c 34 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-06-01 KyleChan first version
  9. */
  10. #include "board.h"
  11. #include "drv_usart_v2.h"
  12. #ifdef RT_USING_SERIAL_V2
  13. //#define DRV_DEBUG
  14. #define DBG_TAG "drv.usart"
  15. #ifdef DRV_DEBUG
  16. #define DBG_LVL DBG_LOG
  17. #else
  18. #define DBG_LVL DBG_INFO
  19. #endif /* DRV_DEBUG */
  20. #include <rtdbg.h>
  21. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
  22. !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
  23. !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
  24. #error "Please define at least one BSP_USING_UARTx"
  25. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  26. #endif
  27. #ifdef RT_SERIAL_USING_DMA
  28. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  29. #endif
  30. enum
  31. {
  32. #ifdef BSP_USING_UART1
  33. UART1_INDEX,
  34. #endif
  35. #ifdef BSP_USING_UART2
  36. UART2_INDEX,
  37. #endif
  38. #ifdef BSP_USING_UART3
  39. UART3_INDEX,
  40. #endif
  41. #ifdef BSP_USING_UART4
  42. UART4_INDEX,
  43. #endif
  44. #ifdef BSP_USING_UART5
  45. UART5_INDEX,
  46. #endif
  47. #ifdef BSP_USING_UART6
  48. UART6_INDEX,
  49. #endif
  50. #ifdef BSP_USING_UART7
  51. UART7_INDEX,
  52. #endif
  53. #ifdef BSP_USING_UART8
  54. UART8_INDEX,
  55. #endif
  56. #ifdef BSP_USING_LPUART1
  57. LPUART1_INDEX,
  58. #endif
  59. };
  60. static struct stm32_uart_config uart_config[] =
  61. {
  62. #ifdef BSP_USING_UART1
  63. UART1_CONFIG,
  64. #endif
  65. #ifdef BSP_USING_UART2
  66. UART2_CONFIG,
  67. #endif
  68. #ifdef BSP_USING_UART3
  69. UART3_CONFIG,
  70. #endif
  71. #ifdef BSP_USING_UART4
  72. UART4_CONFIG,
  73. #endif
  74. #ifdef BSP_USING_UART5
  75. UART5_CONFIG,
  76. #endif
  77. #ifdef BSP_USING_UART6
  78. UART6_CONFIG,
  79. #endif
  80. #ifdef BSP_USING_UART7
  81. UART7_CONFIG,
  82. #endif
  83. #ifdef BSP_USING_UART8
  84. UART8_CONFIG,
  85. #endif
  86. #ifdef BSP_USING_LPUART1
  87. LPUART1_CONFIG,
  88. #endif
  89. };
  90. static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
  91. static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  92. {
  93. struct stm32_uart *uart;
  94. RT_ASSERT(serial != RT_NULL);
  95. RT_ASSERT(cfg != RT_NULL);
  96. uart = rt_container_of(serial, struct stm32_uart, serial);
  97. uart->handle.Instance = uart->config->Instance;
  98. uart->handle.Init.BaudRate = cfg->baud_rate;
  99. uart->handle.Init.Mode = UART_MODE_TX_RX;
  100. uart->handle.Init.OverSampling = UART_OVERSAMPLING_16;
  101. switch (cfg->data_bits)
  102. {
  103. case DATA_BITS_8:
  104. if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
  105. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  106. else
  107. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  108. break;
  109. case DATA_BITS_9:
  110. uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
  111. break;
  112. default:
  113. uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
  114. break;
  115. }
  116. switch (cfg->stop_bits)
  117. {
  118. case STOP_BITS_1:
  119. uart->handle.Init.StopBits = UART_STOPBITS_1;
  120. break;
  121. case STOP_BITS_2:
  122. uart->handle.Init.StopBits = UART_STOPBITS_2;
  123. break;
  124. default:
  125. uart->handle.Init.StopBits = UART_STOPBITS_1;
  126. break;
  127. }
  128. switch (cfg->parity)
  129. {
  130. case PARITY_NONE:
  131. uart->handle.Init.Parity = UART_PARITY_NONE;
  132. break;
  133. case PARITY_ODD:
  134. uart->handle.Init.Parity = UART_PARITY_ODD;
  135. break;
  136. case PARITY_EVEN:
  137. uart->handle.Init.Parity = UART_PARITY_EVEN;
  138. break;
  139. default:
  140. uart->handle.Init.Parity = UART_PARITY_NONE;
  141. break;
  142. }
  143. switch (cfg->flowcontrol)
  144. {
  145. case RT_SERIAL_FLOWCONTROL_NONE:
  146. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  147. break;
  148. case RT_SERIAL_FLOWCONTROL_CTSRTS:
  149. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
  150. break;
  151. default:
  152. uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  153. break;
  154. }
  155. #ifdef RT_SERIAL_USING_DMA
  156. uart->dma_rx.remaining_cnt = serial->config.rx_bufsz;
  157. #endif
  158. if (HAL_UART_Init(&uart->handle) != HAL_OK)
  159. {
  160. return -RT_ERROR;
  161. }
  162. return RT_EOK;
  163. }
  164. static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
  165. {
  166. struct stm32_uart *uart;
  167. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  168. RT_ASSERT(serial != RT_NULL);
  169. uart = rt_container_of(serial, struct stm32_uart, serial);
  170. if(ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
  171. {
  172. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
  173. ctrl_arg = RT_DEVICE_FLAG_DMA_RX;
  174. else
  175. ctrl_arg = RT_DEVICE_FLAG_INT_RX;
  176. }
  177. else if(ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
  178. {
  179. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  180. ctrl_arg = RT_DEVICE_FLAG_DMA_TX;
  181. else
  182. ctrl_arg = RT_DEVICE_FLAG_INT_TX;
  183. }
  184. switch (cmd)
  185. {
  186. /* disable interrupt */
  187. case RT_DEVICE_CTRL_CLR_INT:
  188. NVIC_DisableIRQ(uart->config->irq_type);
  189. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
  190. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  191. else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
  192. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE);
  193. #ifdef RT_SERIAL_USING_DMA
  194. else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  195. {
  196. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
  197. HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
  198. if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
  199. {
  200. RT_ASSERT(0);
  201. }
  202. if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
  203. {
  204. RT_ASSERT(0);
  205. }
  206. }
  207. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  208. {
  209. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC);
  210. HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
  211. if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
  212. {
  213. RT_ASSERT(0);
  214. }
  215. }
  216. #endif
  217. break;
  218. case RT_DEVICE_CTRL_SET_INT:
  219. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  220. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  221. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX)
  222. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
  223. else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX)
  224. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TXE);
  225. break;
  226. case RT_DEVICE_CTRL_CONFIG:
  227. if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX))
  228. {
  229. #ifdef RT_SERIAL_USING_DMA
  230. stm32_dma_config(serial, ctrl_arg);
  231. #endif
  232. }
  233. else
  234. stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg);
  235. break;
  236. case RT_DEVICE_CHECK_OPTMODE:
  237. {
  238. if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
  239. return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
  240. else
  241. return RT_SERIAL_TX_BLOCKING_BUFFER;
  242. }
  243. case RT_DEVICE_CTRL_CLOSE:
  244. if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
  245. {
  246. RT_ASSERT(0)
  247. }
  248. break;
  249. }
  250. return RT_EOK;
  251. }
  252. static int stm32_putc(struct rt_serial_device *serial, char c)
  253. {
  254. struct stm32_uart *uart;
  255. RT_ASSERT(serial != RT_NULL);
  256. uart = rt_container_of(serial, struct stm32_uart, serial);
  257. while (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) == RESET);
  258. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  259. UART_SET_TDR(&uart->handle, c);
  260. return 1;
  261. }
  262. rt_uint32_t stm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
  263. {
  264. rt_uint32_t mask;
  265. if (word_length == UART_WORDLENGTH_8B)
  266. {
  267. if (parity == UART_PARITY_NONE)
  268. {
  269. mask = 0x00FFU ;
  270. }
  271. else
  272. {
  273. mask = 0x007FU ;
  274. }
  275. }
  276. #ifdef UART_WORDLENGTH_9B
  277. else if (word_length == UART_WORDLENGTH_9B)
  278. {
  279. if (parity == UART_PARITY_NONE)
  280. {
  281. mask = 0x01FFU ;
  282. }
  283. else
  284. {
  285. mask = 0x00FFU ;
  286. }
  287. }
  288. #endif
  289. #ifdef UART_WORDLENGTH_7B
  290. else if (word_length == UART_WORDLENGTH_7B)
  291. {
  292. if (parity == UART_PARITY_NONE)
  293. {
  294. mask = 0x007FU ;
  295. }
  296. else
  297. {
  298. mask = 0x003FU ;
  299. }
  300. }
  301. else
  302. {
  303. mask = 0x0000U;
  304. }
  305. #endif
  306. return mask;
  307. }
  308. static int stm32_getc(struct rt_serial_device *serial)
  309. {
  310. int ch;
  311. struct stm32_uart *uart;
  312. RT_ASSERT(serial != RT_NULL);
  313. uart = rt_container_of(serial, struct stm32_uart, serial);
  314. ch = -1;
  315. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  316. ch = UART_GET_RDR(&uart->handle, stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity));
  317. return ch;
  318. }
  319. static rt_size_t stm32_transmit(struct rt_serial_device *serial,
  320. rt_uint8_t *buf,
  321. rt_size_t size,
  322. rt_uint32_t tx_flag)
  323. {
  324. struct stm32_uart *uart;
  325. RT_ASSERT(serial != RT_NULL);
  326. RT_ASSERT(buf != RT_NULL);
  327. uart = rt_container_of(serial, struct stm32_uart, serial);
  328. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  329. {
  330. HAL_UART_Transmit_DMA(&uart->handle, buf, size);
  331. return size;
  332. }
  333. stm32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)tx_flag);
  334. return size;
  335. }
  336. #ifdef RT_SERIAL_USING_DMA
  337. static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag)
  338. {
  339. struct stm32_uart *uart;
  340. rt_base_t level;
  341. rt_size_t recv_len, counter;
  342. RT_ASSERT(serial != RT_NULL);
  343. uart = rt_container_of(serial, struct stm32_uart, serial);
  344. level = rt_hw_interrupt_disable();
  345. recv_len = 0;
  346. counter = __HAL_DMA_GET_COUNTER(&(uart->dma_rx.handle));
  347. switch (isr_flag)
  348. {
  349. case UART_RX_DMA_IT_IDLE_FLAG:
  350. if (counter <= uart->dma_rx.remaining_cnt)
  351. recv_len = uart->dma_rx.remaining_cnt - counter;
  352. else
  353. recv_len = serial->config.rx_bufsz + uart->dma_rx.remaining_cnt - counter;
  354. break;
  355. case UART_RX_DMA_IT_HT_FLAG:
  356. if (counter < uart->dma_rx.remaining_cnt)
  357. recv_len = uart->dma_rx.remaining_cnt - counter;
  358. break;
  359. case UART_RX_DMA_IT_TC_FLAG:
  360. if(counter >= uart->dma_rx.remaining_cnt)
  361. recv_len = serial->config.rx_bufsz + uart->dma_rx.remaining_cnt - counter;
  362. default:
  363. break;
  364. }
  365. if (recv_len)
  366. {
  367. uart->dma_rx.remaining_cnt = counter;
  368. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  369. }
  370. rt_hw_interrupt_enable(level);
  371. }
  372. #endif /* RT_SERIAL_USING_DMA */
  373. /**
  374. * Uart common interrupt process. This need add to uart ISR.
  375. *
  376. * @param serial serial device
  377. */
  378. static void uart_isr(struct rt_serial_device *serial)
  379. {
  380. struct stm32_uart *uart;
  381. RT_ASSERT(serial != RT_NULL);
  382. uart = rt_container_of(serial, struct stm32_uart, serial);
  383. /* If the Read data register is not empty and the RXNE interrupt is enabled (RDR) */
  384. if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET) &&
  385. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_RXNE) != RESET))
  386. {
  387. struct rt_serial_rx_fifo *rx_fifo;
  388. rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
  389. RT_ASSERT(rx_fifo != RT_NULL);
  390. rt_ringbuffer_putchar(&(rx_fifo->rb), UART_GET_RDR(&uart->handle, stm32_uart_get_mask(uart->handle.Init.WordLength, uart->handle.Init.Parity)));
  391. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  392. }
  393. /* If the Transmit data register is empty and the TXE interrupt enable is enabled (TDR)*/
  394. else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET) &&
  395. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TXE)) != RESET)
  396. {
  397. struct rt_serial_tx_fifo *tx_fifo;
  398. tx_fifo = (struct rt_serial_tx_fifo *) serial->serial_tx;
  399. RT_ASSERT(tx_fifo != RT_NULL);
  400. rt_uint8_t put_char = 0;
  401. if (rt_ringbuffer_getchar(&(tx_fifo->rb), &put_char))
  402. {
  403. UART_SET_TDR(&uart->handle, put_char);
  404. }
  405. else
  406. {
  407. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TXE);
  408. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_TC);
  409. }
  410. }
  411. else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
  412. (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
  413. {
  414. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  415. {
  416. /* The HAL_UART_TxCpltCallback will be triggered */
  417. HAL_UART_IRQHandler(&(uart->handle));
  418. }
  419. else
  420. {
  421. /* Transmission complete interrupt disable ( CR1 Register) */
  422. __HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_TC);
  423. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  424. }
  425. /* Clear Transmission complete interrupt flag ( ISR Register ) */
  426. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  427. }
  428. #ifdef RT_SERIAL_USING_DMA
  429. else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
  430. && (__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
  431. {
  432. dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG);
  433. __HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
  434. }
  435. #endif
  436. else
  437. {
  438. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
  439. {
  440. LOG_E("(%s) serial device Overrun error!", serial->parent.parent.name);
  441. __HAL_UART_CLEAR_OREFLAG(&uart->handle);
  442. }
  443. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
  444. {
  445. __HAL_UART_CLEAR_NEFLAG(&uart->handle);
  446. }
  447. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
  448. {
  449. __HAL_UART_CLEAR_FEFLAG(&uart->handle);
  450. }
  451. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
  452. {
  453. __HAL_UART_CLEAR_PEFLAG(&uart->handle);
  454. }
  455. #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
  456. && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
  457. && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
  458. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
  459. {
  460. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
  461. }
  462. #endif
  463. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
  464. {
  465. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
  466. }
  467. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
  468. {
  469. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
  470. }
  471. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
  472. {
  473. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
  474. }
  475. if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
  476. {
  477. UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
  478. }
  479. }
  480. }
  481. #if defined(BSP_USING_UART1)
  482. void USART1_IRQHandler(void)
  483. {
  484. /* enter interrupt */
  485. rt_interrupt_enter();
  486. uart_isr(&(uart_obj[UART1_INDEX].serial));
  487. /* leave interrupt */
  488. rt_interrupt_leave();
  489. }
  490. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  491. void UART1_DMA_RX_IRQHandler(void)
  492. {
  493. /* enter interrupt */
  494. rt_interrupt_enter();
  495. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
  496. /* leave interrupt */
  497. rt_interrupt_leave();
  498. }
  499. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  500. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  501. void UART1_DMA_TX_IRQHandler(void)
  502. {
  503. /* enter interrupt */
  504. rt_interrupt_enter();
  505. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
  506. /* leave interrupt */
  507. rt_interrupt_leave();
  508. }
  509. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  510. #endif /* BSP_USING_UART1 */
  511. #if defined(BSP_USING_UART2)
  512. void USART2_IRQHandler(void)
  513. {
  514. /* enter interrupt */
  515. rt_interrupt_enter();
  516. uart_isr(&(uart_obj[UART2_INDEX].serial));
  517. /* leave interrupt */
  518. rt_interrupt_leave();
  519. }
  520. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  521. void UART2_DMA_RX_IRQHandler(void)
  522. {
  523. /* enter interrupt */
  524. rt_interrupt_enter();
  525. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
  526. /* leave interrupt */
  527. rt_interrupt_leave();
  528. }
  529. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  530. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  531. void UART2_DMA_TX_IRQHandler(void)
  532. {
  533. /* enter interrupt */
  534. rt_interrupt_enter();
  535. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
  536. /* leave interrupt */
  537. rt_interrupt_leave();
  538. }
  539. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  540. #endif /* BSP_USING_UART2 */
  541. #if defined(BSP_USING_UART3)
  542. void USART3_IRQHandler(void)
  543. {
  544. /* enter interrupt */
  545. rt_interrupt_enter();
  546. uart_isr(&(uart_obj[UART3_INDEX].serial));
  547. /* leave interrupt */
  548. rt_interrupt_leave();
  549. }
  550. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  551. void UART3_DMA_RX_IRQHandler(void)
  552. {
  553. /* enter interrupt */
  554. rt_interrupt_enter();
  555. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
  556. /* leave interrupt */
  557. rt_interrupt_leave();
  558. }
  559. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
  560. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  561. void UART3_DMA_TX_IRQHandler(void)
  562. {
  563. /* enter interrupt */
  564. rt_interrupt_enter();
  565. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
  566. /* leave interrupt */
  567. rt_interrupt_leave();
  568. }
  569. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
  570. #endif /* BSP_USING_UART3*/
  571. #if defined(BSP_USING_UART4)
  572. void UART4_IRQHandler(void)
  573. {
  574. /* enter interrupt */
  575. rt_interrupt_enter();
  576. uart_isr(&(uart_obj[UART4_INDEX].serial));
  577. /* leave interrupt */
  578. rt_interrupt_leave();
  579. }
  580. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  581. void UART4_DMA_RX_IRQHandler(void)
  582. {
  583. /* enter interrupt */
  584. rt_interrupt_enter();
  585. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
  586. /* leave interrupt */
  587. rt_interrupt_leave();
  588. }
  589. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
  590. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  591. void UART4_DMA_TX_IRQHandler(void)
  592. {
  593. /* enter interrupt */
  594. rt_interrupt_enter();
  595. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
  596. /* leave interrupt */
  597. rt_interrupt_leave();
  598. }
  599. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
  600. #endif /* BSP_USING_UART4*/
  601. #if defined(BSP_USING_UART5)
  602. void UART5_IRQHandler(void)
  603. {
  604. /* enter interrupt */
  605. rt_interrupt_enter();
  606. uart_isr(&(uart_obj[UART5_INDEX].serial));
  607. /* leave interrupt */
  608. rt_interrupt_leave();
  609. }
  610. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  611. void UART5_DMA_RX_IRQHandler(void)
  612. {
  613. /* enter interrupt */
  614. rt_interrupt_enter();
  615. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
  616. /* leave interrupt */
  617. rt_interrupt_leave();
  618. }
  619. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  620. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  621. void UART5_DMA_TX_IRQHandler(void)
  622. {
  623. /* enter interrupt */
  624. rt_interrupt_enter();
  625. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
  626. /* leave interrupt */
  627. rt_interrupt_leave();
  628. }
  629. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  630. #endif /* BSP_USING_UART5*/
  631. #if defined(BSP_USING_UART6)
  632. void USART6_IRQHandler(void)
  633. {
  634. /* enter interrupt */
  635. rt_interrupt_enter();
  636. uart_isr(&(uart_obj[UART6_INDEX].serial));
  637. /* leave interrupt */
  638. rt_interrupt_leave();
  639. }
  640. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  641. void UART6_DMA_RX_IRQHandler(void)
  642. {
  643. /* enter interrupt */
  644. rt_interrupt_enter();
  645. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
  646. /* leave interrupt */
  647. rt_interrupt_leave();
  648. }
  649. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  650. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  651. void UART6_DMA_TX_IRQHandler(void)
  652. {
  653. /* enter interrupt */
  654. rt_interrupt_enter();
  655. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
  656. /* leave interrupt */
  657. rt_interrupt_leave();
  658. }
  659. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  660. #endif /* BSP_USING_UART6*/
  661. #if defined(BSP_USING_UART7)
  662. void UART7_IRQHandler(void)
  663. {
  664. /* enter interrupt */
  665. rt_interrupt_enter();
  666. uart_isr(&(uart_obj[UART7_INDEX].serial));
  667. /* leave interrupt */
  668. rt_interrupt_leave();
  669. }
  670. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  671. void UART7_DMA_RX_IRQHandler(void)
  672. {
  673. /* enter interrupt */
  674. rt_interrupt_enter();
  675. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
  676. /* leave interrupt */
  677. rt_interrupt_leave();
  678. }
  679. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  680. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  681. void UART7_DMA_TX_IRQHandler(void)
  682. {
  683. /* enter interrupt */
  684. rt_interrupt_enter();
  685. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
  686. /* leave interrupt */
  687. rt_interrupt_leave();
  688. }
  689. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  690. #endif /* BSP_USING_UART7*/
  691. #if defined(BSP_USING_UART8)
  692. void UART8_IRQHandler(void)
  693. {
  694. /* enter interrupt */
  695. rt_interrupt_enter();
  696. uart_isr(&(uart_obj[UART8_INDEX].serial));
  697. /* leave interrupt */
  698. rt_interrupt_leave();
  699. }
  700. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  701. void UART8_DMA_RX_IRQHandler(void)
  702. {
  703. /* enter interrupt */
  704. rt_interrupt_enter();
  705. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
  706. /* leave interrupt */
  707. rt_interrupt_leave();
  708. }
  709. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  710. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  711. void UART8_DMA_TX_IRQHandler(void)
  712. {
  713. /* enter interrupt */
  714. rt_interrupt_enter();
  715. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
  716. /* leave interrupt */
  717. rt_interrupt_leave();
  718. }
  719. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  720. #endif /* BSP_USING_UART8*/
  721. #if defined(BSP_USING_LPUART1)
  722. void LPUART1_IRQHandler(void)
  723. {
  724. /* enter interrupt */
  725. rt_interrupt_enter();
  726. uart_isr(&(uart_obj[LPUART1_INDEX].serial));
  727. /* leave interrupt */
  728. rt_interrupt_leave();
  729. }
  730. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA)
  731. void LPUART1_DMA_RX_IRQHandler(void)
  732. {
  733. /* enter interrupt */
  734. rt_interrupt_enter();
  735. HAL_DMA_IRQHandler(&uart_obj[LPUART1_INDEX].dma_rx.handle);
  736. /* leave interrupt */
  737. rt_interrupt_leave();
  738. }
  739. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
  740. #endif /* BSP_USING_LPUART1*/
  741. static void stm32_uart_get_config(void)
  742. {
  743. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  744. #ifdef BSP_USING_UART1
  745. uart_obj[UART1_INDEX].serial.config = config;
  746. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  747. uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
  748. uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
  749. #ifdef BSP_UART1_RX_USING_DMA
  750. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  751. static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG;
  752. uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
  753. #endif
  754. #ifdef BSP_UART1_TX_USING_DMA
  755. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  756. static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG;
  757. uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
  758. #endif
  759. #endif
  760. #ifdef BSP_USING_UART2
  761. uart_obj[UART2_INDEX].serial.config = config;
  762. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  763. uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE;
  764. uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE;
  765. #ifdef BSP_UART2_RX_USING_DMA
  766. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  767. static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG;
  768. uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
  769. #endif
  770. #ifdef BSP_UART2_TX_USING_DMA
  771. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  772. static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG;
  773. uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
  774. #endif
  775. #endif
  776. #ifdef BSP_USING_UART3
  777. uart_obj[UART3_INDEX].serial.config = config;
  778. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  779. uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
  780. uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
  781. #ifdef BSP_UART3_RX_USING_DMA
  782. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  783. static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
  784. uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
  785. #endif
  786. #ifdef BSP_UART3_TX_USING_DMA
  787. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  788. static struct dma_config uart3_dma_tx = UART3_DMA_TX_CONFIG;
  789. uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
  790. #endif
  791. #endif
  792. #ifdef BSP_USING_UART4
  793. uart_obj[UART4_INDEX].serial.config = config;
  794. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  795. uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
  796. uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
  797. #ifdef BSP_UART4_RX_USING_DMA
  798. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  799. static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
  800. uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
  801. #endif
  802. #ifdef BSP_UART4_TX_USING_DMA
  803. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  804. static struct dma_config uart4_dma_tx = UART4_DMA_TX_CONFIG;
  805. uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
  806. #endif
  807. #endif
  808. }
  809. #ifdef RT_SERIAL_USING_DMA
  810. static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  811. {
  812. struct rt_serial_rx_fifo *rx_fifo;
  813. DMA_HandleTypeDef *DMA_Handle;
  814. struct dma_config *dma_config;
  815. struct stm32_uart *uart;
  816. RT_ASSERT(serial != RT_NULL);
  817. RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
  818. uart = rt_container_of(serial, struct stm32_uart, serial);
  819. if (RT_DEVICE_FLAG_DMA_RX == flag)
  820. {
  821. DMA_Handle = &uart->dma_rx.handle;
  822. dma_config = uart->config->dma_rx;
  823. }
  824. else /* RT_DEVICE_FLAG_DMA_TX == flag */
  825. {
  826. DMA_Handle = &uart->dma_tx.handle;
  827. dma_config = uart->config->dma_tx;
  828. }
  829. LOG_D("%s dma config start", uart->config->name);
  830. {
  831. rt_uint32_t tmpreg = 0x00U;
  832. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
  833. || defined(SOC_SERIES_STM32L0)
  834. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  835. SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
  836. tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
  837. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
  838. || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
  839. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  840. SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  841. tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
  842. #elif defined(SOC_SERIES_STM32MP1)
  843. /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
  844. SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  845. tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
  846. #endif
  847. #if defined(DMAMUX1) && (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB))
  848. /* enable DMAMUX clock for L4+ and G4 */
  849. __HAL_RCC_DMAMUX1_CLK_ENABLE();
  850. #elif defined(SOC_SERIES_STM32MP1)
  851. __HAL_RCC_DMAMUX_CLK_ENABLE();
  852. #endif
  853. UNUSED(tmpreg); /* To avoid compiler warnings */
  854. }
  855. if (RT_DEVICE_FLAG_DMA_RX == flag)
  856. {
  857. __HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
  858. }
  859. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  860. {
  861. __HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
  862. }
  863. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
  864. DMA_Handle->Instance = dma_config->Instance;
  865. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  866. DMA_Handle->Instance = dma_config->Instance;
  867. DMA_Handle->Init.Channel = dma_config->channel;
  868. #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
  869. || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  870. DMA_Handle->Instance = dma_config->Instance;
  871. DMA_Handle->Init.Request = dma_config->request;
  872. #endif
  873. DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
  874. DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
  875. DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
  876. DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
  877. if (RT_DEVICE_FLAG_DMA_RX == flag)
  878. {
  879. DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
  880. DMA_Handle->Init.Mode = DMA_CIRCULAR;
  881. }
  882. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  883. {
  884. DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
  885. DMA_Handle->Init.Mode = DMA_NORMAL;
  886. }
  887. DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
  888. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
  889. DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
  890. #endif
  891. if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
  892. {
  893. RT_ASSERT(0);
  894. }
  895. if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
  896. {
  897. RT_ASSERT(0);
  898. }
  899. /* enable interrupt */
  900. if (flag == RT_DEVICE_FLAG_DMA_RX)
  901. {
  902. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  903. RT_ASSERT(rx_fifo != RT_NULL);
  904. /* Start DMA transfer */
  905. if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.rx_bufsz) != HAL_OK)
  906. {
  907. /* Transfer error in reception process */
  908. RT_ASSERT(0);
  909. }
  910. CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
  911. __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
  912. }
  913. /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
  914. HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
  915. HAL_NVIC_EnableIRQ(dma_config->dma_irq);
  916. HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
  917. HAL_NVIC_EnableIRQ(uart->config->irq_type);
  918. LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
  919. LOG_D("%s dma config done", uart->config->name);
  920. }
  921. /**
  922. * @brief UART error callbacks
  923. * @param huart: UART handle
  924. * @note This example shows a simple way to report transfer error, and you can
  925. * add your own implementation.
  926. * @retval None
  927. */
  928. void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
  929. {
  930. RT_ASSERT(huart != NULL);
  931. struct stm32_uart *uart = (struct stm32_uart *)huart;
  932. LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
  933. UNUSED(uart);
  934. }
  935. /**
  936. * @brief Rx Transfer completed callback
  937. * @param huart: UART handle
  938. * @note This example shows a simple way to report end of DMA Rx transfer, and
  939. * you can add your own implementation.
  940. * @retval None
  941. */
  942. void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
  943. {
  944. struct stm32_uart *uart;
  945. RT_ASSERT(huart != NULL);
  946. uart = (struct stm32_uart *)huart;
  947. dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG);
  948. }
  949. /**
  950. * @brief Rx Half transfer completed callback
  951. * @param huart: UART handle
  952. * @note This example shows a simple way to report end of DMA Rx Half transfer,
  953. * and you can add your own implementation.
  954. * @retval None
  955. */
  956. void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
  957. {
  958. struct stm32_uart *uart;
  959. RT_ASSERT(huart != NULL);
  960. uart = (struct stm32_uart *)huart;
  961. dma_recv_isr(&uart->serial, UART_RX_DMA_IT_HT_FLAG);
  962. }
  963. /**
  964. * @brief HAL_UART_TxCpltCallback
  965. * @param huart: UART handle
  966. * @note This callback can be called by two functions, first in UART_EndTransmit_IT when
  967. * UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
  968. * @retval None
  969. */
  970. void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
  971. {
  972. struct stm32_uart *uart;
  973. struct rt_serial_device *serial;
  974. rt_size_t trans_total_index;
  975. rt_base_t level;
  976. RT_ASSERT(huart != NULL);
  977. uart = (struct stm32_uart *)huart;
  978. serial = &uart->serial;
  979. RT_ASSERT(serial != RT_NULL);
  980. level = rt_hw_interrupt_disable();
  981. trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
  982. rt_hw_interrupt_enable(level);
  983. if (trans_total_index) return;
  984. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  985. }
  986. #endif /* RT_SERIAL_USING_DMA */
  987. static const struct rt_uart_ops stm32_uart_ops =
  988. {
  989. .configure = stm32_configure,
  990. .control = stm32_control,
  991. .putc = stm32_putc,
  992. .getc = stm32_getc,
  993. .transmit = stm32_transmit
  994. };
  995. int rt_hw_usart_init(void)
  996. {
  997. rt_err_t result = 0;
  998. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
  999. stm32_uart_get_config();
  1000. for (int i = 0; i < obj_num; i++)
  1001. {
  1002. /* init UART object */
  1003. uart_obj[i].config = &uart_config[i];
  1004. uart_obj[i].serial.ops = &stm32_uart_ops;
  1005. /* register UART device */
  1006. result = rt_hw_serial_register(&uart_obj[i].serial,
  1007. uart_obj[i].config->name,
  1008. RT_DEVICE_FLAG_RDWR,
  1009. NULL);
  1010. RT_ASSERT(result == RT_EOK);
  1011. }
  1012. return result;
  1013. }
  1014. #endif /* RT_USING_SERIAL_V2 */