mfxstm32l152.c 57 KB

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  1. /**
  2. ******************************************************************************
  3. * @file mfxstm32l152.c
  4. * @author MCD Application Team
  5. * @brief This file provides a set of functions needed to manage the MFXSTM32L152
  6. * IO Expander devices.
  7. ******************************************************************************
  8. * @attention
  9. *
  10. * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  11. *
  12. * Redistribution and use in source and binary forms, with or without modification,
  13. * are permitted provided that the following conditions are met:
  14. * 1. Redistributions of source code must retain the above copyright notice,
  15. * this list of conditions and the following disclaimer.
  16. * 2. Redistributions in binary form must reproduce the above copyright notice,
  17. * this list of conditions and the following disclaimer in the documentation
  18. * and/or other materials provided with the distribution.
  19. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  20. * may be used to endorse or promote products derived from this software
  21. * without specific prior written permission.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  27. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  28. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  29. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  30. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  31. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. *
  34. ******************************************************************************
  35. */
  36. /* Includes ------------------------------------------------------------------*/
  37. #include "mfxstm32l152.h"
  38. /** @addtogroup BSP
  39. * @{
  40. */
  41. /** @addtogroup Component
  42. * @{
  43. */
  44. /** @defgroup MFXSTM32L152
  45. * @{
  46. */
  47. /* Private typedef -----------------------------------------------------------*/
  48. /** @defgroup MFXSTM32L152_Private_Types_Definitions
  49. * @{
  50. */
  51. /* Private define ------------------------------------------------------------*/
  52. /** @defgroup MFXSTM32L152_Private_Defines
  53. * @{
  54. */
  55. #define MFXSTM32L152_MAX_INSTANCE 3
  56. /* Private macro -------------------------------------------------------------*/
  57. /** @defgroup MFXSTM32L152_Private_Macros
  58. * @{
  59. */
  60. /* Private variables ---------------------------------------------------------*/
  61. /** @defgroup MFXSTM32L152_Private_Variables
  62. * @{
  63. */
  64. /* Touch screen driver structure initialization */
  65. TS_DrvTypeDef mfxstm32l152_ts_drv =
  66. {
  67. mfxstm32l152_Init,
  68. mfxstm32l152_ReadID,
  69. mfxstm32l152_Reset,
  70. mfxstm32l152_TS_Start,
  71. mfxstm32l152_TS_DetectTouch,
  72. mfxstm32l152_TS_GetXY,
  73. mfxstm32l152_TS_EnableIT,
  74. mfxstm32l152_TS_ClearIT,
  75. mfxstm32l152_TS_ITStatus,
  76. mfxstm32l152_TS_DisableIT,
  77. };
  78. /* IO driver structure initialization */
  79. IO_DrvTypeDef mfxstm32l152_io_drv =
  80. {
  81. mfxstm32l152_Init,
  82. mfxstm32l152_ReadID,
  83. mfxstm32l152_Reset,
  84. mfxstm32l152_IO_Start,
  85. mfxstm32l152_IO_Config,
  86. mfxstm32l152_IO_WritePin,
  87. mfxstm32l152_IO_ReadPin,
  88. mfxstm32l152_IO_EnableIT,
  89. mfxstm32l152_IO_DisableIT,
  90. mfxstm32l152_IO_ITStatus,
  91. mfxstm32l152_IO_ClearIT,
  92. };
  93. /* IDD driver structure initialization */
  94. IDD_DrvTypeDef mfxstm32l152_idd_drv =
  95. {
  96. mfxstm32l152_Init,
  97. mfxstm32l152_DeInit,
  98. mfxstm32l152_ReadID,
  99. mfxstm32l152_Reset,
  100. mfxstm32l152_LowPower,
  101. mfxstm32l152_WakeUp,
  102. mfxstm32l152_IDD_Start,
  103. mfxstm32l152_IDD_Config,
  104. mfxstm32l152_IDD_GetValue,
  105. mfxstm32l152_IDD_EnableIT,
  106. mfxstm32l152_IDD_ClearIT,
  107. mfxstm32l152_IDD_GetITStatus,
  108. mfxstm32l152_IDD_DisableIT,
  109. mfxstm32l152_Error_EnableIT,
  110. mfxstm32l152_Error_ClearIT,
  111. mfxstm32l152_Error_GetITStatus,
  112. mfxstm32l152_Error_DisableIT,
  113. mfxstm32l152_Error_ReadSrc,
  114. mfxstm32l152_Error_ReadMsg
  115. };
  116. /* mfxstm32l152 instances by address */
  117. uint8_t mfxstm32l152[MFXSTM32L152_MAX_INSTANCE] = {0};
  118. /**
  119. * @}
  120. */
  121. /* Private function prototypes -----------------------------------------------*/
  122. /** @defgroup MFXSTM32L152_Private_Function_Prototypes
  123. * @{
  124. */
  125. static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr);
  126. static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr);
  127. static void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue );
  128. /* Private functions ---------------------------------------------------------*/
  129. /** @defgroup MFXSTM32L152_Private_Functions
  130. * @{
  131. */
  132. /**
  133. * @brief Initialize the mfxstm32l152 and configure the needed hardware resources
  134. * @param DeviceAddr: Device address on communication Bus.
  135. * @retval None
  136. */
  137. void mfxstm32l152_Init(uint16_t DeviceAddr)
  138. {
  139. uint8_t instance;
  140. uint8_t empty;
  141. /* Check if device instance already exists */
  142. instance = mfxstm32l152_GetInstance(DeviceAddr);
  143. /* To prevent double initialization */
  144. if(instance == 0xFF)
  145. {
  146. /* Look for empty instance */
  147. empty = mfxstm32l152_GetInstance(0);
  148. if(empty < MFXSTM32L152_MAX_INSTANCE)
  149. {
  150. /* Register the current device instance */
  151. mfxstm32l152[empty] = DeviceAddr;
  152. /* Initialize IO BUS layer */
  153. MFX_IO_Init();
  154. }
  155. }
  156. mfxstm32l152_SetIrqOutPinPolarity(DeviceAddr, MFXSTM32L152_OUT_PIN_POLARITY_HIGH);
  157. mfxstm32l152_SetIrqOutPinType(DeviceAddr, MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL);
  158. }
  159. /**
  160. * @brief DeInitialize the mfxstm32l152 and unconfigure the needed hardware resources
  161. * @param DeviceAddr: Device address on communication Bus.
  162. * @retval None
  163. */
  164. void mfxstm32l152_DeInit(uint16_t DeviceAddr)
  165. {
  166. uint8_t instance;
  167. /* release existing instance */
  168. instance = mfxstm32l152_ReleaseInstance(DeviceAddr);
  169. /* De-Init only if instance was previously registered */
  170. if(instance != 0xFF)
  171. {
  172. /* De-Initialize IO BUS layer */
  173. MFX_IO_DeInit();
  174. }
  175. }
  176. /**
  177. * @brief Reset the mfxstm32l152 by Software.
  178. * @param DeviceAddr: Device address on communication Bus.
  179. * @retval None
  180. */
  181. void mfxstm32l152_Reset(uint16_t DeviceAddr)
  182. {
  183. /* Soft Reset */
  184. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST);
  185. /* Wait for a delay to ensure registers erasing */
  186. rt_thread_delay(10);
  187. }
  188. /**
  189. * @brief Put mfxstm32l152 Device in Low Power standby mode
  190. * @param DeviceAddr: Device address on communication Bus.
  191. * @retval None
  192. */
  193. void mfxstm32l152_LowPower(uint16_t DeviceAddr)
  194. {
  195. /* Enter standby mode */
  196. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY);
  197. /* enable wakeup pin */
  198. MFX_IO_EnableWakeupPin();
  199. }
  200. /**
  201. * @brief WakeUp mfxstm32l152 from standby mode
  202. * @param DeviceAddr: Device address on communication Bus.
  203. * @retval None
  204. */
  205. void mfxstm32l152_WakeUp(uint16_t DeviceAddr)
  206. {
  207. uint8_t instance;
  208. /* Check if device instance already exists */
  209. instance = mfxstm32l152_GetInstance(DeviceAddr);
  210. /* if instance does not exist, first initialize pins*/
  211. if(instance == 0xFF)
  212. {
  213. /* enable wakeup pin */
  214. MFX_IO_EnableWakeupPin();
  215. }
  216. /* toggle wakeup pin */
  217. MFX_IO_Wakeup();
  218. }
  219. /**
  220. * @brief Read the MFXSTM32L152 IO Expander device ID.
  221. * @param DeviceAddr: Device address on communication Bus.
  222. * @retval The Device ID (two bytes).
  223. */
  224. uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr)
  225. {
  226. uint8_t id;
  227. /* Wait for a delay to ensure the state of registers */
  228. rt_thread_mdelay(1);
  229. /* Initialize IO BUS layer */
  230. MFX_IO_Init();
  231. id = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_ID);
  232. /* Return the device ID value */
  233. return (id);
  234. }
  235. /**
  236. * @brief Read the MFXSTM32L152 device firmware version.
  237. * @param DeviceAddr: Device address on communication Bus.
  238. * @retval The Device FW version (two bytes).
  239. */
  240. uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr)
  241. {
  242. uint8_t data[2];
  243. MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_FW_VERSION_MSB, data, sizeof(data)) ;
  244. /* Recompose MFX firmware value */
  245. return ((data[0] << 8) | data[1]);
  246. }
  247. /**
  248. * @brief Enable the interrupt mode for the selected IT source
  249. * @param DeviceAddr: Device address on communication Bus.
  250. * @param Source: The interrupt source to be configured, could be:
  251. * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
  252. * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
  253. * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
  254. * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
  255. * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
  256. * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
  257. * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
  258. * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
  259. * @retval None
  260. */
  261. void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source)
  262. {
  263. uint8_t tmp = 0;
  264. /* Get the current value of the INT_EN register */
  265. tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
  266. /* Set the interrupts to be Enabled */
  267. tmp |= Source;
  268. /* Set the register */
  269. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
  270. }
  271. /**
  272. * @brief Disable the interrupt mode for the selected IT source
  273. * @param DeviceAddr: Device address on communication Bus.
  274. * @param Source: The interrupt source to be configured, could be:
  275. * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
  276. * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
  277. * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
  278. * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
  279. * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
  280. * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
  281. * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
  282. * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
  283. * @retval None
  284. */
  285. void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source)
  286. {
  287. uint8_t tmp = 0;
  288. /* Get the current value of the INT_EN register */
  289. tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
  290. /* Set the interrupts to be Enabled */
  291. tmp &= ~Source;
  292. /* Set the register */
  293. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
  294. }
  295. /**
  296. * @brief Returns the selected Global interrupt source pending bit value
  297. * @param DeviceAddr: Device address on communication Bus.
  298. * @param Source: the Global interrupt source to be checked, could be:
  299. * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
  300. * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
  301. * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
  302. * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
  303. * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
  304. * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
  305. * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
  306. * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
  307. * @retval The value of the checked Global interrupt source status.
  308. */
  309. uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source)
  310. {
  311. /* Return the global IT source status (pending or not)*/
  312. return((MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_PENDING) & Source));
  313. }
  314. /**
  315. * @brief Clear the selected Global interrupt pending bit(s)
  316. * @param DeviceAddr: Device address on communication Bus.
  317. * @param Source: the Global interrupt source to be cleared, could be any combination
  318. * of the below values. The acknowledge signal for MFXSTM32L152_GPIOs configured in input
  319. * with interrupt is not on this register but in IRQ_GPI_ACK1, IRQ_GPI_ACK2 registers.
  320. * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
  321. * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
  322. * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
  323. * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
  324. * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
  325. * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
  326. * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
  327. * /\/\ IMPORTANT NOTE /\/\ must not use MFXSTM32L152_IRQ_GPIO as argument, see IRQ_GPI_ACK1 and IRQ_GPI_ACK2 registers
  328. * @retval None
  329. */
  330. void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source)
  331. {
  332. /* Write 1 to the bits that have to be cleared */
  333. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source);
  334. }
  335. /**
  336. * @brief Set the global interrupt Polarity of IRQ_OUT_PIN.
  337. * @param DeviceAddr: Device address on communication Bus.
  338. * @param Polarity: the IT mode polarity, could be one of the following values:
  339. * @arg MFXSTM32L152_OUT_PIN_POLARITY_LOW: Interrupt output line is active Low edge
  340. * @arg MFXSTM32L152_OUT_PIN_POLARITY_HIGH: Interrupt line output is active High edge
  341. * @retval None
  342. */
  343. void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity)
  344. {
  345. uint8_t tmp = 0;
  346. /* Get the current register value */
  347. tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
  348. /* Mask the polarity bits */
  349. tmp &= ~(uint8_t)0x02;
  350. /* Modify the Interrupt Output line configuration */
  351. tmp |= Polarity;
  352. /* Set the new register value */
  353. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
  354. /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
  355. rt_thread_delay(1);
  356. }
  357. /**
  358. * @brief Set the global interrupt Type of IRQ_OUT_PIN.
  359. * @param DeviceAddr: Device address on communication Bus.
  360. * @param Type: Interrupt line activity type, could be one of the following values:
  361. * @arg MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN: Open Drain output Interrupt line
  362. * @arg MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL: Push Pull output Interrupt line
  363. * @retval None
  364. */
  365. void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type)
  366. {
  367. uint8_t tmp = 0;
  368. /* Get the current register value */
  369. tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
  370. /* Mask the type bits */
  371. tmp &= ~(uint8_t)0x01;
  372. /* Modify the Interrupt Output line configuration */
  373. tmp |= Type;
  374. /* Set the new register value */
  375. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
  376. /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
  377. rt_thread_delay(1);
  378. }
  379. /* ------------------------------------------------------------------ */
  380. /* ----------------------- GPIO ------------------------------------- */
  381. /* ------------------------------------------------------------------ */
  382. /**
  383. * @brief Start the IO functionality used and enable the AF for selected IO pin(s).
  384. * @param DeviceAddr: Device address on communication Bus.
  385. * @param AF_en: 0 to disable, else enabled.
  386. * @retval None
  387. */
  388. void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin)
  389. {
  390. uint8_t mode;
  391. /* Get the current register value */
  392. mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
  393. /* Set the IO Functionalities to be Enabled */
  394. mode |= MFXSTM32L152_GPIO_EN;
  395. /* Enable ALTERNATE functions */
  396. /* AGPIO[0..3] can be either IDD or GPIO */
  397. /* AGPIO[4..7] can be either TS or GPIO */
  398. /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
  399. /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
  400. /* so if IDD and TS are both active it is better to let ALTERNATE off (0) */
  401. /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
  402. /* remind that AGPIO are less efficient then normal GPIO (They use pooling rather then EXTI */
  403. if (IO_Pin > 0xFFFF)
  404. {
  405. mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
  406. }
  407. else
  408. {
  409. mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
  410. }
  411. /* Write the new register value */
  412. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
  413. /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
  414. rt_thread_delay(1);
  415. }
  416. /**
  417. * @brief Configures the IO pin(s) according to IO mode structure value.
  418. * @param DeviceAddr: Device address on communication Bus.
  419. * @param IO_Pin: The output pin to be set or reset. This parameter can be one
  420. * of the following values:
  421. * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
  422. * @param IO_Mode: The IO pin mode to configure, could be one of the following values:
  423. * @arg IO_MODE_INPUT
  424. * @arg IO_MODE_OUTPUT
  425. * @arg IO_MODE_IT_RISING_EDGE
  426. * @arg IO_MODE_IT_FALLING_EDGE
  427. * @arg IO_MODE_IT_LOW_LEVEL
  428. * @arg IO_MODE_IT_HIGH_LEVEL
  429. * @arg IO_MODE_INPUT_PU,
  430. * @arg IO_MODE_INPUT_PD,
  431. * @arg IO_MODE_OUTPUT_OD_PU,
  432. * @arg IO_MODE_OUTPUT_OD_PD,
  433. * @arg IO_MODE_OUTPUT_PP_PU,
  434. * @arg IO_MODE_OUTPUT_PP_PD,
  435. * @arg IO_MODE_IT_RISING_EDGE_PU
  436. * @arg IO_MODE_IT_FALLING_EDGE_PU
  437. * @arg IO_MODE_IT_LOW_LEVEL_PU
  438. * @arg IO_MODE_IT_HIGH_LEVEL_PU
  439. * @arg IO_MODE_IT_RISING_EDGE_PD
  440. * @arg IO_MODE_IT_FALLING_EDGE_PD
  441. * @arg IO_MODE_IT_LOW_LEVEL_PD
  442. * @arg IO_MODE_IT_HIGH_LEVEL_PD
  443. * @retval None
  444. */
  445. uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode)
  446. {
  447. uint8_t error_code = 0;
  448. /* Configure IO pin according to selected IO mode */
  449. switch(IO_Mode)
  450. {
  451. case IO_MODE_OFF: /* Off or analog mode */
  452. case IO_MODE_ANALOG: /* Off or analog mode */
  453. mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
  454. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  455. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
  456. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
  457. break;
  458. case IO_MODE_INPUT: /* Input mode */
  459. mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
  460. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  461. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
  462. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  463. break;
  464. case IO_MODE_INPUT_PU: /* Input mode */
  465. mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
  466. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  467. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  468. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  469. break;
  470. case IO_MODE_INPUT_PD: /* Input mode */
  471. mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
  472. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  473. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  474. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
  475. break;
  476. case IO_MODE_OUTPUT: /* Output mode */
  477. case IO_MODE_OUTPUT_PP_PD: /* Output mode */
  478. mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
  479. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
  480. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
  481. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
  482. break;
  483. case IO_MODE_OUTPUT_PP_PU: /* Output mode */
  484. mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
  485. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
  486. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
  487. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  488. break;
  489. case IO_MODE_OUTPUT_OD_PD: /* Output mode */
  490. mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
  491. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
  492. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
  493. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
  494. break;
  495. case IO_MODE_OUTPUT_OD_PU: /* Output mode */
  496. mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
  497. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
  498. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
  499. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  500. break;
  501. case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */
  502. mfxstm32l152_IO_EnableIT(DeviceAddr);
  503. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  504. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
  505. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  506. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
  507. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
  508. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  509. break;
  510. case IO_MODE_IT_RISING_EDGE_PU: /* Interrupt rising edge mode */
  511. mfxstm32l152_IO_EnableIT(DeviceAddr);
  512. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  513. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  514. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  515. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
  516. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
  517. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  518. break;
  519. case IO_MODE_IT_RISING_EDGE_PD: /* Interrupt rising edge mode */
  520. mfxstm32l152_IO_EnableIT(DeviceAddr);
  521. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  522. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  523. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
  524. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
  525. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
  526. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  527. break;
  528. case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */
  529. mfxstm32l152_IO_EnableIT(DeviceAddr);
  530. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  531. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
  532. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  533. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
  534. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
  535. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  536. break;
  537. case IO_MODE_IT_FALLING_EDGE_PU: /* Interrupt falling edge mode */
  538. mfxstm32l152_IO_EnableIT(DeviceAddr);
  539. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  540. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  541. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  542. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
  543. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
  544. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  545. break;
  546. case IO_MODE_IT_FALLING_EDGE_PD: /* Interrupt falling edge mode */
  547. mfxstm32l152_IO_EnableIT(DeviceAddr);
  548. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  549. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  550. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
  551. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
  552. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
  553. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  554. break;
  555. case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */
  556. mfxstm32l152_IO_EnableIT(DeviceAddr);
  557. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  558. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
  559. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  560. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
  561. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
  562. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  563. break;
  564. case IO_MODE_IT_LOW_LEVEL_PU: /* Low level interrupt mode */
  565. mfxstm32l152_IO_EnableIT(DeviceAddr);
  566. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  567. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  568. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  569. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
  570. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
  571. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  572. break;
  573. case IO_MODE_IT_LOW_LEVEL_PD: /* Low level interrupt mode */
  574. mfxstm32l152_IO_EnableIT(DeviceAddr);
  575. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  576. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  577. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
  578. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
  579. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
  580. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  581. break;
  582. case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */
  583. mfxstm32l152_IO_EnableIT(DeviceAddr);
  584. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  585. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
  586. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  587. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
  588. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
  589. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  590. break;
  591. case IO_MODE_IT_HIGH_LEVEL_PU: /* High level interrupt mode */
  592. mfxstm32l152_IO_EnableIT(DeviceAddr);
  593. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  594. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  595. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
  596. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
  597. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
  598. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  599. break;
  600. case IO_MODE_IT_HIGH_LEVEL_PD: /* High level interrupt mode */
  601. mfxstm32l152_IO_EnableIT(DeviceAddr);
  602. mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
  603. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
  604. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
  605. mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
  606. mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
  607. mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
  608. break;
  609. default:
  610. error_code = (uint8_t) IO_Mode;
  611. break;
  612. }
  613. return error_code;
  614. }
  615. /**
  616. * @brief Initialize the selected IO pin direction.
  617. * @param DeviceAddr: Device address on communication Bus.
  618. * @param IO_Pin: The IO pin to be configured. This parameter could be any
  619. * combination of the following values:
  620. * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
  621. * @param Direction: could be MFXSTM32L152_GPIO_DIR_IN or MFXSTM32L152_GPIO_DIR_OUT.
  622. * @retval None
  623. */
  624. void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction)
  625. {
  626. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_DIR1, IO_Pin, Direction);
  627. }
  628. /**
  629. * @brief Set the global interrupt Type.
  630. * @param DeviceAddr: Device address on communication Bus.
  631. * @param IO_Pin: The IO pin to be configured. This parameter could be any
  632. * combination of the following values:
  633. * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
  634. * @param Evt: Interrupt line activity type, could be one of the following values:
  635. * @arg MFXSTM32L152_IRQ_GPI_EVT_LEVEL: Interrupt line is active in level model
  636. * @arg MFXSTM32L152_IRQ_GPI_EVT_EDGE: Interrupt line is active in edge model
  637. * @retval None
  638. */
  639. void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt)
  640. {
  641. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1, IO_Pin, Evt);
  642. rt_thread_delay(1);
  643. }
  644. /**
  645. * @brief Configure the Edge for which a transition is detectable for the
  646. * selected pin.
  647. * @param DeviceAddr: Device address on communication Bus.
  648. * @param IO_Pin: The IO pin to be configured. This parameter could be any
  649. * combination of the following values:
  650. * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
  651. * @param Evt: Interrupt line activity type, could be one of the following values:
  652. * @arg MFXSTM32L152_IRQ_GPI_TYPE_LLFE: Interrupt line is active in Low Level or Falling Edge
  653. * @arg MFXSTM32L152_IRQ_GPI_TYPE_HLRE: Interrupt line is active in High Level or Rising Edge
  654. * @retval None
  655. */
  656. void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type)
  657. {
  658. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1, IO_Pin, Type);
  659. rt_thread_delay(1);
  660. }
  661. /**
  662. * @brief When GPIO is in output mode, puts the corresponding GPO in High (1) or Low (0) level.
  663. * @param DeviceAddr: Device address on communication Bus.
  664. * @param IO_Pin: The output pin to be set or reset. This parameter can be one
  665. * of the following values:
  666. * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
  667. * @param PinState: The new IO pin state.
  668. * @retval None
  669. */
  670. void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState)
  671. {
  672. /* Apply the bit value to the selected pin */
  673. if (PinState != 0)
  674. {
  675. /* Set the SET register */
  676. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_SET1, IO_Pin, 1);
  677. }
  678. else
  679. {
  680. /* Set the CLEAR register */
  681. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_CLR1, IO_Pin, 1);
  682. }
  683. }
  684. /**
  685. * @brief Return the state of the selected IO pin(s).
  686. * @param DeviceAddr: Device address on communication Bus.
  687. * @param IO_Pin: The output pin to be set or reset. This parameter can be one
  688. * of the following values:
  689. * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
  690. * @retval IO pin(s) state.
  691. */
  692. uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin)
  693. {
  694. uint32_t tmp1 = 0;
  695. uint32_t tmp2 = 0;
  696. uint32_t tmp3 = 0;
  697. if(IO_Pin & 0x000000FF)
  698. {
  699. tmp1 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE1);
  700. }
  701. if(IO_Pin & 0x0000FF00)
  702. {
  703. tmp2 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE2);
  704. }
  705. if(IO_Pin & 0x00FF0000)
  706. {
  707. tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE3);
  708. }
  709. tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
  710. return(tmp3 & IO_Pin);
  711. }
  712. /**
  713. * @brief Enable the global IO interrupt source.
  714. * @param DeviceAddr: Device address on communication Bus.
  715. * @retval None
  716. */
  717. void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr)
  718. {
  719. MFX_IO_ITConfig();
  720. /* Enable global IO IT source */
  721. mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
  722. }
  723. /**
  724. * @brief Disable the global IO interrupt source.
  725. * @param DeviceAddr: Device address on communication Bus.
  726. * @retval None
  727. */
  728. void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr)
  729. {
  730. /* Disable global IO IT source */
  731. mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
  732. }
  733. /**
  734. * @brief Enable interrupt mode for the selected IO pin(s).
  735. * @param DeviceAddr: Device address on communication Bus.
  736. * @param IO_Pin: The IO interrupt to be enabled. This parameter could be any
  737. * combination of the following values:
  738. * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
  739. * @retval None
  740. */
  741. void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
  742. {
  743. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 1);
  744. }
  745. /**
  746. * @brief Disable interrupt mode for the selected IO pin(s).
  747. * @param DeviceAddr: Device address on communication Bus.
  748. * @param IO_Pin: The IO interrupt to be disabled. This parameter could be any
  749. * combination of the following values:
  750. * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
  751. * @retval None
  752. */
  753. void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
  754. {
  755. mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 0);
  756. }
  757. /**
  758. * @brief Check the status of the selected IO interrupt pending bit
  759. * @param DeviceAddr: Device address on communication Bus.
  760. * @param IO_Pin: The IO interrupt to be checked could be:
  761. * @arg MFXSTM32L152_GPIO_PIN_x Where x can be from 0 to 23.
  762. * @retval Status of the checked IO pin(s).
  763. */
  764. uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin)
  765. {
  766. /* Get the Interrupt status */
  767. uint8_t tmp1 = 0;
  768. uint16_t tmp2 = 0;
  769. uint32_t tmp3 = 0;
  770. if(IO_Pin & 0xFF)
  771. {
  772. tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1);
  773. }
  774. if(IO_Pin & 0xFFFF00)
  775. {
  776. tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2);
  777. }
  778. if(IO_Pin & 0xFFFF0000)
  779. {
  780. tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3);
  781. }
  782. tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
  783. return(tmp3 & IO_Pin);
  784. }
  785. /**
  786. * @brief Clear the selected IO interrupt pending bit(s). It clear automatically also the general MFXSTM32L152_REG_ADR_IRQ_PENDING
  787. * @param DeviceAddr: Device address on communication Bus.
  788. * @param IO_Pin: the IO interrupt to be cleared, could be:
  789. * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
  790. * @retval None
  791. */
  792. void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin)
  793. {
  794. /* Clear the IO IT pending bit(s) by acknowledging */
  795. /* it cleans automatically also the Global IRQ_GPIO */
  796. /* normally this function is called under interrupt */
  797. uint8_t pin_0_7, pin_8_15, pin_16_23;
  798. pin_0_7 = IO_Pin & 0x0000ff;
  799. pin_8_15 = IO_Pin >> 8;
  800. pin_8_15 = pin_8_15 & 0x00ff;
  801. pin_16_23 = IO_Pin >> 16;
  802. if (pin_0_7)
  803. {
  804. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7);
  805. }
  806. if (pin_8_15)
  807. {
  808. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15);
  809. }
  810. if (pin_16_23)
  811. {
  812. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23);
  813. }
  814. }
  815. /**
  816. * @brief Enable the AF for aGPIO.
  817. * @param DeviceAddr: Device address on communication Bus.
  818. * @retval None
  819. */
  820. void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr)
  821. {
  822. uint8_t mode;
  823. /* Get the current register value */
  824. mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
  825. /* Enable ALTERNATE functions */
  826. /* AGPIO[0..3] can be either IDD or GPIO */
  827. /* AGPIO[4..7] can be either TS or GPIO */
  828. /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
  829. /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
  830. /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
  831. /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
  832. /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
  833. mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
  834. /* Write the new register value */
  835. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
  836. }
  837. /**
  838. * @brief Disable the AF for aGPIO.
  839. * @param DeviceAddr: Device address on communication Bus.
  840. * @retval None
  841. */
  842. void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr)
  843. {
  844. uint8_t mode;
  845. /* Get the current register value */
  846. mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
  847. /* Enable ALTERNATE functions */
  848. /* AGPIO[0..3] can be either IDD or GPIO */
  849. /* AGPIO[4..7] can be either TS or GPIO */
  850. /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
  851. /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
  852. /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
  853. /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
  854. /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
  855. mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
  856. /* Write the new register value */
  857. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
  858. }
  859. /* ------------------------------------------------------------------ */
  860. /* --------------------- TOUCH SCREEN ------------------------------- */
  861. /* ------------------------------------------------------------------ */
  862. /**
  863. * @brief Configures the touch Screen Controller (Single point detection)
  864. * @param DeviceAddr: Device address on communication Bus.
  865. * @retval None.
  866. */
  867. void mfxstm32l152_TS_Start(uint16_t DeviceAddr)
  868. {
  869. uint8_t mode;
  870. /* Get the current register value */
  871. mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
  872. /* Set the Functionalities to be Enabled */
  873. mode |= MFXSTM32L152_TS_EN;
  874. /* Set the new register value */
  875. MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
  876. /* Wait for 2 ms */
  877. rt_thread_delay(2);
  878. /* Select 2 nF filter capacitor */
  879. /* Configuration:
  880. - Touch average control : 4 samples
  881. - Touch delay time : 500 uS
  882. - Panel driver setting time: 500 uS
  883. */
  884. MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32);
  885. MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5);
  886. MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04);
  887. /* Configure the Touch FIFO threshold: single point reading */
  888. MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01);
  889. /* Clear the FIFO memory content. */
  890. MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
  891. /* Touch screen control configuration :
  892. - No window tracking index
  893. */
  894. MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00);
  895. /* Clear all the IT status pending bits if any */
  896. mfxstm32l152_IO_ClearIT(DeviceAddr, 0xFFFFFF);
  897. /* Wait for 1 ms delay */
  898. rt_thread_delay(1);
  899. }
  900. /**
  901. * @brief Return if there is touch detected or not.
  902. * @param DeviceAddr: Device address on communication Bus.
  903. * @retval Touch detected state.
  904. */
  905. uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr)
  906. {
  907. uint8_t state;
  908. uint8_t ret = 0;
  909. state = MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_STA);
  910. state = ((state & (uint8_t)MFXSTM32L152_TS_CTRL_STATUS) == (uint8_t)MFXSTM32L152_TS_CTRL_STATUS);
  911. if(state > 0)
  912. {
  913. if(MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_LEVEL) > 0)
  914. {
  915. ret = 1;
  916. }
  917. }
  918. return ret;
  919. }
  920. /**
  921. * @brief Get the touch screen X and Y positions values
  922. * @param DeviceAddr: Device address on communication Bus.
  923. * @param X: Pointer to X position value
  924. * @param Y: Pointer to Y position value
  925. * @retval None.
  926. */
  927. void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
  928. {
  929. uint8_t data_xy[3];
  930. MFX_IO_ReadMultiple(DeviceAddr, MFXSTM32L152_TS_XY_DATA, data_xy, sizeof(data_xy)) ;
  931. /* Calculate positions values */
  932. *X = (data_xy[1]<<4) + (data_xy[0]>>4);
  933. *Y = (data_xy[2]<<4) + (data_xy[0]&4);
  934. /* Reset the FIFO memory content. */
  935. MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
  936. }
  937. /**
  938. * @brief Configure the selected source to generate a global interrupt or not
  939. * @param DeviceAddr: Device address on communication Bus.
  940. * @retval None
  941. */
  942. void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr)
  943. {
  944. MFX_IO_ITConfig();
  945. /* Enable global TS IT source */
  946. mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
  947. }
  948. /**
  949. * @brief Configure the selected source to generate a global interrupt or not
  950. * @param DeviceAddr: Device address on communication Bus.
  951. * @retval None
  952. */
  953. void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr)
  954. {
  955. /* Disable global TS IT source */
  956. mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
  957. }
  958. /**
  959. * @brief Configure the selected source to generate a global interrupt or not
  960. * @param DeviceAddr: Device address on communication Bus.
  961. * @retval TS interrupts status
  962. */
  963. uint8_t mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr)
  964. {
  965. /* Return TS interrupts status */
  966. return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_TS));
  967. }
  968. /**
  969. * @brief Configure the selected source to generate a global interrupt or not
  970. * @param DeviceAddr: Device address on communication Bus.
  971. * @retval None
  972. */
  973. void mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr)
  974. {
  975. /* Clear the global TS IT source */
  976. mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_TS);
  977. }
  978. /* ------------------------------------------------------------------ */
  979. /* --------------------- IDD MEASUREMENT ---------------------------- */
  980. /* ------------------------------------------------------------------ */
  981. /**
  982. * @brief Launch IDD current measurement
  983. * @param DeviceAddr: Device address on communication Bus
  984. * @retval None.
  985. */
  986. void mfxstm32l152_IDD_Start(uint16_t DeviceAddr)
  987. {
  988. uint8_t mode = 0;
  989. /* Get the current register value */
  990. mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
  991. /* Set the Functionalities to be enabled */
  992. mode |= MFXSTM32L152_IDD_CTRL_REQ;
  993. /* Start measurement campaign */
  994. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
  995. }
  996. /**
  997. * @brief Configures the IDD current measurement
  998. * @param DeviceAddr: Device address on communication Bus.
  999. * @param MfxIddConfig: Parameters depending on hardware config.
  1000. * @retval None
  1001. */
  1002. void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig)
  1003. {
  1004. uint8_t value = 0;
  1005. uint8_t mode = 0;
  1006. /* Get the current register value */
  1007. mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
  1008. if((mode & MFXSTM32L152_IDD_EN) != MFXSTM32L152_IDD_EN)
  1009. {
  1010. /* Set the Functionalities to be enabled */
  1011. mode |= MFXSTM32L152_IDD_EN;
  1012. /* Set the new register value */
  1013. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
  1014. }
  1015. /* Control register setting: number of shunts */
  1016. value = ((MfxIddConfig.ShuntNbUsed << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
  1017. value |= (MfxIddConfig.VrefMeasurement & MFXSTM32L152_IDD_CTRL_VREF_DIS);
  1018. value |= (MfxIddConfig.Calibration & MFXSTM32L152_IDD_CTRL_CAL_DIS);
  1019. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value);
  1020. /* Idd pre delay configuration: unit and value*/
  1021. value = (MfxIddConfig.PreDelayUnit & MFXSTM32L152_IDD_PREDELAY_UNIT) |
  1022. (MfxIddConfig.PreDelayValue & MFXSTM32L152_IDD_PREDELAY_VALUE);
  1023. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value);
  1024. /* Shunt 0 register value: MSB then LSB */
  1025. value = (uint8_t) (MfxIddConfig.Shunt0Value >> 8);
  1026. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value);
  1027. value = (uint8_t) (MfxIddConfig.Shunt0Value);
  1028. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value);
  1029. /* Shunt 1 register value: MSB then LSB */
  1030. value = (uint8_t) (MfxIddConfig.Shunt1Value >> 8);
  1031. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value);
  1032. value = (uint8_t) (MfxIddConfig.Shunt1Value);
  1033. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value);
  1034. /* Shunt 2 register value: MSB then LSB */
  1035. value = (uint8_t) (MfxIddConfig.Shunt2Value >> 8);
  1036. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value);
  1037. value = (uint8_t) (MfxIddConfig.Shunt2Value);
  1038. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value);
  1039. /* Shunt 3 register value: MSB then LSB */
  1040. value = (uint8_t) (MfxIddConfig.Shunt3Value >> 8);
  1041. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value);
  1042. value = (uint8_t) (MfxIddConfig.Shunt3Value);
  1043. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value);
  1044. /* Shunt 4 register value: MSB then LSB */
  1045. value = (uint8_t) (MfxIddConfig.Shunt4Value >> 8);
  1046. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value);
  1047. value = (uint8_t) (MfxIddConfig.Shunt4Value);
  1048. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value);
  1049. /* Shunt 0 stabilization delay */
  1050. value = MfxIddConfig.Shunt0StabDelay;
  1051. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value);
  1052. /* Shunt 1 stabilization delay */
  1053. value = MfxIddConfig.Shunt1StabDelay;
  1054. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value);
  1055. /* Shunt 2 stabilization delay */
  1056. value = MfxIddConfig.Shunt2StabDelay;
  1057. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value);
  1058. /* Shunt 3 stabilization delay */
  1059. value = MfxIddConfig.Shunt3StabDelay;
  1060. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value);
  1061. /* Shunt 4 stabilization delay */
  1062. value = MfxIddConfig.Shunt4StabDelay;
  1063. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value);
  1064. /* Idd ampli gain value: MSB then LSB */
  1065. value = (uint8_t) (MfxIddConfig.AmpliGain >> 8);
  1066. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value);
  1067. value = (uint8_t) (MfxIddConfig.AmpliGain);
  1068. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value);
  1069. /* Idd VDD min value: MSB then LSB */
  1070. value = (uint8_t) (MfxIddConfig.VddMin >> 8);
  1071. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value);
  1072. value = (uint8_t) (MfxIddConfig.VddMin);
  1073. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value);
  1074. /* Idd number of measurements */
  1075. value = MfxIddConfig.MeasureNb;
  1076. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value);
  1077. /* Idd delta delay configuration: unit and value */
  1078. value = (MfxIddConfig.DeltaDelayUnit & MFXSTM32L152_IDD_DELTADELAY_UNIT) |
  1079. (MfxIddConfig.DeltaDelayValue & MFXSTM32L152_IDD_DELTADELAY_VALUE);
  1080. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value);
  1081. /* Idd number of shut on board */
  1082. value = MfxIddConfig.ShuntNbOnBoard;
  1083. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value);
  1084. }
  1085. /**
  1086. * @brief This function allows to modify number of shunt used for a measurement
  1087. * @param DeviceAddr: Device address on communication Bus
  1088. * @retval None.
  1089. */
  1090. void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit)
  1091. {
  1092. uint8_t mode = 0;
  1093. /* Get the current register value */
  1094. mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
  1095. /* Clear number of shunt limit */
  1096. mode &= ~(MFXSTM32L152_IDD_CTRL_SHUNT_NB);
  1097. /* Clear number of shunt limit */
  1098. mode |= ((ShuntNbLimit << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
  1099. /* Write noewx desired limit */
  1100. MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
  1101. }
  1102. /**
  1103. * @brief Get Idd current value
  1104. * @param DeviceAddr: Device address on communication Bus
  1105. * @param ReadValue: Pointer on value to be read
  1106. * @retval Idd value in 10 nA.
  1107. */
  1108. void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue)
  1109. {
  1110. uint8_t data[3];
  1111. MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VALUE_MSB, data, sizeof(data)) ;
  1112. /* Recompose Idd current value */
  1113. *ReadValue = (data[0] << 16) | (data[1] << 8) | data[2];
  1114. }
  1115. /**
  1116. * @brief Get Last shunt used for measurement
  1117. * @param DeviceAddr: Device address on communication Bus
  1118. * @retval Last shunt used
  1119. */
  1120. uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr)
  1121. {
  1122. return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT_USED));
  1123. }
  1124. /**
  1125. * @brief Configure mfx to enable Idd interrupt
  1126. * @param DeviceAddr: Device address on communication Bus.
  1127. * @retval None
  1128. */
  1129. void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr)
  1130. {
  1131. MFX_IO_ITConfig();
  1132. /* Enable global IDD interrupt source */
  1133. mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
  1134. }
  1135. /**
  1136. * @brief Clear Idd global interrupt
  1137. * @param DeviceAddr: Device address on communication Bus.
  1138. * @retval None
  1139. */
  1140. void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr)
  1141. {
  1142. /* Clear the global IDD interrupt source */
  1143. mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_IDD);
  1144. }
  1145. /**
  1146. * @brief get Idd interrupt status
  1147. * @param DeviceAddr: Device address on communication Bus.
  1148. * @retval IDD interrupts status
  1149. */
  1150. uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr)
  1151. {
  1152. /* Return IDD interrupt status */
  1153. return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_IDD));
  1154. }
  1155. /**
  1156. * @brief disable Idd interrupt
  1157. * @param DeviceAddr: Device address on communication Bus.
  1158. * @retval None.
  1159. */
  1160. void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr)
  1161. {
  1162. /* Disable global IDD interrupt source */
  1163. mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
  1164. }
  1165. /* ------------------------------------------------------------------ */
  1166. /* --------------------- ERROR MANAGEMENT --------------------------- */
  1167. /* ------------------------------------------------------------------ */
  1168. /**
  1169. * @brief Read Error Source.
  1170. * @param DeviceAddr: Device address on communication Bus.
  1171. * @retval Error message code with error source
  1172. */
  1173. uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr)
  1174. {
  1175. /* Get the current source register value */
  1176. return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_SRC));
  1177. }
  1178. /**
  1179. * @brief Read Error Message
  1180. * @param DeviceAddr: Device address on communication Bus.
  1181. * @retval Error message code with error source
  1182. */
  1183. uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr)
  1184. {
  1185. /* Get the current message register value */
  1186. return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_MSG));
  1187. }
  1188. /**
  1189. * @brief Enable Error global interrupt
  1190. * @param DeviceAddr: Device address on communication Bus.
  1191. * @retval None
  1192. */
  1193. void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr)
  1194. {
  1195. MFX_IO_ITConfig();
  1196. /* Enable global Error interrupt source */
  1197. mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
  1198. }
  1199. /**
  1200. * @brief Clear Error global interrupt
  1201. * @param DeviceAddr: Device address on communication Bus.
  1202. * @retval None
  1203. */
  1204. void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr)
  1205. {
  1206. /* Clear the global Error interrupt source */
  1207. mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
  1208. }
  1209. /**
  1210. * @brief get Error interrupt status
  1211. * @param DeviceAddr: Device address on communication Bus.
  1212. * @retval Error interrupts status
  1213. */
  1214. uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr)
  1215. {
  1216. /* Return Error interrupt status */
  1217. return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_ERROR));
  1218. }
  1219. /**
  1220. * @brief disable Error interrupt
  1221. * @param DeviceAddr: Device address on communication Bus.
  1222. * @retval None.
  1223. */
  1224. void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr)
  1225. {
  1226. /* Disable global Error interrupt source */
  1227. mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
  1228. }
  1229. /**
  1230. * @brief FOR DEBUG ONLY
  1231. */
  1232. uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr)
  1233. {
  1234. /* Get the current register value */
  1235. return(MFX_IO_Read((uint8_t) DeviceAddr, RegAddr));
  1236. }
  1237. void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value)
  1238. {
  1239. /* set the current register value */
  1240. MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value);
  1241. }
  1242. /* ------------------------------------------------------------------ */
  1243. /* ----------------------- Private functions ------------------------ */
  1244. /* ------------------------------------------------------------------ */
  1245. /**
  1246. * @brief Check if the device instance of the selected address is already registered
  1247. * and return its index
  1248. * @param DeviceAddr: Device address on communication Bus.
  1249. * @retval Index of the device instance if registered, 0xFF if not.
  1250. */
  1251. static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr)
  1252. {
  1253. uint8_t idx = 0;
  1254. /* Check all the registered instances */
  1255. for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
  1256. {
  1257. if(mfxstm32l152[idx] == DeviceAddr)
  1258. {
  1259. return idx;
  1260. }
  1261. }
  1262. return 0xFF;
  1263. }
  1264. /**
  1265. * @brief Release registered device instance
  1266. * @param DeviceAddr: Device address on communication Bus.
  1267. * @retval Index of released device instance, 0xFF if not.
  1268. */
  1269. static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr)
  1270. {
  1271. uint8_t idx = 0;
  1272. /* Check for all the registered instances */
  1273. for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
  1274. {
  1275. if(mfxstm32l152[idx] == DeviceAddr)
  1276. {
  1277. mfxstm32l152[idx] = 0;
  1278. return idx;
  1279. }
  1280. }
  1281. return 0xFF;
  1282. }
  1283. /**
  1284. * @brief Internal routine
  1285. * @param DeviceAddr: Device address on communication Bus.
  1286. * @param RegisterAddr: Register Address
  1287. * @param PinPosition: Pin [0:23]
  1288. * @param PinValue: 0/1
  1289. * @retval None
  1290. */
  1291. void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue )
  1292. {
  1293. uint8_t tmp = 0;
  1294. uint8_t pin_0_7, pin_8_15, pin_16_23;
  1295. pin_0_7 = PinPosition & 0x0000ff;
  1296. pin_8_15 = PinPosition >> 8;
  1297. pin_8_15 = pin_8_15 & 0x00ff;
  1298. pin_16_23 = PinPosition >> 16;
  1299. if (pin_0_7)
  1300. {
  1301. /* Get the current register value */
  1302. tmp = MFX_IO_Read(DeviceAddr, RegisterAddr);
  1303. /* Set the selected pin direction */
  1304. if (PinValue != 0)
  1305. {
  1306. tmp |= (uint8_t)pin_0_7;
  1307. }
  1308. else
  1309. {
  1310. tmp &= ~(uint8_t)pin_0_7;
  1311. }
  1312. /* Set the new register value */
  1313. MFX_IO_Write(DeviceAddr, RegisterAddr, tmp);
  1314. }
  1315. if (pin_8_15)
  1316. {
  1317. /* Get the current register value */
  1318. tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+1);
  1319. /* Set the selected pin direction */
  1320. if (PinValue != 0)
  1321. {
  1322. tmp |= (uint8_t)pin_8_15;
  1323. }
  1324. else
  1325. {
  1326. tmp &= ~(uint8_t)pin_8_15;
  1327. }
  1328. /* Set the new register value */
  1329. MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp);
  1330. }
  1331. if (pin_16_23)
  1332. {
  1333. /* Get the current register value */
  1334. tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+2);
  1335. /* Set the selected pin direction */
  1336. if (PinValue != 0)
  1337. {
  1338. tmp |= (uint8_t)pin_16_23;
  1339. }
  1340. else
  1341. {
  1342. tmp &= ~(uint8_t)pin_16_23;
  1343. }
  1344. /* Set the new register value */
  1345. MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp);
  1346. }
  1347. }
  1348. /**
  1349. * @}
  1350. */
  1351. /**
  1352. * @}
  1353. */
  1354. /**
  1355. * @}
  1356. */
  1357. /**
  1358. * @}
  1359. */
  1360. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/