sysctl.c 137 KB

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  1. //*****************************************************************************
  2. //
  3. // sysctl.c - Driver for the system controller.
  4. //
  5. // Copyright (c) 2005-2020 Texas Instruments Incorporated. All rights reserved.
  6. // Software License Agreement
  7. //
  8. // Redistribution and use in source and binary forms, with or without
  9. // modification, are permitted provided that the following conditions
  10. // are met:
  11. //
  12. // Redistributions of source code must retain the above copyright
  13. // notice, this list of conditions and the following disclaimer.
  14. //
  15. // Redistributions in binary form must reproduce the above copyright
  16. // notice, this list of conditions and the following disclaimer in the
  17. // documentation and/or other materials provided with the
  18. // distribution.
  19. //
  20. // Neither the name of Texas Instruments Incorporated nor the names of
  21. // its contributors may be used to endorse or promote products derived
  22. // from this software without specific prior written permission.
  23. //
  24. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25. // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26. // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  27. // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  28. // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  29. // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  30. // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31. // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32. // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33. // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34. // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. //
  36. // This is part of revision 2.2.0.295 of the Tiva Peripheral Driver Library.
  37. //
  38. //*****************************************************************************
  39. //*****************************************************************************
  40. //
  41. //! \addtogroup sysctl_api
  42. //! @{
  43. //
  44. //*****************************************************************************
  45. #include <stdbool.h>
  46. #include <stdint.h>
  47. #include "inc/hw_ints.h"
  48. #include "inc/hw_nvic.h"
  49. #include "inc/hw_sysctl.h"
  50. #include "inc/hw_types.h"
  51. #include "inc/hw_flash.h"
  52. #include "driverlib/cpu.h"
  53. #include "driverlib/debug.h"
  54. #include "driverlib/interrupt.h"
  55. #include "driverlib/sysctl.h"
  56. //*****************************************************************************
  57. //
  58. // The flash shift used in the math to calculate the flash sector size.
  59. //
  60. //*****************************************************************************
  61. #ifndef FLASH_PP_MAINSS_S
  62. #define FLASH_PP_MAINSS_S 16
  63. #endif
  64. //*****************************************************************************
  65. //
  66. // This macro converts the XTAL value provided in the ui32Config parameter to
  67. // an index to the g_pui32Xtals array.
  68. //
  69. //*****************************************************************************
  70. #define SysCtlXtalCfgToIndex(a) ((a & 0x7c0) >> 6)
  71. //*****************************************************************************
  72. //
  73. // An array that maps the crystal number in RCC to a frequency.
  74. //
  75. //*****************************************************************************
  76. static const uint32_t g_pui32Xtals[] =
  77. {
  78. 1000000,
  79. 1843200,
  80. 2000000,
  81. 2457600,
  82. 3579545,
  83. 3686400,
  84. 4000000,
  85. 4096000,
  86. 4915200,
  87. 5000000,
  88. 5120000,
  89. 6000000,
  90. 6144000,
  91. 7372800,
  92. 8000000,
  93. 8192000,
  94. 10000000,
  95. 12000000,
  96. 12288000,
  97. 13560000,
  98. 14318180,
  99. 16000000,
  100. 16384000,
  101. 18000000,
  102. 20000000,
  103. 24000000,
  104. 25000000
  105. };
  106. //*****************************************************************************
  107. //
  108. // Maximum number of VCO entries in the g_pui32XTALtoVCO and
  109. // g_pui32VCOFrequencies structures for a device.
  110. //
  111. //*****************************************************************************
  112. #define MAX_VCO_ENTRIES 2
  113. #define MAX_XTAL_ENTRIES 18
  114. //*****************************************************************************
  115. //
  116. // These macros are used in the g_pui32XTALtoVCO table to make it more
  117. // readable.
  118. //
  119. //*****************************************************************************
  120. #define PLL_M_TO_REG(mi, mf) \
  121. ((uint32_t)mi | (uint32_t)(mf << SYSCTL_PLLFREQ0_MFRAC_S))
  122. #define PLL_N_TO_REG(n) \
  123. ((uint32_t)(n - 1) << SYSCTL_PLLFREQ1_N_S)
  124. #define PLL_Q_TO_REG(q) \
  125. ((uint32_t)(q - 1) << SYSCTL_PLLFREQ1_Q_S)
  126. //*****************************************************************************
  127. //
  128. // Look up of the values that go into the PLLFREQ0 and PLLFREQ1 registers.
  129. //
  130. //*****************************************************************************
  131. static const uint32_t g_pppui32XTALtoVCO[MAX_VCO_ENTRIES][MAX_XTAL_ENTRIES][3] =
  132. {
  133. {
  134. //
  135. // VCO 320 MHz
  136. //
  137. { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz
  138. { PLL_M_TO_REG(62, 512), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz
  139. { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 6 MHz
  140. { PLL_M_TO_REG(52, 85), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz
  141. { PLL_M_TO_REG(43, 412), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz
  142. { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz
  143. { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz
  144. { PLL_M_TO_REG(32, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz
  145. { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 12 MHz
  146. { PLL_M_TO_REG(26, 43), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz
  147. { PLL_M_TO_REG(23, 613), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz
  148. { PLL_M_TO_REG(22, 358), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz
  149. { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz
  150. { PLL_M_TO_REG(19, 544), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz
  151. { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(9), PLL_Q_TO_REG(2) }, // 18 MHz
  152. { PLL_M_TO_REG(16, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz
  153. { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 24 MHz
  154. { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz
  155. },
  156. {
  157. //
  158. // VCO 480 MHz
  159. //
  160. { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz
  161. { PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz
  162. { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6 MHz
  163. { PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz
  164. { PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz
  165. { PLL_M_TO_REG(60, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz
  166. { PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz
  167. { PLL_M_TO_REG(48, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz
  168. { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12 MHz
  169. { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz
  170. { PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz
  171. { PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz
  172. { PLL_M_TO_REG(30, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz
  173. { PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz
  174. { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 18 MHz
  175. { PLL_M_TO_REG(24, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz
  176. { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 24 MHz
  177. { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz
  178. },
  179. };
  180. //*****************************************************************************
  181. //
  182. // The mapping of system clock frequency to flash memory timing parameters.
  183. //
  184. //*****************************************************************************
  185. static const struct
  186. {
  187. uint32_t ui32Frequency;
  188. uint32_t ui32MemTiming;
  189. }
  190. g_sXTALtoMEMTIM[] =
  191. {
  192. { 16000000, (SYSCTL_MEMTIM0_FBCHT_0_5 | SYSCTL_MEMTIM0_FBCE |
  193. (0 << SYSCTL_MEMTIM0_FWS_S) |
  194. SYSCTL_MEMTIM0_EBCHT_0_5 | SYSCTL_MEMTIM0_EBCE |
  195. (0 << SYSCTL_MEMTIM0_EWS_S) |
  196. SYSCTL_MEMTIM0_MB1) },
  197. { 40000000, (SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_FWS_S) |
  198. SYSCTL_MEMTIM0_EBCHT_1_5 | (1 << SYSCTL_MEMTIM0_EWS_S) |
  199. SYSCTL_MEMTIM0_MB1) },
  200. { 60000000, (SYSCTL_MEMTIM0_FBCHT_2 | (2 << SYSCTL_MEMTIM0_FWS_S) |
  201. SYSCTL_MEMTIM0_EBCHT_2 | (2 << SYSCTL_MEMTIM0_EWS_S) |
  202. SYSCTL_MEMTIM0_MB1) },
  203. { 80000000, (SYSCTL_MEMTIM0_FBCHT_2_5 | (3 << SYSCTL_MEMTIM0_FWS_S) |
  204. SYSCTL_MEMTIM0_EBCHT_2_5 | (3 << SYSCTL_MEMTIM0_EWS_S) |
  205. SYSCTL_MEMTIM0_MB1) },
  206. { 100000000, (SYSCTL_MEMTIM0_FBCHT_3 | (4 << SYSCTL_MEMTIM0_FWS_S) |
  207. SYSCTL_MEMTIM0_EBCHT_3 | (4 << SYSCTL_MEMTIM0_EWS_S) |
  208. SYSCTL_MEMTIM0_MB1) },
  209. { 120000000, (SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) |
  210. SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) |
  211. SYSCTL_MEMTIM0_MB1) },
  212. };
  213. //*****************************************************************************
  214. //
  215. // Get the correct memory timings for a given system clock value.
  216. //
  217. //*****************************************************************************
  218. static uint32_t
  219. _SysCtlMemTimingGet(uint32_t ui32SysClock)
  220. {
  221. uint_fast8_t ui8Idx;
  222. //
  223. // Loop through the flash memory timings.
  224. //
  225. for(ui8Idx = 0;
  226. ui8Idx < (sizeof(g_sXTALtoMEMTIM) / sizeof(g_sXTALtoMEMTIM[0]));
  227. ui8Idx++)
  228. {
  229. //
  230. // See if the system clock frequency is less than the maximum frequency
  231. // for this flash memory timing.
  232. //
  233. if(ui32SysClock <= g_sXTALtoMEMTIM[ui8Idx].ui32Frequency)
  234. {
  235. //
  236. // This flash memory timing is the best choice for the system clock
  237. // frequency, so return it now.
  238. //
  239. return(g_sXTALtoMEMTIM[ui8Idx].ui32MemTiming);
  240. }
  241. }
  242. //
  243. // An appropriate flash memory timing could not be found, so the device is
  244. // being clocked too fast. Return the default flash memory timing.
  245. //
  246. return(0);
  247. }
  248. //*****************************************************************************
  249. //
  250. // Calculate the system frequency from the register settings base on the
  251. // oscillator input.
  252. //
  253. //*****************************************************************************
  254. static uint32_t
  255. _SysCtlFrequencyGet(uint32_t ui32Xtal)
  256. {
  257. uint32_t ui32Result;
  258. uint_fast16_t ui16F1, ui16F2;
  259. uint_fast16_t ui16PInt, ui16PFract;
  260. uint_fast8_t ui8Q, ui8N;
  261. //
  262. // Extract all of the values from the hardware registers.
  263. //
  264. ui16PFract = ((HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MFRAC_M) >>
  265. SYSCTL_PLLFREQ0_MFRAC_S);
  266. ui16PInt = HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_MINT_M;
  267. ui8Q = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_Q_M) >>
  268. SYSCTL_PLLFREQ1_Q_S) + 1);
  269. ui8N = (((HWREG(SYSCTL_PLLFREQ1) & SYSCTL_PLLFREQ1_N_M) >>
  270. SYSCTL_PLLFREQ1_N_S) + 1);
  271. //
  272. // Divide the crystal value by N.
  273. //
  274. ui32Xtal /= (uint32_t)ui8N;
  275. //
  276. // Calculate the multiplier for bits 9:5.
  277. //
  278. ui16F1 = ui16PFract / 32;
  279. //
  280. // Calculate the multiplier for bits 4:0.
  281. //
  282. ui16F2 = ui16PFract - (ui16F1 * 32);
  283. //
  284. // Get the integer portion.
  285. //
  286. ui32Result = ui32Xtal * (uint32_t)ui16PInt;
  287. //
  288. // Add first fractional bits portion(9:0).
  289. //
  290. ui32Result += (ui32Xtal * (uint32_t)ui16F1) / 32;
  291. //
  292. // Add the second fractional bits portion(4:0).
  293. //
  294. ui32Result += (ui32Xtal * (uint32_t)ui16F2) / 1024;
  295. //
  296. // Divide the result by Q.
  297. //
  298. ui32Result = ui32Result / (uint32_t)ui8Q;
  299. //
  300. // Return the resulting PLL frequency.
  301. //
  302. return(ui32Result);
  303. }
  304. //*****************************************************************************
  305. //
  306. // Look up of the possible VCO frequencies.
  307. //
  308. //*****************************************************************************
  309. static const uint32_t g_pui32VCOFrequencies[MAX_VCO_ENTRIES] =
  310. {
  311. 160000000, // VCO 320
  312. 240000000, // VCO 480
  313. };
  314. //*****************************************************************************
  315. //
  316. // The base addresses of the various peripheral control registers.
  317. //
  318. //*****************************************************************************
  319. #define SYSCTL_PPBASE 0x400fe300
  320. #define SYSCTL_SRBASE 0x400fe500
  321. #define SYSCTL_RCGCBASE 0x400fe600
  322. #define SYSCTL_SCGCBASE 0x400fe700
  323. #define SYSCTL_DCGCBASE 0x400fe800
  324. #define SYSCTL_PCBASE 0x400fe900
  325. #define SYSCTL_PRBASE 0x400fea00
  326. //*****************************************************************************
  327. //
  328. //! \internal
  329. //! Checks a peripheral identifier.
  330. //!
  331. //! \param ui32Peripheral is the peripheral identifier.
  332. //!
  333. //! This function determines if a peripheral identifier is valid.
  334. //!
  335. //! \return Returns \b true if the peripheral identifier is valid and \b false
  336. //! otherwise.
  337. //
  338. //*****************************************************************************
  339. #ifdef DEBUG
  340. static bool
  341. _SysCtlPeripheralValid(uint32_t ui32Peripheral)
  342. {
  343. return((ui32Peripheral == SYSCTL_PERIPH_ADC0) ||
  344. (ui32Peripheral == SYSCTL_PERIPH_ADC1) ||
  345. (ui32Peripheral == SYSCTL_PERIPH_CAN0) ||
  346. (ui32Peripheral == SYSCTL_PERIPH_CAN1) ||
  347. (ui32Peripheral == SYSCTL_PERIPH_COMP0) ||
  348. (ui32Peripheral == SYSCTL_PERIPH_CCM0) ||
  349. (ui32Peripheral == SYSCTL_PERIPH_EEPROM0) ||
  350. (ui32Peripheral == SYSCTL_PERIPH_EPHY0) ||
  351. (ui32Peripheral == SYSCTL_PERIPH_EMAC0) ||
  352. (ui32Peripheral == SYSCTL_PERIPH_EPI0) ||
  353. (ui32Peripheral == SYSCTL_PERIPH_FAN0) ||
  354. (ui32Peripheral == SYSCTL_PERIPH_GPIOA) ||
  355. (ui32Peripheral == SYSCTL_PERIPH_GPIOB) ||
  356. (ui32Peripheral == SYSCTL_PERIPH_GPIOC) ||
  357. (ui32Peripheral == SYSCTL_PERIPH_GPIOD) ||
  358. (ui32Peripheral == SYSCTL_PERIPH_GPIOE) ||
  359. (ui32Peripheral == SYSCTL_PERIPH_GPIOF) ||
  360. (ui32Peripheral == SYSCTL_PERIPH_GPIOG) ||
  361. (ui32Peripheral == SYSCTL_PERIPH_GPIOH) ||
  362. (ui32Peripheral == SYSCTL_PERIPH_GPIOJ) ||
  363. (ui32Peripheral == SYSCTL_PERIPH_GPIOK) ||
  364. (ui32Peripheral == SYSCTL_PERIPH_GPIOL) ||
  365. (ui32Peripheral == SYSCTL_PERIPH_GPIOM) ||
  366. (ui32Peripheral == SYSCTL_PERIPH_GPION) ||
  367. (ui32Peripheral == SYSCTL_PERIPH_GPIOP) ||
  368. (ui32Peripheral == SYSCTL_PERIPH_GPIOQ) ||
  369. (ui32Peripheral == SYSCTL_PERIPH_GPIOR) ||
  370. (ui32Peripheral == SYSCTL_PERIPH_GPIOS) ||
  371. (ui32Peripheral == SYSCTL_PERIPH_GPIOT) ||
  372. (ui32Peripheral == SYSCTL_PERIPH_HIBERNATE) ||
  373. (ui32Peripheral == SYSCTL_PERIPH_I2C0) ||
  374. (ui32Peripheral == SYSCTL_PERIPH_I2C1) ||
  375. (ui32Peripheral == SYSCTL_PERIPH_I2C2) ||
  376. (ui32Peripheral == SYSCTL_PERIPH_I2C3) ||
  377. (ui32Peripheral == SYSCTL_PERIPH_I2C4) ||
  378. (ui32Peripheral == SYSCTL_PERIPH_I2C5) ||
  379. (ui32Peripheral == SYSCTL_PERIPH_I2C6) ||
  380. (ui32Peripheral == SYSCTL_PERIPH_I2C7) ||
  381. (ui32Peripheral == SYSCTL_PERIPH_I2C8) ||
  382. (ui32Peripheral == SYSCTL_PERIPH_I2C9) ||
  383. (ui32Peripheral == SYSCTL_PERIPH_LCD0) ||
  384. (ui32Peripheral == SYSCTL_PERIPH_PWM0) ||
  385. (ui32Peripheral == SYSCTL_PERIPH_PWM1) ||
  386. (ui32Peripheral == SYSCTL_PERIPH_QEI0) ||
  387. (ui32Peripheral == SYSCTL_PERIPH_QEI1) ||
  388. (ui32Peripheral == SYSCTL_PERIPH_SSI0) ||
  389. (ui32Peripheral == SYSCTL_PERIPH_SSI1) ||
  390. (ui32Peripheral == SYSCTL_PERIPH_SSI2) ||
  391. (ui32Peripheral == SYSCTL_PERIPH_SSI3) ||
  392. (ui32Peripheral == SYSCTL_PERIPH_TIMER0) ||
  393. (ui32Peripheral == SYSCTL_PERIPH_TIMER1) ||
  394. (ui32Peripheral == SYSCTL_PERIPH_TIMER2) ||
  395. (ui32Peripheral == SYSCTL_PERIPH_TIMER3) ||
  396. (ui32Peripheral == SYSCTL_PERIPH_TIMER4) ||
  397. (ui32Peripheral == SYSCTL_PERIPH_TIMER5) ||
  398. (ui32Peripheral == SYSCTL_PERIPH_TIMER6) ||
  399. (ui32Peripheral == SYSCTL_PERIPH_TIMER7) ||
  400. (ui32Peripheral == SYSCTL_PERIPH_UART0) ||
  401. (ui32Peripheral == SYSCTL_PERIPH_UART1) ||
  402. (ui32Peripheral == SYSCTL_PERIPH_UART2) ||
  403. (ui32Peripheral == SYSCTL_PERIPH_UART3) ||
  404. (ui32Peripheral == SYSCTL_PERIPH_UART4) ||
  405. (ui32Peripheral == SYSCTL_PERIPH_UART5) ||
  406. (ui32Peripheral == SYSCTL_PERIPH_UART6) ||
  407. (ui32Peripheral == SYSCTL_PERIPH_UART7) ||
  408. (ui32Peripheral == SYSCTL_PERIPH_UDMA) ||
  409. (ui32Peripheral == SYSCTL_PERIPH_USB0) ||
  410. (ui32Peripheral == SYSCTL_PERIPH_WDOG0) ||
  411. (ui32Peripheral == SYSCTL_PERIPH_WDOG1) ||
  412. (ui32Peripheral == SYSCTL_PERIPH_WTIMER0) ||
  413. (ui32Peripheral == SYSCTL_PERIPH_WTIMER1) ||
  414. (ui32Peripheral == SYSCTL_PERIPH_WTIMER2) ||
  415. (ui32Peripheral == SYSCTL_PERIPH_WTIMER3) ||
  416. (ui32Peripheral == SYSCTL_PERIPH_WTIMER4) ||
  417. (ui32Peripheral == SYSCTL_PERIPH_WTIMER5));
  418. }
  419. #endif
  420. //*****************************************************************************
  421. //
  422. //! Gets the size of the SRAM.
  423. //!
  424. //! This function determines the size of the SRAM on the Tiva device.
  425. //!
  426. //! \return The total number of bytes of SRAM.
  427. //
  428. //*****************************************************************************
  429. uint32_t
  430. SysCtlSRAMSizeGet(void)
  431. {
  432. return((HWREG(FLASH_SSIZE) + 1) * 256);
  433. }
  434. //*****************************************************************************
  435. //
  436. //! Gets the size of the flash.
  437. //!
  438. //! This function determines the size of the flash on the Tiva device.
  439. //!
  440. //! \return The total number of bytes of flash.
  441. //
  442. //*****************************************************************************
  443. uint32_t
  444. SysCtlFlashSizeGet(void)
  445. {
  446. //
  447. // TM4C123 devices report the flash size in DC0.
  448. //
  449. if(CLASS_IS_TM4C123)
  450. {
  451. //
  452. // Compute the size of the flash.
  453. //
  454. return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800);
  455. }
  456. else
  457. {
  458. //
  459. // Get the flash size from the FLASH_PP register.
  460. //
  461. return(2048 * ((HWREG(FLASH_PP) & FLASH_PP_SIZE_M) + 1));
  462. }
  463. }
  464. //*****************************************************************************
  465. //
  466. //! Gets the size of a single eraseable sector of flash.
  467. //!
  468. //! This function determines the flash sector size on the Tiva device.
  469. //! This size determines the erase granularity of the device flash.
  470. //!
  471. //! \return The number of bytes in a single flash sector.
  472. //
  473. //*****************************************************************************
  474. uint32_t
  475. SysCtlFlashSectorSizeGet(void)
  476. {
  477. //
  478. // TM4C129 devices store the value in a different register.
  479. //
  480. if(CLASS_IS_TM4C129)
  481. {
  482. //
  483. // Get the flash sector size from the FLASH_PP register.
  484. //
  485. return(1 << (10 +
  486. ((HWREG(FLASH_PP) &
  487. FLASH_PP_MAINSS_M) >> FLASH_PP_MAINSS_S)));
  488. }
  489. else
  490. {
  491. //
  492. // The sector size is fixed at 1KB.
  493. //
  494. return(1024);
  495. }
  496. }
  497. //*****************************************************************************
  498. //
  499. //! Determines if a peripheral is present.
  500. //!
  501. //! \param ui32Peripheral is the peripheral in question.
  502. //!
  503. //! This function determines if a particular peripheral is present in the
  504. //! device. Each member of the Tiva family has a different peripheral
  505. //! set; this function determines which peripherals are present on this device.
  506. //!
  507. //! The \e ui32Peripheral parameter must be only one of the following values:
  508. //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
  509. //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
  510. //! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
  511. //! \b SYSCTL_PERIPH_EPI0,
  512. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  513. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  514. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
  515. //! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
  516. //! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
  517. //! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
  518. //! \b SYSCTL_PERIPH_HIBERNATE,
  519. //! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
  520. //! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
  521. //! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
  522. //! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
  523. //! \b SYSCTL_PERIPH_ONEWIRE0,
  524. //! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
  525. //! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
  526. //! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
  527. //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
  528. //! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
  529. //! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
  530. //! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
  531. //! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
  532. //! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
  533. //! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
  534. //! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
  535. //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
  536. //!
  537. //! \return Returns \b true if the specified peripheral is present and \b false
  538. //! if it is not.
  539. //
  540. //*****************************************************************************
  541. bool
  542. SysCtlPeripheralPresent(uint32_t ui32Peripheral)
  543. {
  544. //
  545. // Check the arguments.
  546. //
  547. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  548. //
  549. // See if this peripheral is present.
  550. //
  551. return(HWREGBITW(SYSCTL_PPBASE + ((ui32Peripheral & 0xff00) >> 8),
  552. ui32Peripheral & 0xff));
  553. }
  554. //*****************************************************************************
  555. //
  556. //! Determines if a peripheral is ready.
  557. //!
  558. //! \param ui32Peripheral is the peripheral in question.
  559. //!
  560. //! This function determines if a particular peripheral is ready to be
  561. //! accessed. The peripheral may be in a non-ready state if it is not enabled,
  562. //! is being held in reset, or is in the process of becoming ready after being
  563. //! enabled or taken out of reset.
  564. //!
  565. //! The \e ui32Peripheral parameter must be only one of the following values:
  566. //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
  567. //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
  568. //! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
  569. //! \b SYSCTL_PERIPH_EPI0,
  570. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  571. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  572. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
  573. //! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
  574. //! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
  575. //! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
  576. //! \b SYSCTL_PERIPH_HIBERNATE,
  577. //! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
  578. //! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
  579. //! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
  580. //! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
  581. //! \b SYSCTL_PERIPH_ONEWIRE0,
  582. //! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
  583. //! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
  584. //! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
  585. //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
  586. //! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
  587. //! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
  588. //! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
  589. //! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
  590. //! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
  591. //! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
  592. //! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
  593. //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
  594. //!
  595. //! \note The ability to check for a peripheral being ready varies based on the
  596. //! Tiva part in use. Please consult the data sheet for the part you are
  597. //! using to determine if this feature is available.
  598. //!
  599. //! \return Returns \b true if the specified peripheral is ready and \b false
  600. //! if it is not.
  601. //
  602. //*****************************************************************************
  603. bool
  604. SysCtlPeripheralReady(uint32_t ui32Peripheral)
  605. {
  606. //
  607. // Check the arguments.
  608. //
  609. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  610. //
  611. // See if this peripheral is ready.
  612. //
  613. return(HWREGBITW(SYSCTL_PRBASE + ((ui32Peripheral & 0xff00) >> 8),
  614. ui32Peripheral & 0xff));
  615. }
  616. //*****************************************************************************
  617. //
  618. //! Powers on a peripheral.
  619. //!
  620. //! \param ui32Peripheral is the peripheral to be powered on.
  621. //!
  622. //! This function turns on the power to a peripheral. The peripheral continues
  623. //! to receive power even when its clock is not enabled.
  624. //!
  625. //! The \e ui32Peripheral parameter must be only one of the following values:
  626. //! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC,
  627. //! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0
  628. //!
  629. //! \note The ability to power off a peripheral varies based on the Tiva
  630. //! part in use. Please consult the data sheet for the part you are using to
  631. //! determine if this feature is available.
  632. //!
  633. //! \return None.
  634. //
  635. //*****************************************************************************
  636. void
  637. SysCtlPeripheralPowerOn(uint32_t ui32Peripheral)
  638. {
  639. //
  640. // Check the arguments.
  641. //
  642. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  643. //
  644. // Power on this peripheral.
  645. //
  646. HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8),
  647. ui32Peripheral & 0xff) = 1;
  648. }
  649. //*****************************************************************************
  650. //
  651. //! Powers off a peripheral.
  652. //!
  653. //! \param ui32Peripheral is the peripheral to be powered off.
  654. //!
  655. //! This function allows the power to a peripheral to be turned off. The
  656. //! peripheral continues to receive power when its clock is enabled, but
  657. //! the power is removed when its clock is disabled.
  658. //!
  659. //! The \e ui32Peripheral parameter must be only one of the following values:
  660. //! \b SYSCTL_PERIPH_CAN0,\b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_EMAC,
  661. //! \b SYSCTL_PERIPH_EPHY, \b SYSCTL_PERIPH_LCD0, \b SYSCTL_PERIPH_USB0
  662. //!
  663. //! \note The ability to power off a peripheral varies based on the Tiva
  664. //! part in use. Please consult the data sheet for the part you are using to
  665. //! determine if this feature is available.
  666. //!
  667. //! \return None.
  668. //
  669. //*****************************************************************************
  670. void
  671. SysCtlPeripheralPowerOff(uint32_t ui32Peripheral)
  672. {
  673. //
  674. // Check the arguments.
  675. //
  676. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  677. //
  678. // Power off this peripheral.
  679. //
  680. HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8),
  681. ui32Peripheral & 0xff) = 0;
  682. }
  683. //*****************************************************************************
  684. //
  685. //! Performs a software reset of a peripheral.
  686. //!
  687. //! \param ui32Peripheral is the peripheral to reset.
  688. //!
  689. //! This function performs a software reset of the specified peripheral. An
  690. //! individual peripheral reset signal is asserted for a brief period and then
  691. //! de-asserted, returning the internal state of the peripheral to its reset
  692. //! condition.
  693. //!
  694. //! The \e ui32Peripheral parameter must be only one of the following values:
  695. //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
  696. //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
  697. //! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
  698. //! \b SYSCTL_PERIPH_EPI0,
  699. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  700. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  701. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
  702. //! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
  703. //! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
  704. //! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
  705. //! \b SYSCTL_PERIPH_HIBERNATE,
  706. //! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
  707. //! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
  708. //! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
  709. //! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
  710. //! \b SYSCTL_PERIPH_ONEWIRE0,
  711. //! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
  712. //! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
  713. //! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
  714. //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
  715. //! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
  716. //! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
  717. //! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
  718. //! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
  719. //! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
  720. //! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
  721. //! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
  722. //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
  723. //!
  724. //! \return None.
  725. //
  726. //*****************************************************************************
  727. void
  728. SysCtlPeripheralReset(uint32_t ui32Peripheral)
  729. {
  730. volatile uint_fast8_t ui8Delay;
  731. //
  732. // Check the arguments.
  733. //
  734. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  735. //
  736. // Put the peripheral into the reset state.
  737. //
  738. HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8),
  739. ui32Peripheral & 0xff) = 1;
  740. //
  741. // Delay for a little bit.
  742. //
  743. for(ui8Delay = 0; ui8Delay < 16; ui8Delay++)
  744. {
  745. }
  746. //
  747. // Take the peripheral out of the reset state.
  748. //
  749. HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8),
  750. ui32Peripheral & 0xff) = 0;
  751. }
  752. //*****************************************************************************
  753. //
  754. //! Enables a peripheral.
  755. //!
  756. //! \param ui32Peripheral is the peripheral to enable.
  757. //!
  758. //! This function enables a peripheral. At power-up, all peripherals are
  759. //! disabled; they must be enabled in order to operate or respond to register
  760. //! reads/writes.
  761. //!
  762. //! The \e ui32Peripheral parameter must be only one of the following values:
  763. //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
  764. //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
  765. //! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
  766. //! \b SYSCTL_PERIPH_EPI0,
  767. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  768. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  769. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
  770. //! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
  771. //! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
  772. //! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
  773. //! \b SYSCTL_PERIPH_HIBERNATE,
  774. //! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
  775. //! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
  776. //! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
  777. //! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
  778. //! \b SYSCTL_PERIPH_ONEWIRE0,
  779. //! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
  780. //! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
  781. //! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
  782. //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
  783. //! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
  784. //! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
  785. //! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
  786. //! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
  787. //! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
  788. //! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
  789. //! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
  790. //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
  791. //!
  792. //! \note It takes five clock cycles after the write to enable a peripheral
  793. //! before the the peripheral is actually enabled. During this time, attempts
  794. //! to access the peripheral result in a bus fault. Care should be taken
  795. //! to ensure that the peripheral is not accessed during this brief time
  796. //! period.
  797. //!
  798. //! \return None.
  799. //
  800. //*****************************************************************************
  801. void
  802. SysCtlPeripheralEnable(uint32_t ui32Peripheral)
  803. {
  804. //
  805. // Check the arguments.
  806. //
  807. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  808. //
  809. // Enable this peripheral.
  810. //
  811. HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
  812. ui32Peripheral & 0xff) = 1;
  813. }
  814. //*****************************************************************************
  815. //
  816. //! Disables a peripheral.
  817. //!
  818. //! \param ui32Peripheral is the peripheral to disable.
  819. //!
  820. //! This function disables a peripheral. Once disabled, they do not operate or
  821. //! respond to register reads/writes.
  822. //!
  823. //! The \e ui32Peripheral parameter must be only one of the following values:
  824. //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
  825. //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
  826. //! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
  827. //! \b SYSCTL_PERIPH_EPI0,
  828. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  829. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  830. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
  831. //! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
  832. //! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
  833. //! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
  834. //! \b SYSCTL_PERIPH_HIBERNATE,
  835. //! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
  836. //! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
  837. //! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
  838. //! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
  839. //! \b SYSCTL_PERIPH_ONEWIRE0,
  840. //! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
  841. //! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
  842. //! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
  843. //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
  844. //! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
  845. //! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
  846. //! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
  847. //! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
  848. //! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
  849. //! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
  850. //! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
  851. //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
  852. //!
  853. //! \return None.
  854. //
  855. //*****************************************************************************
  856. void
  857. SysCtlPeripheralDisable(uint32_t ui32Peripheral)
  858. {
  859. //
  860. // Check the arguments.
  861. //
  862. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  863. //
  864. // Disable this peripheral.
  865. //
  866. HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
  867. ui32Peripheral & 0xff) = 0;
  868. }
  869. //*****************************************************************************
  870. //
  871. //! Enables a peripheral in sleep mode.
  872. //!
  873. //! \param ui32Peripheral is the peripheral to enable in sleep mode.
  874. //!
  875. //! This function allows a peripheral to continue operating when the processor
  876. //! goes into sleep mode. Because the clocking configuration of the device
  877. //! does not change, any peripheral can safely continue operating while the
  878. //! processor is in sleep mode and can therefore wake the processor from sleep
  879. //! mode.
  880. //!
  881. //! Sleep mode clocking of peripherals must be enabled via
  882. //! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
  883. //! configuration is maintained but has no effect when sleep mode is entered.
  884. //!
  885. //! The \e ui32Peripheral parameter must be only one of the following values:
  886. //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
  887. //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
  888. //! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
  889. //! \b SYSCTL_PERIPH_EPI0,
  890. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  891. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  892. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
  893. //! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
  894. //! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
  895. //! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
  896. //! \b SYSCTL_PERIPH_HIBERNATE,
  897. //! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
  898. //! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
  899. //! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
  900. //! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
  901. //! \b SYSCTL_PERIPH_ONEWIRE0,
  902. //! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
  903. //! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
  904. //! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
  905. //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
  906. //! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
  907. //! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
  908. //! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
  909. //! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
  910. //! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
  911. //! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
  912. //! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
  913. //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
  914. //!
  915. //! \return None.
  916. //
  917. //*****************************************************************************
  918. void
  919. SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral)
  920. {
  921. //
  922. // Check the arguments.
  923. //
  924. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  925. //
  926. // Enable this peripheral in sleep mode.
  927. //
  928. HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
  929. ui32Peripheral & 0xff) = 1;
  930. }
  931. //*****************************************************************************
  932. //
  933. //! Disables a peripheral in sleep mode.
  934. //!
  935. //! \param ui32Peripheral is the peripheral to disable in sleep mode.
  936. //!
  937. //! This function causes a peripheral to stop operating when the processor goes
  938. //! into sleep mode. Disabling peripherals while in sleep mode helps to lower
  939. //! the current draw of the device. If enabled (via SysCtlPeripheralEnable()),
  940. //! the peripheral automatically resumes operation when the processor
  941. //! leaves sleep mode, maintaining its entire state from before sleep mode was
  942. //! entered.
  943. //!
  944. //! Sleep mode clocking of peripherals must be enabled via
  945. //! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
  946. //! configuration is maintained but has no effect when sleep mode is entered.
  947. //!
  948. //! The \e ui32Peripheral parameter must be only one of the following values:
  949. //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
  950. //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
  951. //! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
  952. //! \b SYSCTL_PERIPH_EPI0,
  953. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  954. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  955. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
  956. //! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
  957. //! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
  958. //! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
  959. //! \b SYSCTL_PERIPH_HIBERNATE,
  960. //! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
  961. //! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
  962. //! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
  963. //! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
  964. //! \b SYSCTL_PERIPH_ONEWIRE0,
  965. //! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
  966. //! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
  967. //! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
  968. //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
  969. //! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
  970. //! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
  971. //! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
  972. //! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
  973. //! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
  974. //! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
  975. //! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
  976. //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
  977. //!
  978. //! \return None.
  979. //
  980. //*****************************************************************************
  981. void
  982. SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral)
  983. {
  984. //
  985. // Check the arguments.
  986. //
  987. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  988. //
  989. // Disable this peripheral in sleep mode.
  990. //
  991. HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
  992. ui32Peripheral & 0xff) = 0;
  993. }
  994. //*****************************************************************************
  995. //
  996. //! Enables a peripheral in deep-sleep mode.
  997. //!
  998. //! \param ui32Peripheral is the peripheral to enable in deep-sleep mode.
  999. //!
  1000. //! This function allows a peripheral to continue operating when the processor
  1001. //! goes into deep-sleep mode. Because the clocking configuration of the
  1002. //! device may change, not all peripherals can safely continue operating while
  1003. //! the processor is in deep-sleep mode. Those that must run at a particular
  1004. //! frequency (such as a UART) do not work as expected if the clock changes.
  1005. //! It is the responsibility of the caller to make sensible choices.
  1006. //!
  1007. //! Deep-sleep mode clocking of peripherals must be enabled via
  1008. //! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
  1009. //! configuration is maintained but has no effect when deep-sleep mode is
  1010. //! entered.
  1011. //!
  1012. //! The \e ui32Peripheral parameter must be only one of the following values:
  1013. //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
  1014. //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
  1015. //! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
  1016. //! \b SYSCTL_PERIPH_EPI0,
  1017. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  1018. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  1019. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
  1020. //! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
  1021. //! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
  1022. //! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
  1023. //! \b SYSCTL_PERIPH_HIBERNATE,
  1024. //! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
  1025. //! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
  1026. //! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
  1027. //! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
  1028. //! \b SYSCTL_PERIPH_ONEWIRE0,
  1029. //! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
  1030. //! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
  1031. //! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
  1032. //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
  1033. //! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
  1034. //! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
  1035. //! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
  1036. //! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
  1037. //! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
  1038. //! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
  1039. //! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
  1040. //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
  1041. //!
  1042. //! \return None.
  1043. //
  1044. //*****************************************************************************
  1045. void
  1046. SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral)
  1047. {
  1048. //
  1049. // Check the arguments.
  1050. //
  1051. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  1052. //
  1053. // Enable this peripheral in deep-sleep mode.
  1054. //
  1055. HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
  1056. ui32Peripheral & 0xff) = 1;
  1057. }
  1058. //*****************************************************************************
  1059. //
  1060. //! Disables a peripheral in deep-sleep mode.
  1061. //!
  1062. //! \param ui32Peripheral is the peripheral to disable in deep-sleep mode.
  1063. //!
  1064. //! This function causes a peripheral to stop operating when the processor goes
  1065. //! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
  1066. //! to lower the current draw of the device, and can keep peripherals that
  1067. //! require a particular clock frequency from operating when the clock changes
  1068. //! as a result of entering deep-sleep mode. If enabled (via
  1069. //! SysCtlPeripheralEnable()), the peripheral automatically resumes
  1070. //! operation when the processor leaves deep-sleep mode, maintaining its entire
  1071. //! state from before deep-sleep mode was entered.
  1072. //!
  1073. //! Deep-sleep mode clocking of peripherals must be enabled via
  1074. //! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
  1075. //! configuration is maintained but has no effect when deep-sleep mode is
  1076. //! entered.
  1077. //!
  1078. //! The \e ui32Peripheral parameter must be only one of the following values:
  1079. //! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
  1080. //! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CCM0,\b SYSCTL_PERIPH_COMP0,
  1081. //! \b SYSCTL_PERIPH_EEPROM0, \b SYSCTL_PERIPH_EMAC, \b SYSCTL_PERIPH_EPHY,
  1082. //! \b SYSCTL_PERIPH_EPI0,
  1083. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  1084. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  1085. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
  1086. //! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
  1087. //! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
  1088. //! \b SYSCTL_PERIPH_GPIOR, \b SYSCTL_PERIPH_GPIOS, \b SYSCTL_PERIPH_GPIOT,
  1089. //! \b SYSCTL_PERIPH_HIBERNATE,
  1090. //! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
  1091. //! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
  1092. //! \b SYSCTL_PERIPH_I2C6, \b SYSCTL_PERIPH_I2C7, \b SYSCTL_PERIPH_I2C8,
  1093. //! \b SYSCTL_PERIPH_I2C9, \b SYSCTL_PERIPH_LCD0,
  1094. //! \b SYSCTL_PERIPH_ONEWIRE0,
  1095. //! \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1, \b SYSCTL_PERIPH_QEI0,
  1096. //! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
  1097. //! \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3, \b SYSCTL_PERIPH_TIMER0,
  1098. //! \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3,
  1099. //! \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5, \b SYSCTL_PERIPH_TIMER6,
  1100. //! \b SYSCTL_PERIPH_TIMER7, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
  1101. //! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4,
  1102. //! \b SYSCTL_PERIPH_UART5, \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7,
  1103. //! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0,
  1104. //! \b SYSCTL_PERIPH_WDOG1, \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
  1105. //! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
  1106. //! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5
  1107. //!
  1108. //! \return None.
  1109. //
  1110. //*****************************************************************************
  1111. void
  1112. SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral)
  1113. {
  1114. //
  1115. // Check the arguments.
  1116. //
  1117. ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
  1118. //
  1119. // Disable this peripheral in deep-sleep mode.
  1120. //
  1121. HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
  1122. ui32Peripheral & 0xff) = 0;
  1123. }
  1124. //*****************************************************************************
  1125. //
  1126. //! Controls peripheral clock gating in sleep and deep-sleep mode.
  1127. //!
  1128. //! \param bEnable is a boolean that is \b true if the sleep and deep-sleep
  1129. //! peripheral configuration should be used and \b false if not.
  1130. //!
  1131. //! This function controls how peripherals are clocked when the processor goes
  1132. //! into sleep or deep-sleep mode. By default, the peripherals are clocked the
  1133. //! same as in run mode; if peripheral clock gating is enabled, they are
  1134. //! clocked according to the configuration set by
  1135. //! SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(),
  1136. //! SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable().
  1137. //!
  1138. //! \return None.
  1139. //
  1140. //*****************************************************************************
  1141. void
  1142. SysCtlPeripheralClockGating(bool bEnable)
  1143. {
  1144. if(CLASS_IS_TM4C123)
  1145. {
  1146. //
  1147. // Enable peripheral clock gating as requested.
  1148. //
  1149. if(bEnable)
  1150. {
  1151. HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG;
  1152. }
  1153. else
  1154. {
  1155. HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG);
  1156. }
  1157. }
  1158. else
  1159. {
  1160. //
  1161. // Enable peripheral clock gating as requested.
  1162. //
  1163. if(bEnable)
  1164. {
  1165. HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_ACG;
  1166. }
  1167. else
  1168. {
  1169. HWREG(SYSCTL_RSCLKCFG) &= ~SYSCTL_RSCLKCFG_ACG;
  1170. }
  1171. }
  1172. }
  1173. //*****************************************************************************
  1174. //
  1175. //! Registers an interrupt handler for the system control interrupt.
  1176. //!
  1177. //! \param pfnHandler is a pointer to the function to be called when the system
  1178. //! control interrupt occurs.
  1179. //!
  1180. //! This function registers the handler to be called when a system control
  1181. //! interrupt occurs. This function enables the global interrupt in the
  1182. //! interrupt controller; specific system control interrupts must be enabled
  1183. //! via SysCtlIntEnable(). It is the interrupt handler's responsibility to
  1184. //! clear the interrupt source via SysCtlIntClear().
  1185. //!
  1186. //! System control can generate interrupts when the PLL achieves lock, if the
  1187. //! internal LDO current limit is exceeded, if the internal oscillator fails,
  1188. //! if the main oscillator fails, if the internal LDO output voltage droops too
  1189. //! much, if the external voltage droops too much, or if the PLL fails.
  1190. //!
  1191. //! \sa IntRegister() for important information about registering interrupt
  1192. //! handlers.
  1193. //!
  1194. //! \note The events that cause system control interrupts vary based on the
  1195. //! Tiva part in use. Please consult the data sheet for the part you are
  1196. //! using to determine which interrupt sources are available.
  1197. //!
  1198. //! \return None.
  1199. //
  1200. //*****************************************************************************
  1201. void
  1202. SysCtlIntRegister(void (*pfnHandler)(void))
  1203. {
  1204. //
  1205. // Register the interrupt handler, returning an error if an error occurs.
  1206. //
  1207. IntRegister(INT_SYSCTL_TM4C123, pfnHandler);
  1208. //
  1209. // Enable the system control interrupt.
  1210. //
  1211. IntEnable(INT_SYSCTL_TM4C123);
  1212. }
  1213. //*****************************************************************************
  1214. //
  1215. //! Unregisters the interrupt handler for the system control interrupt.
  1216. //!
  1217. //! This function unregisters the handler to be called when a system control
  1218. //! interrupt occurs. This function also masks off the interrupt in the
  1219. //! interrupt controller so that the interrupt handler no longer is called.
  1220. //!
  1221. //! \sa IntRegister() for important information about registering interrupt
  1222. //! handlers.
  1223. //!
  1224. //! \return None.
  1225. //
  1226. //*****************************************************************************
  1227. void
  1228. SysCtlIntUnregister(void)
  1229. {
  1230. //
  1231. // Disable the interrupt.
  1232. //
  1233. IntDisable(INT_SYSCTL_TM4C123);
  1234. //
  1235. // Unregister the interrupt handler.
  1236. //
  1237. IntUnregister(INT_SYSCTL_TM4C123);
  1238. }
  1239. //*****************************************************************************
  1240. //
  1241. //! Enables individual system control interrupt sources.
  1242. //!
  1243. //! \param ui32Ints is a bit mask of the interrupt sources to be enabled. Must
  1244. //! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK,
  1245. //! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK,
  1246. //! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or
  1247. //! \b SYSCTL_INT_BOR1.
  1248. //!
  1249. //! This function enables the indicated system control interrupt sources. Only
  1250. //! the sources that are enabled can be reflected to the processor interrupt;
  1251. //! disabled sources have no effect on the processor.
  1252. //!
  1253. //! \note The interrupt sources vary based on the Tiva part in use.
  1254. //! Please consult the data sheet for the part you are using to determine
  1255. //! which interrupt sources are available.
  1256. //!
  1257. //! \return None.
  1258. //
  1259. //*****************************************************************************
  1260. void
  1261. SysCtlIntEnable(uint32_t ui32Ints)
  1262. {
  1263. //
  1264. // Enable the specified interrupts.
  1265. //
  1266. HWREG(SYSCTL_IMC) |= ui32Ints;
  1267. }
  1268. //*****************************************************************************
  1269. //
  1270. //! Disables individual system control interrupt sources.
  1271. //!
  1272. //! \param ui32Ints is a bit mask of the interrupt sources to be disabled.
  1273. //! Must be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK,
  1274. //! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK,
  1275. //! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or
  1276. //! \b SYSCTL_INT_BOR1.
  1277. //!
  1278. //! This function disables the indicated system control interrupt sources.
  1279. //! Only the sources that are enabled can be reflected to the processor
  1280. //! interrupt; disabled sources have no effect on the processor.
  1281. //!
  1282. //! \note The interrupt sources vary based on the Tiva part in use.
  1283. //! Please consult the data sheet for the part you are using to determine
  1284. //! which interrupt sources are available.
  1285. //!
  1286. //! \return None.
  1287. //
  1288. //*****************************************************************************
  1289. void
  1290. SysCtlIntDisable(uint32_t ui32Ints)
  1291. {
  1292. //
  1293. // Disable the specified interrupts.
  1294. //
  1295. HWREG(SYSCTL_IMC) &= ~(ui32Ints);
  1296. }
  1297. //*****************************************************************************
  1298. //
  1299. //! Clears system control interrupt sources.
  1300. //!
  1301. //! \param ui32Ints is a bit mask of the interrupt sources to be cleared. Must
  1302. //! be a logical OR of \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK,
  1303. //! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK,
  1304. //! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or
  1305. //! \b SYSCTL_INT_BOR1.
  1306. //!
  1307. //! The specified system control interrupt sources are cleared, so that they no
  1308. //! longer assert. This function must be called in the interrupt handler to
  1309. //! keep it from being called again immediately on exit.
  1310. //!
  1311. //! \note Because there is a write buffer in the Cortex-M processor, it may
  1312. //! take several clock cycles before the interrupt source is actually cleared.
  1313. //! Therefore, it is recommended that the interrupt source be cleared early in
  1314. //! the interrupt handler (as opposed to the very last action) to avoid
  1315. //! returning from the interrupt handler before the interrupt source is
  1316. //! actually cleared. Failure to do so may result in the interrupt handler
  1317. //! being immediately reentered (because the interrupt controller still sees
  1318. //! the interrupt source asserted).
  1319. //!
  1320. //! \note The interrupt sources vary based on the Tiva part in use.
  1321. //! Please consult the data sheet for the part you are using to determine
  1322. //! which interrupt sources are available.
  1323. //!
  1324. //! \return None.
  1325. //
  1326. //*****************************************************************************
  1327. void
  1328. SysCtlIntClear(uint32_t ui32Ints)
  1329. {
  1330. //
  1331. // Clear the requested interrupt sources.
  1332. //
  1333. HWREG(SYSCTL_MISC) = ui32Ints;
  1334. }
  1335. //*****************************************************************************
  1336. //
  1337. //! Gets the current interrupt status.
  1338. //!
  1339. //! \param bMasked is false if the raw interrupt status is required and true if
  1340. //! the masked interrupt status is required.
  1341. //!
  1342. //! This function returns the interrupt status for the system controller.
  1343. //! Either the raw interrupt status or the status of interrupts that are
  1344. //! allowed to reflect to the processor can be returned.
  1345. //!
  1346. //! \note The interrupt sources vary based on the Tiva part in use.
  1347. //! Please consult the data sheet for the part you are using to determine
  1348. //! which interrupt sources are available.
  1349. //!
  1350. //! \return The current interrupt status, enumerated as a bit field of
  1351. //! \b SYSCTL_INT_BOR0, \b SYSCTL_INT_VDDA_OK,
  1352. //! \b SYSCTL_INT_MOSC_PUP, \b SYSCTL_INT_USBPLL_LOCK,
  1353. //! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_BOR, and/or
  1354. //! \b SYSCTL_INT_BOR1.
  1355. //
  1356. //*****************************************************************************
  1357. uint32_t
  1358. SysCtlIntStatus(bool bMasked)
  1359. {
  1360. //
  1361. // Return either the interrupt status or the raw interrupt status as
  1362. // requested.
  1363. //
  1364. if(bMasked)
  1365. {
  1366. return(HWREG(SYSCTL_MISC));
  1367. }
  1368. else
  1369. {
  1370. return(HWREG(SYSCTL_RIS));
  1371. }
  1372. }
  1373. //*****************************************************************************
  1374. //
  1375. //! Sets the output voltage of the LDO when the device enters sleep mode.
  1376. //!
  1377. //! \param ui32Voltage is the required output voltage from the LDO while in
  1378. //! sleep mode.
  1379. //!
  1380. //! This function sets the output voltage of the LDO while in sleep mode.
  1381. //! The \e ui32Voltage parameter must be one of the following values:
  1382. //! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V,
  1383. //! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or
  1384. //! \b SYSCTL_LDO_1_20V.
  1385. //!
  1386. //! \note The availability of this feature, the default LDO voltage, and the
  1387. //! adjustment range varies with the Tiva part in use. Please consult the
  1388. //! data sheet for the part you are using to determine whether this support is
  1389. //! available.
  1390. //!
  1391. //! \return None.
  1392. //
  1393. //*****************************************************************************
  1394. void
  1395. SysCtlLDOSleepSet(uint32_t ui32Voltage)
  1396. {
  1397. //
  1398. // Check the arguments.
  1399. //
  1400. ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) ||
  1401. (ui32Voltage == SYSCTL_LDO_0_95V) ||
  1402. (ui32Voltage == SYSCTL_LDO_1_00V) ||
  1403. (ui32Voltage == SYSCTL_LDO_1_05V) ||
  1404. (ui32Voltage == SYSCTL_LDO_1_10V) ||
  1405. (ui32Voltage == SYSCTL_LDO_1_15V) ||
  1406. (ui32Voltage == SYSCTL_LDO_1_20V));
  1407. //
  1408. // Set the sleep-mode LDO voltage to the requested value.
  1409. //
  1410. HWREG(SYSCTL_LDOSPCTL) = ui32Voltage;
  1411. }
  1412. //*****************************************************************************
  1413. //
  1414. //! Returns the output voltage of the LDO when the device enters sleep mode.
  1415. //!
  1416. //! This function determines the output voltage of the LDO while in sleep mode,
  1417. //! as specified by the control register.
  1418. //!
  1419. //! \note The availability of this feature, the default LDO voltage, and the
  1420. //! adjustment range varies with the Tiva part in use. Please consult the
  1421. //! data sheet for the part you are using to determine whether this support is
  1422. //! available.
  1423. //!
  1424. //! \return Returns the sleep-mode voltage of the LDO and is one of
  1425. //! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V,
  1426. //! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or
  1427. //! \b SYSCTL_LDO_1_20V.
  1428. //
  1429. //*****************************************************************************
  1430. uint32_t
  1431. SysCtlLDOSleepGet(void)
  1432. {
  1433. //
  1434. // Return the sleep-mode LDO voltage setting.
  1435. //
  1436. return(HWREG(SYSCTL_LDOSPCTL));
  1437. }
  1438. //*****************************************************************************
  1439. //
  1440. //! Sets the output voltage of the LDO when the device enters deep-sleep
  1441. //! mode.
  1442. //!
  1443. //! \param ui32Voltage is the required output voltage from the LDO while in
  1444. //! deep-sleep mode.
  1445. //!
  1446. //! This function sets the output voltage of the LDO while in deep-sleep mode.
  1447. //! The \e ui32Voltage parameter specifies the output voltage of the LDO and
  1448. //! must be one of the following values: \b SYSCTL_LDO_0_90V,
  1449. //! \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V, \b SYSCTL_LDO_1_05V,
  1450. //! \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or \b SYSCTL_LDO_1_20V.
  1451. //!
  1452. //! \note The availability of this feature, the default LDO voltage, and the
  1453. //! adjustment range varies with the Tiva part in use. Please consult the
  1454. //! data sheet for the part you are using to determine whether this support is
  1455. //! available.
  1456. //!
  1457. //! \return None.
  1458. //
  1459. //*****************************************************************************
  1460. void
  1461. SysCtlLDODeepSleepSet(uint32_t ui32Voltage)
  1462. {
  1463. //
  1464. // Check the arguments.
  1465. //
  1466. ASSERT((ui32Voltage == SYSCTL_LDO_0_90V) ||
  1467. (ui32Voltage == SYSCTL_LDO_0_95V) ||
  1468. (ui32Voltage == SYSCTL_LDO_1_00V) ||
  1469. (ui32Voltage == SYSCTL_LDO_1_05V) ||
  1470. (ui32Voltage == SYSCTL_LDO_1_10V) ||
  1471. (ui32Voltage == SYSCTL_LDO_1_15V) ||
  1472. (ui32Voltage == SYSCTL_LDO_1_20V));
  1473. //
  1474. // Set the deep-sleep LDO voltage to the requested value.
  1475. //
  1476. HWREG(SYSCTL_LDODPCTL) = ui32Voltage;
  1477. }
  1478. //*****************************************************************************
  1479. //
  1480. //! Returns the output voltage of the LDO when the device enters deep-sleep
  1481. //! mode.
  1482. //!
  1483. //! This function returns the output voltage of the LDO when the device is
  1484. //! in deep-sleep mode, as specified by the control register.
  1485. //!
  1486. //! \note The availability of this feature, the default LDO voltage, and the
  1487. //! adjustment range varies with the Tiva part in use. Please consult the
  1488. //! data sheet for the part you are using to determine whether this support is
  1489. //! available.
  1490. //!
  1491. //! \return Returns the deep-sleep-mode voltage of the LDO; is one of
  1492. //! \b SYSCTL_LDO_0_90V, \b SYSCTL_LDO_0_95V, \b SYSCTL_LDO_1_00V,
  1493. //! \b SYSCTL_LDO_1_05V, \b SYSCTL_LDO_1_10V, \b SYSCTL_LDO_1_15V, or
  1494. //! \b SYSCTL_LDO_1_20V.
  1495. //
  1496. //*****************************************************************************
  1497. uint32_t
  1498. SysCtlLDODeepSleepGet(void)
  1499. {
  1500. //
  1501. // Return the deep-sleep-mode LDO voltage setting.
  1502. //
  1503. return(HWREG(SYSCTL_LDODPCTL));
  1504. }
  1505. //*****************************************************************************
  1506. //
  1507. //! Configures the power to the flash and SRAM while in sleep mode.
  1508. //!
  1509. //! \param ui32Config is the required flash and SRAM power configuration.
  1510. //!
  1511. //! This function allows the power configuration of the flash and SRAM while in
  1512. //! sleep mode to be set. The \e ui32Config parameter is the logical OR of the
  1513. //! flash power configuration and the SRAM power configuration.
  1514. //!
  1515. //! The flash power configuration is specified as either:
  1516. //!
  1517. //! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode,
  1518. //! providing fast wake-up time but higher power consumption.
  1519. //! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing
  1520. //! reduced power consumption but longer wake-up time.
  1521. //!
  1522. //! The SRAM power configuration is specified as one of:
  1523. //!
  1524. //! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing
  1525. //! fast wake-up time but higher power consumption.
  1526. //! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode,
  1527. //! providing reduced power consumption but longer wake-up time.
  1528. //! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode,
  1529. //! providing further reduced power consumption but longer wake-up time.
  1530. //!
  1531. //! \note The availability of this feature varies with the Tiva part in
  1532. //! use. Please consult the data sheet for the part you are using to determine
  1533. //! whether this support is available.
  1534. //!
  1535. //! \return None.
  1536. //
  1537. //*****************************************************************************
  1538. void
  1539. SysCtlSleepPowerSet(uint32_t ui32Config)
  1540. {
  1541. //
  1542. // Set the sleep-mode flash and SRAM power configuration.
  1543. //
  1544. HWREG(SYSCTL_SLPPWRCFG) = ui32Config;
  1545. }
  1546. //*****************************************************************************
  1547. //
  1548. //! Configures the power to the flash and SRAM while in deep-sleep mode.
  1549. //!
  1550. //! \param ui32Config is the required flash and SRAM power configuration.
  1551. //!
  1552. //! This function allows the power configuration of the flash and SRAM while in
  1553. //! deep-sleep mode to be set. The \e ui32Config parameter is the logical OR
  1554. //! of the flash power configuration and the SRAM power configuration.
  1555. //!
  1556. //! The flash power configuration is specified as either:
  1557. //!
  1558. //! - \b SYSCTL_FLASH_NORMAL - The flash is left in fully powered mode,
  1559. //! providing fast wake-up time but higher power consumption.
  1560. //! - \b SYSCTL_FLASH_LOW_POWER - The flash is in low power mode, providing
  1561. //! reduced power consumption but longer wake-up time.
  1562. //!
  1563. //! The SRAM power configuration is specified as one of:
  1564. //!
  1565. //! - \b SYSCTL_LDO_SLEEP - The LDO is in sleep mode.
  1566. //! - \b SYSCTL_TEMP_LOW_POWER - The temperature sensor in low power mode.
  1567. //! - \b SYSCTL_SRAM_NORMAL - The SRAM is left in fully powered mode, providing
  1568. //! fast wake-up time but higher power consumption.
  1569. //! - \b SYSCTL_SRAM_STANDBY - The SRAM is placed into a lower power mode,
  1570. //! providing reduced power consumption but longer wake-up time.
  1571. //! - \b SYSCTL_SRAM_LOW_POWER - The SRAM is placed into lowest power mode,
  1572. //! providing further reduced power consumption but longer wake-up time.
  1573. //!
  1574. //! \note The availability of this feature varies with the Tiva part in
  1575. //! use. Please consult the data sheet for the part you are using to determine
  1576. //! whether this support is available.
  1577. //!
  1578. //! \return None.
  1579. //
  1580. //*****************************************************************************
  1581. void
  1582. SysCtlDeepSleepPowerSet(uint32_t ui32Config)
  1583. {
  1584. //
  1585. // Set the deep-sleep-mode flash and SRAM power configuration.
  1586. //
  1587. HWREG(SYSCTL_DSLPPWRCFG) = ui32Config;
  1588. }
  1589. //*****************************************************************************
  1590. //
  1591. //! Resets the device.
  1592. //!
  1593. //! This function performs a software reset of the entire device. The
  1594. //! processor and all peripherals are reset and all device registers are
  1595. //! returned to their default values (with the exception of the reset cause
  1596. //! register, which maintains its current value but has the software reset
  1597. //! bit set as well).
  1598. //!
  1599. //! \return This function does not return.
  1600. //
  1601. //*****************************************************************************
  1602. void
  1603. SysCtlReset(void)
  1604. {
  1605. //
  1606. // Perform a software reset request. This request causes the device to
  1607. // reset, no further code is executed.
  1608. //
  1609. HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;
  1610. //
  1611. // The device should have reset, so this should never be reached. Just in
  1612. // case, loop forever.
  1613. //
  1614. while(1)
  1615. {
  1616. }
  1617. }
  1618. //*****************************************************************************
  1619. //
  1620. //! Puts the processor into sleep mode.
  1621. //!
  1622. //! This function places the processor into sleep mode; it does not return
  1623. //! until the processor returns to run mode. The peripherals that are enabled
  1624. //! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the
  1625. //! processor (if automatic clock gating is enabled with
  1626. //! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
  1627. //! operate).
  1628. //!
  1629. //! \return None.
  1630. //
  1631. //*****************************************************************************
  1632. void
  1633. SysCtlSleep(void)
  1634. {
  1635. //
  1636. // Wait for an interrupt.
  1637. //
  1638. CPUwfi();
  1639. }
  1640. //*****************************************************************************
  1641. //
  1642. //! Puts the processor into deep-sleep mode.
  1643. //!
  1644. //! This function places the processor into deep-sleep mode; it does not return
  1645. //! until the processor returns to run mode. The peripherals that are enabled
  1646. //! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up
  1647. //! the processor (if automatic clock gating is enabled with
  1648. //! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
  1649. //! operate).
  1650. //!
  1651. //! \return None.
  1652. //
  1653. //*****************************************************************************
  1654. void
  1655. SysCtlDeepSleep(void)
  1656. {
  1657. //
  1658. // Enable deep-sleep.
  1659. //
  1660. HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
  1661. //
  1662. // Wait for an interrupt.
  1663. //
  1664. CPUwfi();
  1665. //
  1666. // Disable deep-sleep so that a future sleep works correctly.
  1667. //
  1668. HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
  1669. }
  1670. //*****************************************************************************
  1671. //
  1672. //! Gets the reason for a reset.
  1673. //!
  1674. //! This function returns the reason(s) for a reset. Because the reset
  1675. //! reasons are sticky until either cleared by software or a power-on reset,
  1676. //! multiple reset reasons may be returned if multiple resets have occurred.
  1677. //! The reset reason is a logical OR of \b SYSCTL_CAUSE_HSRVREQ,
  1678. //! \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1, \b SYSCTL_CAUSE_SW,
  1679. //! \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR,
  1680. //! and/or \b SYSCTL_CAUSE_EXT.
  1681. //!
  1682. //! \return Returns the reason(s) for a reset.
  1683. //
  1684. //*****************************************************************************
  1685. uint32_t
  1686. SysCtlResetCauseGet(void)
  1687. {
  1688. //
  1689. // Return the reset reasons.
  1690. //
  1691. return(HWREG(SYSCTL_RESC));
  1692. }
  1693. //*****************************************************************************
  1694. //
  1695. //! Clears reset reasons.
  1696. //!
  1697. //! \param ui32Causes are the reset causes to be cleared; must be a logical OR
  1698. //! of \b SYSCTL_CAUSE_HSRVREQ, \b SYSCTL_CAUSE_HIB, \b SYSCTL_CAUSE_WDOG1,
  1699. //! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG0, \b SYSCTL_CAUSE_BOR,
  1700. //! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
  1701. //!
  1702. //! This function clears the specified sticky reset reasons. Once cleared,
  1703. //! another reset for the same reason can be detected, and a reset for a
  1704. //! different reason can be distinguished (instead of having two reset causes
  1705. //! set). If the reset reason is used by an application, all reset causes
  1706. //! should be cleared after they are retrieved with SysCtlResetCauseGet().
  1707. //!
  1708. //! \return None.
  1709. //
  1710. //*****************************************************************************
  1711. void
  1712. SysCtlResetCauseClear(uint32_t ui32Causes)
  1713. {
  1714. //
  1715. // Clear the given reset reasons.
  1716. //
  1717. HWREG(SYSCTL_RESC) &= ~(ui32Causes);
  1718. }
  1719. //*****************************************************************************
  1720. //
  1721. //! Provides a small delay.
  1722. //!
  1723. //! \param ui32Count is the number of delay loop iterations to perform.
  1724. //!
  1725. //! This function provides a means of generating a delay by executing a simple
  1726. //! 3 instruction cycle loop a given number of times. It is written in
  1727. //! assembly to keep the loop instruction count consistent across tool chains.
  1728. //!
  1729. //! It is important to note that this function does NOT provide an accurate
  1730. //! timing mechanism. Although the delay loop is 3 instruction cycles long,
  1731. //! the execution time of the loop will vary dramatically depending upon the
  1732. //! application's interrupt environment (the loop will be interrupted unless
  1733. //! run with interrupts disabled and this is generally an unwise thing to do)
  1734. //! and also the current system clock rate and flash timings (wait states and
  1735. //! the operation of the prefetch buffer affect the timing).
  1736. //!
  1737. //! For better accuracy, the ROM version of this function may be used. This
  1738. //! version will not suffer from flash- and prefect buffer-related timing
  1739. //! variability but will still be delayed by interrupt service routines.
  1740. //!
  1741. //! For best accuracy, a system timer should be used with code either polling
  1742. //! for a particular timer value being exceeded or processing the timer
  1743. //! interrupt to determine when a particular time period has elapsed.
  1744. //!
  1745. //! \return None.
  1746. //
  1747. //*****************************************************************************
  1748. #if defined(ewarm) || defined(DOXYGEN)
  1749. void
  1750. SysCtlDelay(uint32_t ui32Count)
  1751. {
  1752. __asm(" subs r0, #1\n"
  1753. " bne.n SysCtlDelay\n"
  1754. " bx lr");
  1755. }
  1756. #endif
  1757. #if defined(codered) || defined(gcc) || defined(sourcerygxx)
  1758. void __attribute__((naked))
  1759. SysCtlDelay(uint32_t ui32Count)
  1760. {
  1761. __asm(" subs r0, #1\n"
  1762. " bne SysCtlDelay\n"
  1763. " bx lr");
  1764. }
  1765. #endif
  1766. #if defined(rvmdk) || defined(__ARMCC_VERSION)
  1767. __asm void
  1768. SysCtlDelay(uint32_t ui32Count)
  1769. {
  1770. subs r0, #1;
  1771. bne SysCtlDelay;
  1772. bx lr;
  1773. }
  1774. #endif
  1775. //
  1776. // For CCS implement this function in pure assembly. This prevents the TI
  1777. // compiler from doing funny things with the optimizer.
  1778. //
  1779. #if defined(ccs)
  1780. __asm(" .sect \".text:SysCtlDelay\"\n"
  1781. " .clink\n"
  1782. " .thumbfunc SysCtlDelay\n"
  1783. " .thumb\n"
  1784. " .global SysCtlDelay\n"
  1785. "SysCtlDelay:\n"
  1786. " subs r0, #1\n"
  1787. " bne.n SysCtlDelay\n"
  1788. " bx lr\n");
  1789. #endif
  1790. //*****************************************************************************
  1791. //
  1792. //! Sets the configuration of the main oscillator (MOSC) control.
  1793. //!
  1794. //! \param ui32Config is the required configuration of the MOSC control.
  1795. //!
  1796. //! This function configures the control of the main oscillator. The
  1797. //! \e ui32Config is specified as the logical OR of the following values:
  1798. //!
  1799. //! - \b SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that
  1800. //! detects a failure of the main oscillator (such as a loss of the clock).
  1801. //! - \b SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an
  1802. //! interrupt instead of resetting the processor.
  1803. //! - \b SYSCTL_MOSC_NO_XTAL indicates that there is no crystal or oscillator
  1804. //! connected to the OSC0/OSC1 pins, allowing power consumption to be
  1805. //! reduced.
  1806. //! - \b SYSCTL_MOSC_PWR_DIS disable power to the main oscillator. If this
  1807. //! parameter is not specified, the MOSC input remains powered.
  1808. //! - \b SYSCTL_MOSC_LOWFREQ MOSC is less than 10 MHz.
  1809. //! - \b SYSCTL_MOSC_HIGHFREQ MOSC is greater than 10 MHz.
  1810. //! - \b SYSCTL_MOSC_SESRC specifies that the MOSC is a single-ended
  1811. //! oscillator connected to OSC0. If this parameter is not specified, the
  1812. //! input is assumed to be a crystal.
  1813. //!
  1814. //! \note The availability of MOSC control varies based on the Tiva part
  1815. //! in use. Please consult the data sheet for the part you are using to
  1816. //! determine whether this support is available. In addition, the capability
  1817. //! of MOSC control varies based on the Tiva part in use.
  1818. //!
  1819. //! \return None.
  1820. //
  1821. //*****************************************************************************
  1822. void
  1823. SysCtlMOSCConfigSet(uint32_t ui32Config)
  1824. {
  1825. //
  1826. // Configure the MOSC control.
  1827. //
  1828. HWREG(SYSCTL_MOSCCTL) = ui32Config;
  1829. }
  1830. //*****************************************************************************
  1831. //
  1832. //! Calibrates the precision internal oscillator.
  1833. //!
  1834. //! \param ui32Type is the type of calibration to perform.
  1835. //!
  1836. //! This function performs a calibration of the PIOSC. There are three types
  1837. //! of calibration available; the desired calibration type as specified in
  1838. //! \e ui32Type is one of:
  1839. //!
  1840. //! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the
  1841. //! 32-kHz clock from the hibernate module as a reference. This type is
  1842. //! only possible on parts that have a hibernate module, and then only if
  1843. //! it is enabled, a 32.768-kHz clock source is attached to the XOSC0/1
  1844. //! pins and the hibernate module's RTC is also enabled.
  1845. //!
  1846. //! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory
  1847. //! provided calibration.
  1848. //!
  1849. //! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied
  1850. //! value. The value to be used is ORed into the lower 7-bits of this value,
  1851. //! with 0x40 being the ``nominal'' value (in other words, if everything were
  1852. //! perfect, 0x40 provides exactly 16 MHz). Values larger than 0x40
  1853. //! slow down PIOSC, and values smaller than 0x40 speed up PIOSC.
  1854. //!
  1855. //! \return Returns 1 if the calibration was successful and 0 if it failed.
  1856. //
  1857. //*****************************************************************************
  1858. uint32_t
  1859. SysCtlPIOSCCalibrate(uint32_t ui32Type)
  1860. {
  1861. //
  1862. // Perform the requested calibration. If performing user calibration, the
  1863. // UTEN bit must be set with one write, then the UT field in a second
  1864. // write, and the UPDATE bit in a final write. For other calibration
  1865. // types, a single write to set UPDATE or CAL is all that is required.
  1866. //
  1867. if(ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UPDATE))
  1868. {
  1869. HWREG(SYSCTL_PIOSCCAL) = ui32Type & SYSCTL_PIOSCCAL_UTEN;
  1870. HWREG(SYSCTL_PIOSCCAL) =
  1871. ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UT_M);
  1872. }
  1873. HWREG(SYSCTL_PIOSCCAL) = ui32Type;
  1874. //
  1875. // See if an automatic calibration was requested.
  1876. //
  1877. if(ui32Type & SYSCTL_PIOSCCAL_CAL)
  1878. {
  1879. //
  1880. // Wait for the automatic calibration to complete.
  1881. //
  1882. while((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) == 0)
  1883. {
  1884. }
  1885. //
  1886. // If the automatic calibration failed, return an error.
  1887. //
  1888. if((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) !=
  1889. SYSCTL_PIOSCSTAT_CRPASS)
  1890. {
  1891. return(0);
  1892. }
  1893. }
  1894. //
  1895. // The calibration was successful.
  1896. //
  1897. return(1);
  1898. }
  1899. //*****************************************************************************
  1900. //
  1901. //! Sets the type of reset issued due to certain reset events.
  1902. //!
  1903. //! \param ui32Behavior specifies the types of resets for each of the
  1904. //! configurable reset events.
  1905. //!
  1906. //! This function sets the types of reset issued when a configurable reset
  1907. //! event occurs. The reset events that are configurable are: Watchdog 0 or 1,
  1908. //! a brown out and the external RSTn pin. The valid actions are either a
  1909. //! system reset or a full POR sequence. See the data sheet for more
  1910. //! information on the differences between a full POR and a system reset. All
  1911. //! reset behaviors can be configured with a single call using the logical OR
  1912. //! of the values defined below. Any reset option that is not specifically set
  1913. //! remains configured for its default behavior. Either POR or system reset
  1914. //! can be selected for each reset cause.
  1915. //!
  1916. //! Valid values are logical combinations of the following:
  1917. //!
  1918. //! - \b SYSCTL_ONRST_WDOG0_POR configures a Watchdog 0 reset to perform a full
  1919. //! POR.
  1920. //! - \b SYSCTL_ONRST_WDOG0_SYS configures a Watchdog 0 reset to perform a
  1921. //! system reset.
  1922. //! - \b SYSCTL_ONRST_WDOG1_POR configures a Watchdog 1 reset to perform a full
  1923. //! POR.
  1924. //! - \b SYSCTL_ONRST_WDOG1_SYS configures a Watchdog 1 reset to perform a
  1925. //! system reset.
  1926. //! - \b SYSCTL_ONRST_BOR_POR configures a brown-out reset to perform a full
  1927. //! POR.
  1928. //! - \b SYSCTL_ONRST_BOR_SYS configures a brown-out reset to perform a system
  1929. //! reset.
  1930. //! - \b SYSCTL_ONRST_EXT_POR configures an external pin reset to perform a
  1931. //! full POR.
  1932. //! - \b SYSCTL_ONRST_EXT_SYS configures an external pin reset to perform a
  1933. //! system reset.
  1934. //!
  1935. //! \b Example: Set Watchdog 0 reset to trigger a POR and a brown-out reset
  1936. //! to trigger a system reset while leaving the remaining resets with their
  1937. //! default behaviors.
  1938. //!
  1939. //! \verbatim
  1940. //! SysCtlResetBehaviorSet(SYSCTL_ONRST_WDOG0_POR | SYSCTL_ONRST_BOR_SYS);
  1941. //! \endverbatim
  1942. //!
  1943. //! \note This function cannot be used with TM4C123 devices.
  1944. //!
  1945. //! \return None.
  1946. //
  1947. //*****************************************************************************
  1948. void
  1949. SysCtlResetBehaviorSet(uint32_t ui32Behavior)
  1950. {
  1951. HWREG(SYSCTL_RESBEHAVCTL) = ui32Behavior;
  1952. }
  1953. //*****************************************************************************
  1954. //
  1955. //! Returns the current types of reset issued due to reset events.
  1956. //!
  1957. //! This function returns the types of resets issued when a configurable reset
  1958. //! occurs. The value returned is a logical OR combination of the valid values
  1959. //! that are described in the documentation for the \e ui32Behavior parameter
  1960. //! of the SysCtlResetBehaviorSet() function.
  1961. //!
  1962. //! \note This function should only be used with Flurry-class devices.
  1963. //!
  1964. //! \return The reset behaviors for all configurable resets.
  1965. //
  1966. //*****************************************************************************
  1967. uint32_t
  1968. SysCtlResetBehaviorGet(void)
  1969. {
  1970. return(HWREG(SYSCTL_RESBEHAVCTL));
  1971. }
  1972. //*****************************************************************************
  1973. //
  1974. //! Configures the system clock.
  1975. //!
  1976. //! \param ui32Config is the required configuration of the device clocking.
  1977. //! \param ui32SysClock is the requested processor frequency.
  1978. //!
  1979. //! This function configures the main system clocking for the device. The
  1980. //! input frequency, oscillator source, whether or not to enable the PLL, and
  1981. //! the system clock divider are all configured with this function. This
  1982. //! function configures the system frequency to the closest available divisor
  1983. //! of one of the fixed PLL VCO settings provided in the \e ui32Config
  1984. //! parameter. The caller sets the \e ui32SysClock parameter to request the
  1985. //! system clock frequency, and this function then attempts to match this using
  1986. //! the values provided in the \e ui32Config parameter. If this function
  1987. //! cannot exactly match the requested frequency, it picks the closest
  1988. //! frequency that is lower than the requested frequency. The \e ui32Config
  1989. //! parameter provides the remaining configuration options using a set of
  1990. //! defines that are a logical OR of several different values, many of which
  1991. //! are grouped into sets where only one of the set can be chosen. This
  1992. //! function returns the current system frequency which may not match the
  1993. //! requested frequency.
  1994. //!
  1995. //! If the application is using an external crystal then the frequency is
  1996. //! set by using one of the following values:
  1997. //! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_8MHZ,
  1998. //! \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, \b SYSCTL_XTAL_16MHZ,
  1999. //! \b SYSCTL_XTAL_18MHZ, \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or
  2000. //! \b SYSCTL_XTAL_25MHz.
  2001. //!
  2002. //! The oscillator source is chosen with one of the following values:
  2003. //!
  2004. //! - \b SYSCTL_OSC_MAIN to use an external crystal or oscillator.
  2005. //! - \b SYSCTL_OSC_INT to use the 16-MHz precision internal oscillator.
  2006. //! - \b SYSCTL_OSC_INT30 to use the internal low frequency oscillator.
  2007. //! - \b SYSCTL_OSC_EXT32 to use the hibernate modules 32.786-kHz oscillator.
  2008. //! This option is only available on devices that include the hibernation
  2009. //! module.
  2010. //!
  2011. //! The system clock source is chosen with one of the following values:
  2012. //!
  2013. //! - \b SYSCTL_USE_PLL is used to select the PLL output as the system clock.
  2014. //! - \b SYSCTL_USE_OSC is used to choose one of the oscillators as the
  2015. //! system clock.
  2016. //!
  2017. //! The PLL VCO frequency is chosen with one of the the following values:
  2018. //!
  2019. //! - \b SYSCTL_CFG_VCO_480 to set the PLL VCO output to 480-MHz
  2020. //! - \b SYSCTL_CFG_VCO_320 to set the PLL VCO output to 320-MHz
  2021. //!
  2022. //! Example: Configure the system clocking to be 40 MHz with a 320-MHz PLL
  2023. //! setting using the 16-MHz internal oscillator.
  2024. //!
  2025. //! \verbatim
  2026. //! SysCtlClockFreqSet(SYSCTL_OSC_INT | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_320,
  2027. //! 40000000);
  2028. //! \endverbatim
  2029. //!
  2030. //! \note This function cannot be used with TM4C123 devices. For TM4C123
  2031. //! devices use the SysCtlClockSet() function.
  2032. //!
  2033. //! \return The actual configured system clock frequency in Hz or zero if the
  2034. //! value could not be changed due to a parameter error or PLL lock failure.
  2035. //
  2036. //*****************************************************************************
  2037. uint32_t
  2038. SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock)
  2039. {
  2040. int32_t i32Timeout, i32VCOIdx, i32XtalIdx;
  2041. uint32_t ui32MOSCCTL;
  2042. uint32_t ui32Delay;
  2043. uint32_t ui32SysDiv, ui32Osc, ui32OscSelect, ui32RSClkConfig;
  2044. //
  2045. // TM4C123 devices should not use this function.
  2046. //
  2047. if(CLASS_IS_TM4C123)
  2048. {
  2049. return(0);
  2050. }
  2051. //
  2052. // Get the index of the crystal from the ui32Config parameter.
  2053. //
  2054. i32XtalIdx = SysCtlXtalCfgToIndex(ui32Config);
  2055. //
  2056. // Determine which non-PLL source was selected.
  2057. //
  2058. if((ui32Config & 0x38) == SYSCTL_OSC_INT)
  2059. {
  2060. //
  2061. // Use the nominal frequency for the PIOSC oscillator and set the
  2062. // crystal select.
  2063. //
  2064. ui32Osc = 16000000;
  2065. ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC;
  2066. ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_PIOSC;
  2067. //
  2068. // Force the crystal index to the value for 16-MHz.
  2069. //
  2070. i32XtalIdx = SysCtlXtalCfgToIndex(SYSCTL_XTAL_16MHZ);
  2071. }
  2072. else if((ui32Config & 0x38) == SYSCTL_OSC_INT30)
  2073. {
  2074. //
  2075. // Use the nominal frequency for the low frequency oscillator.
  2076. //
  2077. ui32Osc = 30000;
  2078. ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_LFIOSC;
  2079. }
  2080. else if((ui32Config & 0x38) == (SYSCTL_OSC_EXT32 & 0x38))
  2081. {
  2082. //
  2083. // Use the RTC frequency.
  2084. //
  2085. ui32Osc = 32768;
  2086. ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_RTC;
  2087. }
  2088. else if((ui32Config & 0x38) == SYSCTL_OSC_MAIN)
  2089. {
  2090. //
  2091. // Bounds check the source frequency for the main oscillator. The is
  2092. // because the PLL tables in the g_pppui32XTALtoVCO structure range
  2093. // from 5MHz to 25MHz.
  2094. //
  2095. if((i32XtalIdx > (SysCtlXtalCfgToIndex(SYSCTL_XTAL_25MHZ))) ||
  2096. (i32XtalIdx < (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ))))
  2097. {
  2098. return(0);
  2099. }
  2100. ui32Osc = g_pui32Xtals[i32XtalIdx];
  2101. //
  2102. // Set the PLL source select to MOSC.
  2103. //
  2104. ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_MOSC;
  2105. ui32OscSelect |= SYSCTL_RSCLKCFG_PLLSRC_MOSC;
  2106. //
  2107. // Clear MOSC power down, high oscillator range setting, and no crystal
  2108. // present setting.
  2109. //
  2110. ui32MOSCCTL = HWREG(SYSCTL_MOSCCTL) &
  2111. ~(SYSCTL_MOSCCTL_OSCRNG | SYSCTL_MOSCCTL_PWRDN |
  2112. SYSCTL_MOSCCTL_NOXTAL);
  2113. //
  2114. // Increase the drive strength for MOSC of 10 MHz and above.
  2115. //
  2116. if(i32XtalIdx >= (SysCtlXtalCfgToIndex(SYSCTL_XTAL_10MHZ) -
  2117. (SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ))))
  2118. {
  2119. ui32MOSCCTL |= SYSCTL_MOSCCTL_OSCRNG;
  2120. }
  2121. HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL;
  2122. //
  2123. // Timeout using the legacy delay value.
  2124. //
  2125. ui32Delay = 524288;
  2126. while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0)
  2127. {
  2128. ui32Delay--;
  2129. if(ui32Delay == 0)
  2130. {
  2131. break;
  2132. }
  2133. }
  2134. //
  2135. // If the main oscillator failed to start up then do not switch to
  2136. // it and return.
  2137. //
  2138. if(ui32Delay == 0)
  2139. {
  2140. return(0);
  2141. }
  2142. }
  2143. else
  2144. {
  2145. //
  2146. // This was an invalid request because no oscillator source was
  2147. // indicated.
  2148. //
  2149. ui32Osc = 0;
  2150. ui32OscSelect = SYSCTL_RSCLKCFG_OSCSRC_PIOSC;
  2151. }
  2152. //
  2153. // Check if the running with the PLL enabled was requested.
  2154. //
  2155. if((ui32Config & SYSCTL_USE_OSC) == SYSCTL_USE_PLL)
  2156. {
  2157. //
  2158. // ui32Config must be SYSCTL_OSC_MAIN or SYSCTL_OSC_INT.
  2159. //
  2160. if(((ui32Config & 0x38) != SYSCTL_OSC_MAIN) &&
  2161. ((ui32Config & 0x38) != SYSCTL_OSC_INT))
  2162. {
  2163. return(0);
  2164. }
  2165. //
  2166. // Get the VCO index out of the ui32Config parameter.
  2167. //
  2168. i32VCOIdx = (ui32Config >> 24) & 7;
  2169. //
  2170. // Check that the VCO index is not out of bounds.
  2171. //
  2172. ASSERT(i32VCOIdx < MAX_VCO_ENTRIES);
  2173. //
  2174. // Set the memory timings for the maximum external frequency since
  2175. // this could be a switch to PIOSC or possibly to MOSC which can be
  2176. // up to 25MHz.
  2177. //
  2178. HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(25000000);
  2179. //
  2180. // Clear the old PLL divider and source in case it was set.
  2181. //
  2182. ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG) &
  2183. ~(SYSCTL_RSCLKCFG_PSYSDIV_M |
  2184. SYSCTL_RSCLKCFG_OSCSRC_M |
  2185. SYSCTL_RSCLKCFG_PLLSRC_M | SYSCTL_RSCLKCFG_USEPLL);
  2186. //
  2187. // Update the memory timings to match running from PIOSC.
  2188. //
  2189. ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
  2190. //
  2191. // Update clock configuration to switch back to PIOSC.
  2192. //
  2193. HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
  2194. //
  2195. // The table starts at 5 MHz so modify the index to match this.
  2196. //
  2197. i32XtalIdx -= SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ);
  2198. //
  2199. // Calculate the System divider such that we get a frequency that is
  2200. // the closest to the requested frequency without going over.
  2201. //
  2202. ui32SysDiv = (g_pui32VCOFrequencies[i32VCOIdx] + ui32SysClock - 1) /
  2203. ui32SysClock;
  2204. //
  2205. // Set the oscillator source.
  2206. //
  2207. HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect;
  2208. //
  2209. // Set the M, N and Q values provided from the table and preserve
  2210. // the power state of the main PLL.
  2211. //
  2212. HWREG(SYSCTL_PLLFREQ1) =
  2213. g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1];
  2214. HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv);
  2215. HWREG(SYSCTL_PLLFREQ0) =
  2216. (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] |
  2217. (HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR));
  2218. //
  2219. // Calculate the actual system clock as PSYSDIV is always div-by 2.
  2220. //
  2221. ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / 2;
  2222. //
  2223. // Set the Flash and EEPROM timing values.
  2224. //
  2225. HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock);
  2226. //
  2227. // Check if the PLL is already powered up.
  2228. //
  2229. if(HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR)
  2230. {
  2231. //
  2232. // Trigger the PLL to lock to the new frequency.
  2233. //
  2234. HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ;
  2235. }
  2236. else
  2237. {
  2238. //
  2239. // Power up the PLL.
  2240. //
  2241. HWREG(SYSCTL_PLLFREQ0) |= SYSCTL_PLLFREQ0_PLLPWR;
  2242. }
  2243. //
  2244. // Wait until the PLL has locked.
  2245. //
  2246. for(i32Timeout = 32768; i32Timeout > 0; i32Timeout--)
  2247. {
  2248. if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK))
  2249. {
  2250. break;
  2251. }
  2252. }
  2253. //
  2254. // If the loop above did not timeout then switch over to the PLL
  2255. //
  2256. if(i32Timeout)
  2257. {
  2258. ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
  2259. ui32RSClkConfig |= (1 << SYSCTL_RSCLKCFG_PSYSDIV_S) |
  2260. ui32OscSelect | SYSCTL_RSCLKCFG_USEPLL;
  2261. ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
  2262. //
  2263. // Set the new clock configuration.
  2264. //
  2265. HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
  2266. }
  2267. else
  2268. {
  2269. ui32SysClock = 0;
  2270. }
  2271. }
  2272. else
  2273. {
  2274. //
  2275. // Set the Flash and EEPROM timing values for PIOSC.
  2276. //
  2277. HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(16000000);
  2278. //
  2279. // Make sure that the PLL is powered down since it is not being used.
  2280. //
  2281. HWREG(SYSCTL_PLLFREQ0) &= ~SYSCTL_PLLFREQ0_PLLPWR;
  2282. //
  2283. // Clear the old PLL divider and source in case it was set.
  2284. //
  2285. ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
  2286. ui32RSClkConfig &= ~(SYSCTL_RSCLKCFG_OSYSDIV_M |
  2287. SYSCTL_RSCLKCFG_OSCSRC_M |
  2288. SYSCTL_RSCLKCFG_USEPLL);
  2289. //
  2290. // Update the memory timings.
  2291. //
  2292. ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
  2293. //
  2294. // Set the new clock configuration.
  2295. //
  2296. HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
  2297. //
  2298. // If zero given as the system clock then default to divide by 1.
  2299. //
  2300. if(ui32SysClock == 0)
  2301. {
  2302. ui32SysDiv = 0;
  2303. }
  2304. else
  2305. {
  2306. //
  2307. // Calculate the System divider based on the requested
  2308. // frequency.
  2309. //
  2310. ui32SysDiv = ui32Osc / ui32SysClock;
  2311. //
  2312. // If the system divisor is not already zero, subtract one to
  2313. // set the value in the register which requires the value to
  2314. // be n-1.
  2315. //
  2316. if(ui32SysDiv != 0)
  2317. {
  2318. ui32SysDiv -= 1;
  2319. }
  2320. //
  2321. // Calculate the system clock.
  2322. //
  2323. ui32SysClock = ui32Osc / (ui32SysDiv + 1);
  2324. }
  2325. //
  2326. // Set the memory timing values for the new system clock.
  2327. //
  2328. HWREG(SYSCTL_MEMTIM0) = _SysCtlMemTimingGet(ui32SysClock);
  2329. //
  2330. // Set the new system clock values.
  2331. //
  2332. ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
  2333. ui32RSClkConfig |= (ui32SysDiv << SYSCTL_RSCLKCFG_OSYSDIV_S) |
  2334. ui32OscSelect;
  2335. //
  2336. // Update the memory timings.
  2337. //
  2338. ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU;
  2339. //
  2340. // Set the new clock configuration.
  2341. //
  2342. HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig;
  2343. }
  2344. //
  2345. // Finally change the OSCSRC back to PIOSC
  2346. //
  2347. HWREG(SYSCTL_RSCLKCFG) &= ~(SYSCTL_RSCLKCFG_OSCSRC_M);
  2348. return(ui32SysClock);
  2349. }
  2350. //*****************************************************************************
  2351. //
  2352. //! Sets the clocking of the device.
  2353. //!
  2354. //! \param ui32Config is the required configuration of the device clocking.
  2355. //!
  2356. //! This function configures the clocking of the device. The input crystal
  2357. //! frequency, oscillator to be used, use of the PLL, and the system clock
  2358. //! divider are all configured with this function.
  2359. //!
  2360. //! The \e ui32Config parameter is the logical OR of several different values,
  2361. //! many of which are grouped into sets where only one can be chosen.
  2362. //!
  2363. //! The system clock divider is chosen with one of the following values:
  2364. //! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_2_5,
  2365. //! \b SYSCTL_SYSDIV_3, ... \b SYSCTL_SYSDIV_63_5, \b SYSCTL_SYSDIV_64.
  2366. //!
  2367. //! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or
  2368. //! \b SYSCTL_USE_OSC.
  2369. //!
  2370. //! The external crystal frequency is chosen with one of the following values:
  2371. //! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ,
  2372. //! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ,
  2373. //! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ,
  2374. //! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ,
  2375. //! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ,
  2376. //! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ,
  2377. //! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz.
  2378. //! Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in
  2379. //! operation.
  2380. //!
  2381. //! The oscillator source is chosen with one of the following values:
  2382. //! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4,
  2383. //! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only
  2384. //! available on devices with the hibernate module, and then only when the
  2385. //! hibernate module has been enabled.
  2386. //!
  2387. //! The internal and main oscillators are disabled with the
  2388. //! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.
  2389. //! The external oscillator must be enabled in order to use an external clock
  2390. //! source. Note that attempts to disable the oscillator used to clock the
  2391. //! device is prevented by the hardware.
  2392. //!
  2393. //! To clock the system from an external source (such as an external crystal
  2394. //! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the
  2395. //! system from the main oscillator, use \b SYSCTL_USE_OSC \b |
  2396. //! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use
  2397. //! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate
  2398. //! crystal with one of the \b SYSCTL_XTAL_xxx values.
  2399. //!
  2400. //! \note This function should only be called on TM4C123 devices. For
  2401. //! all other devices use the SysCtlClockFreqSet() function.
  2402. //!
  2403. //! \note If selecting the PLL as the system clock source (that is, via
  2404. //! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to
  2405. //! determine when the PLL has locked. If an interrupt handler for the
  2406. //! system control interrupt is in place, and it responds to and clears the
  2407. //! PLL lock interrupt, this function delays until its timeout has occurred
  2408. //! instead of completing as soon as PLL lock is achieved.
  2409. //!
  2410. //! \return None.
  2411. //
  2412. //*****************************************************************************
  2413. void
  2414. SysCtlClockSet(uint32_t ui32Config)
  2415. {
  2416. uint32_t ui32Delay, ui32RCC, ui32RCC2;
  2417. //
  2418. // Get the current value of the RCC and RCC2 registers.
  2419. //
  2420. ui32RCC = HWREG(SYSCTL_RCC);
  2421. ui32RCC2 = HWREG(SYSCTL_RCC2);
  2422. //
  2423. // Bypass the PLL and system clock dividers for now.
  2424. //
  2425. ui32RCC |= SYSCTL_RCC_BYPASS;
  2426. ui32RCC &= ~(SYSCTL_RCC_USESYSDIV);
  2427. ui32RCC2 |= SYSCTL_RCC2_BYPASS2;
  2428. //
  2429. // Write the new RCC value.
  2430. //
  2431. HWREG(SYSCTL_RCC) = ui32RCC;
  2432. HWREG(SYSCTL_RCC2) = ui32RCC2;
  2433. //
  2434. // See if the oscillator needs to be enabled.
  2435. //
  2436. if((ui32RCC & SYSCTL_RCC_MOSCDIS) && !(ui32Config & SYSCTL_MAIN_OSC_DIS))
  2437. {
  2438. //
  2439. // Make sure that the required oscillators are enabled. For now, the
  2440. // previously enabled oscillators must be enabled along with the newly
  2441. // requested oscillators.
  2442. //
  2443. ui32RCC &= (~SYSCTL_RCC_MOSCDIS | (ui32Config & SYSCTL_MAIN_OSC_DIS));
  2444. //
  2445. // Clear the MOSC power up raw interrupt status to be sure it is not
  2446. // set when waiting below.
  2447. //
  2448. HWREG(SYSCTL_MISC) = SYSCTL_MISC_MOSCPUPMIS;
  2449. //
  2450. // Write the new RCC value.
  2451. //
  2452. HWREG(SYSCTL_RCC) = ui32RCC;
  2453. //
  2454. // Timeout using the legacy delay value.
  2455. //
  2456. ui32Delay = 524288;
  2457. while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0)
  2458. {
  2459. ui32Delay--;
  2460. if(ui32Delay == 0)
  2461. {
  2462. break;
  2463. }
  2464. }
  2465. //
  2466. // If the main oscillator failed to start up then do not switch to
  2467. // it and return.
  2468. //
  2469. if(ui32Delay == 0)
  2470. {
  2471. return;
  2472. }
  2473. }
  2474. //
  2475. // Set the new crystal value and oscillator source. Because the OSCSRC2
  2476. // field in RCC2 overlaps the XTAL field in RCC, the OSCSRC field has a
  2477. // special encoding within ui32Config to avoid the overlap.
  2478. //
  2479. ui32RCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M);
  2480. ui32RCC |= ui32Config & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M);
  2481. ui32RCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M);
  2482. ui32RCC2 |= ui32Config & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M);
  2483. ui32RCC2 |= (ui32Config & 0x00000008) << 3;
  2484. //
  2485. // Write the new RCC value.
  2486. //
  2487. HWREG(SYSCTL_RCC) = ui32RCC;
  2488. HWREG(SYSCTL_RCC2) = ui32RCC2;
  2489. //
  2490. // Set the PLL configuration.
  2491. //
  2492. ui32RCC &= ~SYSCTL_RCC_PWRDN;
  2493. ui32RCC |= ui32Config & SYSCTL_RCC_PWRDN;
  2494. ui32RCC2 &= ~SYSCTL_RCC2_PWRDN2;
  2495. ui32RCC2 |= ui32Config & SYSCTL_RCC2_PWRDN2;
  2496. //
  2497. // Clear the PLL lock interrupt.
  2498. //
  2499. HWREG(SYSCTL_MISC) = SYSCTL_MISC_PLLLMIS;
  2500. //
  2501. // Write the new RCC value.
  2502. //
  2503. if(ui32RCC2 & SYSCTL_RCC2_USERCC2)
  2504. {
  2505. HWREG(SYSCTL_RCC2) = ui32RCC2;
  2506. HWREG(SYSCTL_RCC) = ui32RCC;
  2507. }
  2508. else
  2509. {
  2510. HWREG(SYSCTL_RCC) = ui32RCC;
  2511. HWREG(SYSCTL_RCC2) = ui32RCC2;
  2512. }
  2513. //
  2514. // Set the requested system divider and disable the appropriate
  2515. // oscillators. This value is not written immediately.
  2516. //
  2517. ui32RCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
  2518. SYSCTL_RCC_MOSCDIS);
  2519. ui32RCC |= ui32Config & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
  2520. SYSCTL_RCC_MOSCDIS);
  2521. ui32RCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
  2522. ui32RCC2 |= ui32Config & SYSCTL_RCC2_SYSDIV2_M;
  2523. if(ui32Config & SYSCTL_RCC2_DIV400)
  2524. {
  2525. ui32RCC |= SYSCTL_RCC_USESYSDIV;
  2526. ui32RCC2 &= ~(SYSCTL_RCC_USESYSDIV);
  2527. ui32RCC2 |= ui32Config & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB);
  2528. }
  2529. else
  2530. {
  2531. ui32RCC2 &= ~(SYSCTL_RCC2_DIV400);
  2532. }
  2533. //
  2534. // See if the PLL output is being used to clock the system.
  2535. //
  2536. if(!(ui32Config & SYSCTL_RCC_BYPASS))
  2537. {
  2538. //
  2539. // Wait until the PLL has locked.
  2540. //
  2541. for(ui32Delay = 32768; ui32Delay > 0; ui32Delay--)
  2542. {
  2543. if((HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK))
  2544. {
  2545. break;
  2546. }
  2547. }
  2548. //
  2549. // Enable use of the PLL.
  2550. //
  2551. ui32RCC &= ~(SYSCTL_RCC_BYPASS);
  2552. ui32RCC2 &= ~(SYSCTL_RCC2_BYPASS2);
  2553. }
  2554. //
  2555. // Write the final RCC value.
  2556. //
  2557. HWREG(SYSCTL_RCC) = ui32RCC;
  2558. HWREG(SYSCTL_RCC2) = ui32RCC2;
  2559. //
  2560. // Delay for a little bit so that the system divider takes effect.
  2561. //
  2562. SysCtlDelay(16);
  2563. }
  2564. //*****************************************************************************
  2565. //
  2566. //! Gets the processor clock rate.
  2567. //!
  2568. //! This function determines the clock rate of the processor clock, which is
  2569. //! also the clock rate of the peripheral modules (with the exception of
  2570. //! PWM, which has its own clock divider; other peripherals may have different
  2571. //! clocking, see the device data sheet for details).
  2572. //!
  2573. //! \note This cannot return accurate results if SysCtlClockSet() has not
  2574. //! been called to configure the clocking of the device, or if the device is
  2575. //! directly clocked from a crystal (or a clock source) that is not one of the
  2576. //! supported crystal frequencies. In the latter case, this function should be
  2577. //! modified to directly return the correct system clock rate.
  2578. //!
  2579. //! \note This function can only be called on TM4C123 devices. For TM4C129
  2580. //! devices, the return value from SysCtlClockFreqSet() indicates the system
  2581. //! clock frequency.
  2582. //!
  2583. //! \return The processor clock rate for TM4C123 devices only.
  2584. //
  2585. //*****************************************************************************
  2586. uint32_t
  2587. SysCtlClockGet(void)
  2588. {
  2589. uint32_t ui32RCC, ui32RCC2, ui32PLL, ui32Clk, ui32Max;
  2590. uint32_t ui32PLL1;
  2591. //
  2592. // This function is only valid on TM4C123 devices.
  2593. //
  2594. ASSERT(CLASS_IS_TM4C123);
  2595. //
  2596. // Read RCC and RCC2.
  2597. //
  2598. ui32RCC = HWREG(SYSCTL_RCC);
  2599. ui32RCC2 = HWREG(SYSCTL_RCC2);
  2600. //
  2601. // Get the base clock rate.
  2602. //
  2603. switch((ui32RCC2 & SYSCTL_RCC2_USERCC2) ?
  2604. (ui32RCC2 & SYSCTL_RCC2_OSCSRC2_M) :
  2605. (ui32RCC & SYSCTL_RCC_OSCSRC_M))
  2606. {
  2607. //
  2608. // The main oscillator is the clock source. Determine its rate from
  2609. // the crystal setting field.
  2610. //
  2611. case SYSCTL_RCC_OSCSRC_MAIN:
  2612. {
  2613. ui32Clk = g_pui32Xtals[(ui32RCC & SYSCTL_RCC_XTAL_M) >>
  2614. SYSCTL_RCC_XTAL_S];
  2615. break;
  2616. }
  2617. //
  2618. // The internal oscillator is the source clock.
  2619. //
  2620. case SYSCTL_RCC_OSCSRC_INT:
  2621. {
  2622. //
  2623. // The internal oscillator on all devices is 16 MHz.
  2624. //
  2625. ui32Clk = 16000000;
  2626. break;
  2627. }
  2628. //
  2629. // The internal oscillator divided by four is the source clock.
  2630. //
  2631. case SYSCTL_RCC_OSCSRC_INT4:
  2632. {
  2633. //
  2634. // The internal oscillator on all devices is 16 MHz.
  2635. //
  2636. ui32Clk = 16000000 / 4;
  2637. break;
  2638. }
  2639. //
  2640. // The internal 30-KHz oscillator is the source clock.
  2641. //
  2642. case SYSCTL_RCC_OSCSRC_30:
  2643. {
  2644. //
  2645. // The internal 30-KHz oscillator has an accuracy of +/- 30%.
  2646. //
  2647. ui32Clk = 30000;
  2648. break;
  2649. }
  2650. //
  2651. // The 32.768-KHz clock from the hibernate module is the source clock.
  2652. //
  2653. case SYSCTL_RCC2_OSCSRC2_32:
  2654. {
  2655. ui32Clk = 32768;
  2656. break;
  2657. }
  2658. //
  2659. // An unknown setting, so return a zero clock (that is, an unknown
  2660. // clock rate).
  2661. //
  2662. default:
  2663. {
  2664. return(0);
  2665. }
  2666. }
  2667. //
  2668. // Default the maximum frequency to the maximum 32-bit unsigned value.
  2669. //
  2670. ui32Max = 0xffffffff;
  2671. //
  2672. // See if the PLL is being used.
  2673. //
  2674. if(((ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
  2675. !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) ||
  2676. (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) && !(ui32RCC & SYSCTL_RCC_BYPASS)))
  2677. {
  2678. //
  2679. // Read the two PLL frequency registers. The formula for a
  2680. // TM4C123 device is "(xtal * m) / ((q + 1) * (n + 1))".
  2681. //
  2682. ui32PLL = HWREG(SYSCTL_PLLFREQ0);
  2683. ui32PLL1 = HWREG(SYSCTL_PLLFREQ1);
  2684. //
  2685. // Divide the input clock by the dividers.
  2686. //
  2687. ui32Clk /= ((((ui32PLL1 & SYSCTL_PLLFREQ1_Q_M) >>
  2688. SYSCTL_PLLFREQ1_Q_S) + 1) *
  2689. (((ui32PLL1 & SYSCTL_PLLFREQ1_N_M) >>
  2690. SYSCTL_PLLFREQ1_N_S) + 1) * 2);
  2691. //
  2692. // Multiply the clock by the multiplier, which is split into an
  2693. // integer part and a fractional part.
  2694. //
  2695. ui32Clk = ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MINT_M) >>
  2696. SYSCTL_PLLFREQ0_MINT_S)) +
  2697. ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MFRAC_M) >>
  2698. SYSCTL_PLLFREQ0_MFRAC_S)) >> 10));
  2699. //
  2700. // Force the system divider to be enabled. It is always used when
  2701. // using the PLL, but in some cases it does not read as being enabled.
  2702. //
  2703. ui32RCC |= SYSCTL_RCC_USESYSDIV;
  2704. //
  2705. // Calculate the maximum system frequency.
  2706. //
  2707. switch(HWREG(SYSCTL_DC1) & SYSCTL_DC1_MINSYSDIV_M)
  2708. {
  2709. case SYSCTL_DC1_MINSYSDIV_80:
  2710. {
  2711. ui32Max = 80000000;
  2712. break;
  2713. }
  2714. case SYSCTL_DC1_MINSYSDIV_50:
  2715. {
  2716. ui32Max = 50000000;
  2717. break;
  2718. }
  2719. case SYSCTL_DC1_MINSYSDIV_40:
  2720. {
  2721. ui32Max = 40000000;
  2722. break;
  2723. }
  2724. case SYSCTL_DC1_MINSYSDIV_25:
  2725. {
  2726. ui32Max = 25000000;
  2727. break;
  2728. }
  2729. case SYSCTL_DC1_MINSYSDIV_20:
  2730. {
  2731. ui32Max = 20000000;
  2732. break;
  2733. }
  2734. default:
  2735. {
  2736. break;
  2737. }
  2738. }
  2739. }
  2740. //
  2741. // See if the system divider is being used.
  2742. //
  2743. if(ui32RCC & SYSCTL_RCC_USESYSDIV)
  2744. {
  2745. //
  2746. // Adjust the clock rate by the system clock divider.
  2747. //
  2748. if(ui32RCC2 & SYSCTL_RCC2_USERCC2)
  2749. {
  2750. if((ui32RCC2 & SYSCTL_RCC2_DIV400) &&
  2751. (((ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
  2752. !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) ||
  2753. (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
  2754. !(ui32RCC & SYSCTL_RCC_BYPASS))))
  2755. {
  2756. ui32Clk = ((ui32Clk * 2) / (((ui32RCC2 &
  2757. (SYSCTL_RCC2_SYSDIV2_M |
  2758. SYSCTL_RCC2_SYSDIV2LSB)) >>
  2759. (SYSCTL_RCC2_SYSDIV2_S - 1)) +
  2760. 1));
  2761. }
  2762. else
  2763. {
  2764. ui32Clk /= (((ui32RCC2 & SYSCTL_RCC2_SYSDIV2_M) >>
  2765. SYSCTL_RCC2_SYSDIV2_S) + 1);
  2766. }
  2767. }
  2768. else
  2769. {
  2770. ui32Clk /= (((ui32RCC & SYSCTL_RCC_SYSDIV_M) >>
  2771. SYSCTL_RCC_SYSDIV_S) + 1);
  2772. }
  2773. }
  2774. //
  2775. // Limit the maximum clock to the maximum clock frequency.
  2776. //
  2777. if(ui32Max < ui32Clk)
  2778. {
  2779. ui32Clk = ui32Max;
  2780. }
  2781. //
  2782. // Return the computed clock rate.
  2783. //
  2784. return(ui32Clk);
  2785. }
  2786. //*****************************************************************************
  2787. //
  2788. //! Sets the clocking of the device while in deep-sleep mode.
  2789. //!
  2790. //! \param ui32Config is the required configuration of the device clocking
  2791. //! while in deep-sleep mode.
  2792. //!
  2793. //! This function configures the clocking of the device while in deep-sleep
  2794. //! mode. The oscillator to be used and the system clock divider are
  2795. //! configured with this function.
  2796. //!
  2797. //! The \e ui32Config parameter is the logical OR of the following values:
  2798. //!
  2799. //! The system clock divider is chosen from one of the following values:
  2800. //! \b SYSCTL_DSLP_DIV_1, \b SYSCTL_DSLP_DIV_2, \b SYSCTL_DSLP_DIV_3, ...
  2801. //! \b SYSCTL_DSLP_DIV_64.
  2802. //!
  2803. //! The oscillator source is chosen from one of the following values:
  2804. //! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30,
  2805. //! or \b SYSCTL_DSLP_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only available on
  2806. //! devices with the hibernation module, and then only when the hibernation
  2807. //! module has been enabled.
  2808. //!
  2809. //! The precision internal oscillator can be powered down in deep-sleep mode by
  2810. //! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is
  2811. //! not powered down if it is required for operation while in deep-sleep
  2812. //! (based on other configuration settings.)
  2813. //!
  2814. //! \note This function should only be called on TM4C123 devices. For
  2815. //! other devices use the SysCtlDeepSleepClockConfigSet() function.
  2816. //!
  2817. //! \note The availability of deep-sleep clocking configuration varies with the
  2818. //! Tiva part in use. Please consult the data sheet for the part you are
  2819. //! using to determine whether this support is available.
  2820. //!
  2821. //! \return None.
  2822. //
  2823. //*****************************************************************************
  2824. void
  2825. SysCtlDeepSleepClockSet(uint32_t ui32Config)
  2826. {
  2827. //
  2828. // Set the deep-sleep clock configuration.
  2829. //
  2830. HWREG(SYSCTL_DSLPCLKCFG) = ui32Config;
  2831. }
  2832. //*****************************************************************************
  2833. //
  2834. //! Sets the clock configuration of the device while in deep-sleep mode.
  2835. //!
  2836. //! \param ui32Div is the clock divider when in deep-sleep mode.
  2837. //! \param ui32Config is the configuration of the device clocking while
  2838. //! in deep-sleep mode.
  2839. //!
  2840. //! This function configures the clocking of the device while in deep-sleep
  2841. //! mode. The \e ui32Config parameter selects the oscillator and the
  2842. //! \e ui32Div parameter sets the clock divider used in deep-sleep mode. The
  2843. //! valid values for the \e ui32Div parameter range from 1 to 1024, however not
  2844. //! all Tiva microcontrollers support this full range. This function
  2845. //! replaces the SysCtlDeepSleepClockSet() function and can be used on
  2846. //! Tiva devices that support deep-sleep mode.
  2847. //!
  2848. //! The oscillator source is chosen from one of the following values:
  2849. //! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30,
  2850. //! or \b SYSCTL_DSLP_OSC_EXT32. The \b SYSCTL_DSLP_OSC_EXT32 option is only
  2851. //! available on devices with the hibernation module, and then only when the
  2852. //! hibernation module is enabled.
  2853. //!
  2854. //! The precision internal oscillator can be powered down in deep-sleep mode by
  2855. //! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is
  2856. //! not powered down if it is required for operation while in deep-sleep
  2857. //! (based on other configuration settings).
  2858. //!
  2859. //! The main oscillator can be powered down in deep-sleep mode by
  2860. //! specifying \b SYSCTL_DSLP_MOSC_PD. The main oscillator is
  2861. //! not powered down if it is required for operation while in deep-sleep
  2862. //! (based on other configuration settings).
  2863. //!
  2864. //! \note The availability of deep-sleep clocking configuration and the
  2865. //! configuration values vary with the Tiva device in use. Please consult
  2866. //! the data sheet for the device you are using to determine whether the
  2867. //! desired configuration options are available and to determine the valid
  2868. //! range for the clock divider.
  2869. //!
  2870. //! \return None.
  2871. //
  2872. //*****************************************************************************
  2873. void
  2874. SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, uint32_t ui32Config)
  2875. {
  2876. uint32_t ui32Value;
  2877. ASSERT(ui32Div != 0);
  2878. if(CLASS_IS_TM4C123)
  2879. {
  2880. //
  2881. // Set the deep-sleep clock configuration.
  2882. //
  2883. HWREG(SYSCTL_DSLPCLKCFG) = (ui32Config & ~SYSCTL_DSLPCLKCFG_D_M) |
  2884. ((ui32Div - 1) << SYSCTL_DSLPCLKCFG_D_S);
  2885. }
  2886. else
  2887. {
  2888. //
  2889. // Initialize the value with the divider.
  2890. //
  2891. ui32Value = ui32Div - 1;
  2892. //
  2893. // Set the clock source selection based on the defines used for
  2894. // SysCtlDeepSleepClockSet() function so that there is some backwards
  2895. // compatibility.
  2896. //
  2897. switch(ui32Config & SYSCTL_DSLPCLKCFG_O_M)
  2898. {
  2899. //
  2900. // Choose the main external oscillator.
  2901. //
  2902. case SYSCTL_DSLP_OSC_MAIN:
  2903. {
  2904. ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_MOSC;
  2905. break;
  2906. }
  2907. //
  2908. // Choose the low frequency oscillator.
  2909. //
  2910. case SYSCTL_DSLP_OSC_INT30:
  2911. {
  2912. ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC;
  2913. break;
  2914. }
  2915. //
  2916. // Choose the low frequency oscillator.
  2917. //
  2918. case SYSCTL_DSLP_OSC_EXT32:
  2919. {
  2920. ui32Value |= SYSCTL_DSCLKCFG_DSOSCSRC_RTC;
  2921. break;
  2922. }
  2923. //
  2924. // The zero value uses the PIOSC as the clock source.
  2925. //
  2926. case SYSCTL_DSLP_OSC_INT:
  2927. default:
  2928. {
  2929. break;
  2930. }
  2931. }
  2932. //
  2933. // Set the PIOSC power down bit.
  2934. //
  2935. if(ui32Config & SYSCTL_DSLP_PIOSC_PD)
  2936. {
  2937. ui32Value |= SYSCTL_DSCLKCFG_PIOSCPD;
  2938. }
  2939. //
  2940. // Set the PIOSC power down bit.
  2941. //
  2942. if(ui32Config & SYSCTL_DSLP_MOSC_PD)
  2943. {
  2944. ui32Value |= SYSCTL_DSCLKCFG_MOSCDPD;
  2945. }
  2946. //
  2947. // Update the deep-sleep clock configuration.
  2948. //
  2949. HWREG(SYSCTL_DSCLKCFG) = ui32Value;
  2950. }
  2951. }
  2952. //*****************************************************************************
  2953. //
  2954. //! Sets the PWM clock configuration.
  2955. //!
  2956. //! \param ui32Config is the configuration for the PWM clock; it must be one of
  2957. //! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
  2958. //! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
  2959. //! \b SYSCTL_PWMDIV_64.
  2960. //!
  2961. //! This function configures the rate of the clock provided to the PWM module
  2962. //! as a ratio of the processor clock. This clock is used by the PWM module to
  2963. //! generate PWM signals; its rate forms the basis for all PWM signals.
  2964. //!
  2965. //! \note This function should only be used with TM4C123 devices. For
  2966. //! other TM4C devices, the PWMClockSet() function should be used.
  2967. //!
  2968. //! \note The clocking of the PWM is dependent on the system clock rate as
  2969. //! configured by SysCtlClockSet().
  2970. //!
  2971. //! \return None.
  2972. //
  2973. //*****************************************************************************
  2974. void
  2975. SysCtlPWMClockSet(uint32_t ui32Config)
  2976. {
  2977. //
  2978. // Check the arguments.
  2979. //
  2980. ASSERT((ui32Config == SYSCTL_PWMDIV_1) ||
  2981. (ui32Config == SYSCTL_PWMDIV_2) ||
  2982. (ui32Config == SYSCTL_PWMDIV_4) ||
  2983. (ui32Config == SYSCTL_PWMDIV_8) ||
  2984. (ui32Config == SYSCTL_PWMDIV_16) ||
  2985. (ui32Config == SYSCTL_PWMDIV_32) ||
  2986. (ui32Config == SYSCTL_PWMDIV_64));
  2987. //
  2988. // Check that there is a PWM block on this part.
  2989. //
  2990. ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1));
  2991. //
  2992. // Set the PWM clock configuration into the run-mode clock configuration
  2993. // register.
  2994. //
  2995. HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) &
  2996. ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) |
  2997. ui32Config);
  2998. }
  2999. //*****************************************************************************
  3000. //
  3001. //! Gets the current PWM clock configuration.
  3002. //!
  3003. //! This function returns the current PWM clock configuration.
  3004. //!
  3005. //! \return Returns the current PWM clock configuration; is one of
  3006. //! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
  3007. //! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
  3008. //! \b SYSCTL_PWMDIV_64.
  3009. //!
  3010. //! \note This function should only be used with TM4C123 devices. For
  3011. //! other TM4C devices, the PWMClockGet() function should be used.
  3012. //
  3013. //*****************************************************************************
  3014. uint32_t
  3015. SysCtlPWMClockGet(void)
  3016. {
  3017. //
  3018. // Check that there is a PWM block on this part.
  3019. //
  3020. ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1));
  3021. //
  3022. // Return the current PWM clock configuration. Make sure that
  3023. // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled.
  3024. //
  3025. if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV))
  3026. {
  3027. //
  3028. // The divider is not active so reflect this in the value we return.
  3029. //
  3030. return(SYSCTL_PWMDIV_1);
  3031. }
  3032. else
  3033. {
  3034. //
  3035. // The divider is active so directly return the masked register value.
  3036. //
  3037. return(HWREG(SYSCTL_RCC) &
  3038. (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M));
  3039. }
  3040. }
  3041. //*****************************************************************************
  3042. //
  3043. //! Enables access to a GPIO peripheral via the AHB.
  3044. //!
  3045. //! \param ui32GPIOPeripheral is the GPIO peripheral to enable.
  3046. //!
  3047. //! This function is used to enable the specified GPIO peripheral to be
  3048. //! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced
  3049. //! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access,
  3050. //! the \b _AHB_BASE form of the base address should be used for GPIO
  3051. //! functions. For example, instead of using \b GPIO_PORTA_BASE as the base
  3052. //! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead.
  3053. //!
  3054. //! The \e ui32GPIOPeripheral argument must be only one of the following
  3055. //! values:
  3056. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  3057. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  3058. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ.
  3059. //!
  3060. //! \note On some devices, all GPIO ports are only available on AHB.
  3061. //!
  3062. //! \return None.
  3063. //
  3064. //*****************************************************************************
  3065. void
  3066. SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral)
  3067. {
  3068. //
  3069. // Check the arguments.
  3070. //
  3071. ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
  3072. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
  3073. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
  3074. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
  3075. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
  3076. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
  3077. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
  3078. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
  3079. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
  3080. //
  3081. // Enable this GPIO for AHB access.
  3082. //
  3083. HWREG(SYSCTL_GPIOHBCTL) |= (1 << (ui32GPIOPeripheral & 0xF));
  3084. }
  3085. //*****************************************************************************
  3086. //
  3087. //! Disables access to a GPIO peripheral via the AHB.
  3088. //!
  3089. //! \param ui32GPIOPeripheral is the GPIO peripheral to disable.
  3090. //!
  3091. //! This function disables the specified GPIO peripheral for access from the
  3092. //! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed
  3093. //! from the legacy Advanced Peripheral Bus (APB).
  3094. //!
  3095. //! The \b ui32GPIOPeripheral argument must be only one of the following
  3096. //! values:
  3097. //! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
  3098. //! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
  3099. //! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ.
  3100. //!
  3101. //! \note Some devices allow disabling AHB access to GPIO ports that are only
  3102. //! present on the AHB. Disabling AHB access to these ports will disable
  3103. //! access to these GPIO ports. On some devices, all GPIO ports are only
  3104. //! available on AHB.
  3105. //!
  3106. //! \return None.
  3107. //
  3108. //*****************************************************************************
  3109. void
  3110. SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral)
  3111. {
  3112. //
  3113. // Check the arguments.
  3114. //
  3115. ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
  3116. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
  3117. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
  3118. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
  3119. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
  3120. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
  3121. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
  3122. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
  3123. (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
  3124. //
  3125. // Disable this GPIO for AHB access.
  3126. //
  3127. HWREG(SYSCTL_GPIOHBCTL) &= ~(1 << (ui32GPIOPeripheral & 0xF));
  3128. }
  3129. //*****************************************************************************
  3130. //
  3131. //! Powers up the USB PLL.
  3132. //!
  3133. //! This function enables the USB controller's PLL, which is used by its
  3134. //! physical layer. This call is necessary before connecting to any external
  3135. //! devices.
  3136. //!
  3137. //! \note This function should only be called on TM4C123 devices.
  3138. //!
  3139. //! \return None.
  3140. //
  3141. //*****************************************************************************
  3142. void
  3143. SysCtlUSBPLLEnable(void)
  3144. {
  3145. //
  3146. // Turn on the USB PLL.
  3147. //
  3148. HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN;
  3149. }
  3150. //*****************************************************************************
  3151. //
  3152. //! Powers down the USB PLL.
  3153. //!
  3154. //! This function disables the USB controller's PLL, which is used by its
  3155. //! physical layer. The USB registers are still accessible, but the physical
  3156. //! layer no longer functions.
  3157. //!
  3158. //! \note This function should only be called on TM4C123 devices.
  3159. //!
  3160. //! \return None.
  3161. //
  3162. //*****************************************************************************
  3163. void
  3164. SysCtlUSBPLLDisable(void)
  3165. {
  3166. //
  3167. // Turn off the USB PLL.
  3168. //
  3169. HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN;
  3170. }
  3171. //*****************************************************************************
  3172. //
  3173. //! Configures the response to system voltage events.
  3174. //!
  3175. //! \param ui32Config holds the configuration options for the voltage events.
  3176. //!
  3177. //! This function configures the response to voltage-related events.
  3178. //! These events are triggered when the voltage rails drop below certain
  3179. //! levels. The \e ui32Config parameter provides the configuration for the
  3180. //! voltage events and is a combination of the \b SYSCTL_VEVENT_* values.
  3181. //!
  3182. //! The response to a brown out on the VDDA rail is set by using one of the
  3183. //! following values:
  3184. //! - \b SYSCTL_VEVENT_VDDABO_NONE - There is no action taken on a VDDA
  3185. //! brown out.
  3186. //! - \b SYSCTL_VEVENT_VDDABO_INT - A system interrupt is generated when a
  3187. //! VDDA brown out occurs.
  3188. //! - \b SYSCTL_VEVENT_VDDABO_NMI - An NMI is generated when a VDDA brown out
  3189. //! occurs.
  3190. //! - \b SYSCTL_VEVENT_VDDABO_RST - A reset is generated when a VDDA brown out
  3191. //! occurs. The type of reset that is generated is controller by the
  3192. //! \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet()
  3193. //! function.
  3194. //!
  3195. //! The response to a brown out on the VDD rail is set by using one of the
  3196. //! following values:
  3197. //! - \b SYSCTL_VEVENT_VDDBO_NONE - There is no action taken on a VDD
  3198. //! brown out.
  3199. //! - \b SYSCTL_VEVENT_VDDBO_INT - A system interrupt is generated when a
  3200. //! VDD brown out occurs.
  3201. //! - \b SYSCTL_VEVENT_VDDBO_NMI - An NMI is generated when a VDD brown out
  3202. //! occurs.
  3203. //! - \b SYSCTL_VEVENT_VDDBO_RST - A reset is generated when a VDD brown out
  3204. //! occurs. The type of reset that is generated is controller by the
  3205. //! \b SYSCTL_ONRST_BOR_* setting passed into the SysCtlResetBehaviorSet()
  3206. //! function.
  3207. //!
  3208. //! \b Example: Configure the voltage events to trigger an interrupt on a VDDA
  3209. //! brown out, an NMI on a VDDC brown out and a reset on a VDD brown out.
  3210. //!
  3211. //! \verbatim
  3212. //!
  3213. //! //
  3214. //! // Configure the BOR rest to trigger a full POR. This is needed because
  3215. //! // the SysCtlVoltageEventConfig() call is triggering a reset so the type
  3216. //! // of reset is specified by this call.
  3217. //! //
  3218. //! SysCtlResetBehaviorSet(SYSCTL_ONRST_BOR_POR);
  3219. //!
  3220. //! //
  3221. //! // Trigger an interrupt on a VDDA brown out and a reset on a VDD brown out.
  3222. //! //
  3223. //! SysCtlVoltageEventConfig(SYSCTL_VEVENT_VDDABO_INT |
  3224. //! SYSCTL_VEVENT_VDDBO_RST);
  3225. //! \endverbatim
  3226. //!
  3227. //! \return None.
  3228. //
  3229. //*****************************************************************************
  3230. void
  3231. SysCtlVoltageEventConfig(uint32_t ui32Config)
  3232. {
  3233. //
  3234. // Set the requested events.
  3235. //
  3236. HWREG(SYSCTL_PTBOCTL) = ui32Config;
  3237. }
  3238. //*****************************************************************************
  3239. //
  3240. //! Returns the voltage event status.
  3241. //!
  3242. //! This function returns the voltage event status for the system controller.
  3243. //! The value returned is a logical OR of the following values:
  3244. //! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail.
  3245. //! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail.
  3246. //!
  3247. //! The values returned from this function can be passed to the
  3248. //! SysCtlVoltageEventClear() to clear the current voltage event status.
  3249. //! Because voltage events are not cleared due to a reset, the voltage event
  3250. //! status must be cleared by calling SysCtlVoltageEventClear().
  3251. //!
  3252. //! \b Example: Clear the current voltage event status.
  3253. //!
  3254. //! \verbatim
  3255. //! uint32_t ui32VoltageEvents;
  3256. //!
  3257. //! //
  3258. //! // Read the current voltage event status.
  3259. //! //
  3260. //! ui32VoltageEvents = SysCtlVoltageEventStatus();
  3261. //!
  3262. //! //
  3263. //! // Clear all the current voltage events.
  3264. //! //
  3265. //! SysCtlVoltageEventClear(ui32VoltageEvents);
  3266. //! \endverbatim
  3267. //!
  3268. //! \return The current voltage event status.
  3269. //!
  3270. //! \note The availability of voltage events varies with the Tiva part
  3271. //! in use. Please consult the data sheet for the part you are using to
  3272. //! determine which interrupt sources are available.
  3273. //
  3274. //*****************************************************************************
  3275. uint32_t
  3276. SysCtlVoltageEventStatus(void)
  3277. {
  3278. //
  3279. // Return the current voltage event status.
  3280. //
  3281. return(HWREG(SYSCTL_PWRTC));
  3282. }
  3283. //*****************************************************************************
  3284. //
  3285. //! Clears the voltage event status.
  3286. //!
  3287. //! \param ui32Status is a bit mask of the voltage events to clear.
  3288. //!
  3289. //! This function clears the current voltage events status for the values
  3290. //! specified in the \e ui32Status parameter. The \e ui32Status value must be
  3291. //! a logical OR of the following values:
  3292. //! - \b SYSCTL_VESTAT_VDDBOR a brown-out event occurred on the VDD rail.
  3293. //! - \b SYSCTL_VESTAT_VDDABOR a brown-out event occurred on the VDDA rail.
  3294. //!
  3295. //! \b Example: Clear the current voltage event status.
  3296. //!
  3297. //! \verbatim
  3298. //! //
  3299. //! // Clear all the current voltage events.
  3300. //! //
  3301. //! SysCtlVoltageEventClear(SysCtlVoltageEventStatus());
  3302. //! \endverbatim
  3303. //!
  3304. //! \note The availability of voltage event status varies with the
  3305. //! Tiva part in use. Please consult the data sheet for the part you are
  3306. //! using to determine which interrupt sources are available.
  3307. //!
  3308. //! \return None.
  3309. //
  3310. //*****************************************************************************
  3311. void
  3312. SysCtlVoltageEventClear(uint32_t ui32Status)
  3313. {
  3314. //
  3315. // Clear the requested voltage events.
  3316. //
  3317. HWREG(SYSCTL_PWRTC) |= ui32Status;
  3318. }
  3319. //*****************************************************************************
  3320. //
  3321. //! Gets the effective VCO frequency.
  3322. //!
  3323. //! \param ui32Crystal holds the crystal value definition from \b sysctl.h
  3324. //! such as \b SYSCTL_XTAL_25MHZ.
  3325. //! \param pui32VCOFrequency is a pointer to the storage location which holds
  3326. //! value of the VCO computed.
  3327. //!
  3328. //! This function calculates the VCO of the PLL before the system divider is
  3329. //! applied
  3330. //!
  3331. //! \return \b true if the PLL is configured correctly and a VCO is valid or
  3332. //! \b false if the device is not TM4C129x or the PLL is not used
  3333. //
  3334. //*****************************************************************************
  3335. bool
  3336. SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency)
  3337. {
  3338. int32_t i32XtalIdx;
  3339. uint32_t ui32RSClkConfig, ui32PLLFreq0, ui32PLLFreq1, ui32Osc;
  3340. uint32_t ui32MInt, ui32MFrac, ui32NDiv, ui32QDiv, ui32TempVCO;
  3341. //
  3342. // Check if TM4C123 device is being used. should not use this function.
  3343. //
  3344. if(CLASS_IS_TM4C123)
  3345. {
  3346. //
  3347. // Return error if TM4C123.
  3348. //
  3349. *pui32VCOFrequency = 0;
  3350. return(false);
  3351. }
  3352. //
  3353. // Read the RSCLKCFG register to determine if PLL is being used.
  3354. //
  3355. ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG);
  3356. //
  3357. // Check if PLL is used.
  3358. //
  3359. if((ui32RSClkConfig & SYSCTL_RSCLKCFG_USEPLL) != SYSCTL_RSCLKCFG_USEPLL)
  3360. {
  3361. //
  3362. // Return error if PLL is not used.
  3363. //
  3364. *pui32VCOFrequency = 0;
  3365. return(false);
  3366. }
  3367. //
  3368. // Get the index of the crystal from the ui32Config parameter.
  3369. //
  3370. i32XtalIdx = SysCtlXtalCfgToIndex(ui32Crystal);
  3371. //
  3372. // Get the value of the crystal frequency based on the index
  3373. //
  3374. ui32Osc = g_pui32Xtals[i32XtalIdx];
  3375. //
  3376. // Read the PLLFREQ0 and PLLFREQ1 registers to get information on the
  3377. // MINT, MFRAC, N and Q values of the PLL
  3378. //
  3379. ui32PLLFreq0 = HWREG(SYSCTL_PLLFREQ0);
  3380. ui32PLLFreq1 = HWREG(SYSCTL_PLLFREQ1);
  3381. ui32MInt = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MINT_M) >>
  3382. SYSCTL_PLLFREQ0_MINT_S;
  3383. ui32MFrac = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MFRAC_M) >>
  3384. SYSCTL_PLLFREQ0_MFRAC_S;
  3385. ui32NDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_N_M) >>
  3386. SYSCTL_PLLFREQ1_N_S;
  3387. ui32QDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_Q_M) >>
  3388. SYSCTL_PLLFREQ1_Q_S;
  3389. //
  3390. // Calculate the VCO at the output of the PLL
  3391. //
  3392. ui32TempVCO = (ui32Osc * ui32MInt) + ((ui32Osc * ui32MFrac) / 1024);
  3393. ui32TempVCO /= ((ui32NDiv + 1) * (ui32QDiv + 1));
  3394. *pui32VCOFrequency = ui32TempVCO;
  3395. return(true);
  3396. }
  3397. //*****************************************************************************
  3398. //
  3399. //! Returns the current NMI status.
  3400. //!
  3401. //! This function returns the NMI status for the system controller. The valid
  3402. //! values for the \e ui32Ints parameter are a logical OR of the following
  3403. //! values:
  3404. //! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not
  3405. //! start.
  3406. //! - \b SYSCTL_NMI_TAMPER a tamper event has been detected.
  3407. //! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout.
  3408. //! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout.
  3409. //! - \b SYSCTL_NMI_POWER a power event occurred.
  3410. //! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted.
  3411. //!
  3412. //! \b Example: Clear all current NMI status flags.
  3413. //!
  3414. //! \verbatim
  3415. //!
  3416. //! //
  3417. //! // Clear all the current NMI sources.
  3418. //! //
  3419. //! SysCtlNMIClear(SysCtlNMIStatus());
  3420. //! \endverbatim
  3421. //!
  3422. //! \note The availability of the NMI status varies with the Tiva part in
  3423. //! use. Please consult the data sheet for the part you are using to determine
  3424. //! which interrupt sources are available.
  3425. //!
  3426. //! \return The current NMI status.
  3427. //
  3428. //*****************************************************************************
  3429. uint32_t
  3430. SysCtlNMIStatus(void)
  3431. {
  3432. return(HWREG(SYSCTL_NMIC));
  3433. }
  3434. //*****************************************************************************
  3435. //
  3436. //! Clears NMI sources.
  3437. //!
  3438. //! \param ui32Ints is a bit mask of the non-maskable interrupt sources.
  3439. //!
  3440. //! This function clears the current NMI status specified in the \e ui32Ints
  3441. //! parameter. The valid values for the \e ui32Ints parameter are a logical OR
  3442. //! of the following values:
  3443. //! - \b SYSCTL_NMI_MOSCFAIL the main oscillator is not present or did not
  3444. //! start.
  3445. //! - \b SYSCTL_NMI_TAMPER a tamper event has been detected.
  3446. //! - \b SYSCTL_NMI_WDT0 watchdog 0 generated a timeout.
  3447. //! - \b SYSCTL_NMI_WDT1 watchdog 1 generated a timeout.
  3448. //! - \b SYSCTL_NMI_POWER a power event occurred.
  3449. //! - \b SYSCTL_NMI_EXTERNAL an external NMI pin asserted.
  3450. //!
  3451. //! \b Example: Clear all current NMI status flags.
  3452. //!
  3453. //! \verbatim
  3454. //!
  3455. //! //
  3456. //! // Clear all the current NMI sources.
  3457. //! //
  3458. //! SysCtlNMIClear(SysCtlNMIStatus());
  3459. //! \endverbatim
  3460. //!
  3461. //! \note The availability of the NMI status varies with the Tiva part in
  3462. //! use. Please consult the data sheet for the part you are using to determine
  3463. //! which interrupt sources are available.
  3464. //!
  3465. //! \return None.
  3466. //
  3467. //*****************************************************************************
  3468. void
  3469. SysCtlNMIClear(uint32_t ui32Ints)
  3470. {
  3471. //
  3472. // Clear the requested interrupt sources.
  3473. //
  3474. HWREG(SYSCTL_NMIC) &= ~ui32Ints;
  3475. }
  3476. //*****************************************************************************
  3477. //
  3478. //! Configures and enables or disables the clock output on the DIVSCLK pin.
  3479. //!
  3480. //! \param ui32Config holds the configuration options including enabling or
  3481. //! disabling the clock output on the DIVSCLK pin.
  3482. //! \param ui32Div is the divisor for the clock selected in the \e ui32Config
  3483. //! parameter.
  3484. //!
  3485. //! This function selects the source for the DIVSCLK, enables or disables
  3486. //! the clock output and provides an output divider value. The \e ui32Div
  3487. //! parameter specifies the divider for the selected clock source and has a
  3488. //! valid range of 1-256. The \e ui32Config parameter configures
  3489. //! the DIVSCLK output based on the following settings:
  3490. //!
  3491. //! The first setting allows the output to be enabled or disabled.
  3492. //! - \b SYSCTL_CLKOUT_EN - enable the DIVSCLK output.
  3493. //! - \b SYSCTL_CLKOUT_DIS - disable the DIVSCLK output (default).
  3494. //!
  3495. //! The next group of settings selects the source for the DIVSCLK.
  3496. //! - \b SYSCTL_CLKOUT_SYSCLK - use the current system clock as the
  3497. //! source (default).
  3498. //! - \b SYSCTL_CLKOUT_PIOSC - use the PIOSC as the source.
  3499. //! - \b SYSCTL_CLKOUT_MOSC - use the MOSC as the source.
  3500. //!
  3501. //! \b Example: Enable the PIOSC divided by 4 as the DIVSCLK output.
  3502. //!
  3503. //! \verbatim
  3504. //!
  3505. //! //
  3506. //! // Enable the PIOSC divided by 4 as the DIVSCLK output.
  3507. //! //
  3508. //! SysCtlClockOutConfig(SYSCTL_DIVSCLK_EN | SYSCTL_DIVSCLK_SRC_PIOSC, 4);
  3509. //! \endverbatim
  3510. //!
  3511. //! \note The availability of the DIVSCLK output varies with the Tiva part
  3512. //! in use. Please consult the data sheet for the part you are using to
  3513. //! determine which interrupt sources are available.
  3514. //!
  3515. //! \return None.
  3516. //
  3517. //*****************************************************************************
  3518. void
  3519. SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div)
  3520. {
  3521. ASSERT(ui32Div != 0);
  3522. ASSERT((ui32Config & ~(SYSCTL_CLKOUT_EN | SYSCTL_CLKOUT_DIS |
  3523. SYSCTL_CLKOUT_SYSCLK | SYSCTL_CLKOUT_PIOSC |
  3524. SYSCTL_CLKOUT_MOSC)) == 0);
  3525. //
  3526. // Set the requested configuration and divisor.
  3527. //
  3528. HWREG(SYSCTL_DIVSCLK) = ui32Config | ((ui32Div - 1) &
  3529. SYSCTL_DIVSCLK_DIV_M);
  3530. }
  3531. //*****************************************************************************
  3532. //
  3533. //! Configures the alternate peripheral clock source.
  3534. //!
  3535. //! \param ui32Config holds the configuration options for the alternate
  3536. //! peripheral clock.
  3537. //!
  3538. //! This function configures the alternate peripheral clock. The alternate
  3539. //! peripheral clock is used to provide a known clock in all operating modes
  3540. //! to peripherals that support using the alternate peripheral clock as an
  3541. //! input clock. The \e ui32Config parameter value provides the clock input
  3542. //! source using one of the following values:
  3543. //! - \b SYSCTL_ALTCLK_PIOSC - use the PIOSC as the alternate clock
  3544. //! source (default).
  3545. //! - \b SYSCTL_ALTCLK_RTCOSC - use the Hibernate module RTC clock as the
  3546. //! alternate clock source.
  3547. //! - \b SYSCTL_ALTCLK_LFIOSC - use the low-frequency internal oscillator as
  3548. //! the alternate clock source.
  3549. //!
  3550. //! \b Example: Select the Hibernate module RTC clock as the alternate clock
  3551. //! source.
  3552. //!
  3553. //! \verbatim
  3554. //!
  3555. //! //
  3556. //! // Select the Hibernate module RTC clock as the alternate clock source.
  3557. //! //
  3558. //! SysCtlAltClkConfig(SYSCTL_ALTCLK_RTCOSC);
  3559. //! \endverbatim
  3560. //!
  3561. //! \note The availability of the alternate peripheral clock varies with the
  3562. //! Tiva part in use. Please consult the data sheet for the part you are
  3563. //! using to determine which interrupt sources are available.
  3564. //!
  3565. //! \return None.
  3566. //
  3567. //*****************************************************************************
  3568. void
  3569. SysCtlAltClkConfig(uint32_t ui32Config)
  3570. {
  3571. //
  3572. // Set the requested configuration and divisor.
  3573. //
  3574. HWREG(SYSCTL_ALTCLKCFG) = ui32Config;
  3575. }
  3576. //*****************************************************************************
  3577. //
  3578. // Close the Doxygen group.
  3579. //! @}
  3580. //
  3581. //*****************************************************************************