2837xD_FLASH_IQMATH_lnk_cpu1.cmd 6.0 KB

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  1. MEMORY
  2. {
  3. PAGE 0 : /* Program Memory */
  4. /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
  5. /* BEGIN is used for the "boot to SARAM" bootloader mode */
  6. BEGIN : origin = 0x080000, length = 0x000002
  7. RAMM0 : origin = 0x000122, length = 0x0002DE
  8. RAMD0 : origin = 0x00B000, length = 0x000800
  9. RAMLS0 : origin = 0x008000, length = 0x000800
  10. RAMLS1 : origin = 0x008800, length = 0x000800
  11. RAMLS2 : origin = 0x009000, length = 0x000800
  12. RAMLS3 : origin = 0x009800, length = 0x000800
  13. RAMLS4 : origin = 0x00A000, length = 0x000800
  14. RESET : origin = 0x3FFFC0, length = 0x000002
  15. /* Flash sectors */
  16. FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
  17. FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
  18. FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
  19. FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
  20. FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
  21. FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
  22. FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
  23. FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
  24. FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
  25. FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
  26. FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
  27. FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
  28. FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
  29. FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
  30. PAGE 1 : /* Data Memory */
  31. /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
  32. BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
  33. RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
  34. RAMD1 : origin = 0x00B800, length = 0x000800
  35. RAMLS5 : origin = 0x00A800, length = 0x000800
  36. RAMGS0 : origin = 0x00C000, length = 0x001000
  37. RAMGS1 : origin = 0x00D000, length = 0x001000
  38. RAMGS2 : origin = 0x00E000, length = 0x001000
  39. RAMGS3 : origin = 0x00F000, length = 0x001000
  40. RAMGS4 : origin = 0x010000, length = 0x001000
  41. RAMGS5 : origin = 0x011000, length = 0x001000
  42. RAMGS6 : origin = 0x012000, length = 0x001000
  43. RAMGS7 : origin = 0x013000, length = 0x001000
  44. RAMGS8 : origin = 0x014000, length = 0x001000
  45. RAMGS9 : origin = 0x015000, length = 0x001000
  46. RAMGS10 : origin = 0x016000, length = 0x001000
  47. RAMGS11 : origin = 0x017000, length = 0x001000
  48. RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
  49. RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
  50. RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
  51. RAMGS15 : origin = 0x01B000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
  52. CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
  53. CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
  54. }
  55. SECTIONS
  56. {
  57. /* Allocate program areas: */
  58. .cinit : > FLASHB PAGE = 0, ALIGN(4)
  59. .pinit : > FLASHB, PAGE = 0, ALIGN(4)
  60. .text : > FLASHB PAGE = 0, ALIGN(4)
  61. codestart : > BEGIN PAGE = 0, ALIGN(4)
  62. /* Allocate uninitalized data sections: */
  63. .stack : > RAMM1 PAGE = 1
  64. .ebss : > RAMLS5 PAGE = 1
  65. .esysmem : > RAMLS5 PAGE = 1
  66. /* Initalized sections go in Flash */
  67. .econst : > FLASHB PAGE = 0, ALIGN(4)
  68. .switch : > FLASHB PAGE = 0, ALIGN(4)
  69. .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
  70. Filter_RegsFile : > RAMGS0, PAGE = 1
  71. #ifdef __TI_COMPILER_VERSION__
  72. #if __TI_COMPILER_VERSION__ >= 15009000
  73. .TI.ramfunc : {} LOAD = FLASHD,
  74. RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
  75. LOAD_START(_RamfuncsLoadStart),
  76. LOAD_SIZE(_RamfuncsLoadSize),
  77. LOAD_END(_RamfuncsLoadEnd),
  78. RUN_START(_RamfuncsRunStart),
  79. RUN_SIZE(_RamfuncsRunSize),
  80. RUN_END(_RamfuncsRunEnd),
  81. PAGE = 0, ALIGN(4)
  82. #else
  83. ramfuncs : LOAD = FLASHD,
  84. RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
  85. LOAD_START(_RamfuncsLoadStart),
  86. LOAD_SIZE(_RamfuncsLoadSize),
  87. LOAD_END(_RamfuncsLoadEnd),
  88. RUN_START(_RamfuncsRunStart),
  89. RUN_SIZE(_RamfuncsRunSize),
  90. RUN_END(_RamfuncsRunEnd),
  91. PAGE = 0, ALIGN(4)
  92. #endif
  93. #endif
  94. /* The following section definitions are required when using the IPC API Drivers */
  95. GROUP : > CPU1TOCPU2RAM, PAGE = 1
  96. {
  97. PUTBUFFER
  98. PUTWRITEIDX
  99. GETREADIDX
  100. }
  101. GROUP : > CPU2TOCPU1RAM, PAGE = 1
  102. {
  103. GETBUFFER : TYPE = DSECT
  104. GETWRITEIDX : TYPE = DSECT
  105. PUTREADIDX : TYPE = DSECT
  106. }
  107. /* Allocate IQ math areas: */
  108. IQmath : > FLASHB, PAGE = 0, ALIGN(4) /* Math Code */
  109. IQmathTables : > FLASHC, PAGE = 0, ALIGN(4)
  110. }
  111. /*
  112. //===========================================================================
  113. // End of file.
  114. //===========================================================================
  115. */